2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/ppc/ppc.h"
26 #include "hw/boards.h"
28 #include "hw/char/serial.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
32 #include "exec/address-spaces.h"
37 //#define DEBUG_SERIAL
42 //#define DEBUG_CLOCKS
43 //#define DEBUG_CLOCKS_LL
45 ram_addr_t
ppc405_set_bootinfo (CPUPPCState
*env
, ppc4xx_bd_info_t
*bd
,
48 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
52 /* We put the bd structure at the top of memory */
53 if (bd
->bi_memsize
>= 0x01000000UL
)
54 bdloc
= 0x01000000UL
- sizeof(struct ppc4xx_bd_info_t
);
56 bdloc
= bd
->bi_memsize
- sizeof(struct ppc4xx_bd_info_t
);
57 stl_be_phys(cs
->as
, bdloc
+ 0x00, bd
->bi_memstart
);
58 stl_be_phys(cs
->as
, bdloc
+ 0x04, bd
->bi_memsize
);
59 stl_be_phys(cs
->as
, bdloc
+ 0x08, bd
->bi_flashstart
);
60 stl_be_phys(cs
->as
, bdloc
+ 0x0C, bd
->bi_flashsize
);
61 stl_be_phys(cs
->as
, bdloc
+ 0x10, bd
->bi_flashoffset
);
62 stl_be_phys(cs
->as
, bdloc
+ 0x14, bd
->bi_sramstart
);
63 stl_be_phys(cs
->as
, bdloc
+ 0x18, bd
->bi_sramsize
);
64 stl_be_phys(cs
->as
, bdloc
+ 0x1C, bd
->bi_bootflags
);
65 stl_be_phys(cs
->as
, bdloc
+ 0x20, bd
->bi_ipaddr
);
66 for (i
= 0; i
< 6; i
++) {
67 stb_phys(cs
->as
, bdloc
+ 0x24 + i
, bd
->bi_enetaddr
[i
]);
69 stw_be_phys(cs
->as
, bdloc
+ 0x2A, bd
->bi_ethspeed
);
70 stl_be_phys(cs
->as
, bdloc
+ 0x2C, bd
->bi_intfreq
);
71 stl_be_phys(cs
->as
, bdloc
+ 0x30, bd
->bi_busfreq
);
72 stl_be_phys(cs
->as
, bdloc
+ 0x34, bd
->bi_baudrate
);
73 for (i
= 0; i
< 4; i
++) {
74 stb_phys(cs
->as
, bdloc
+ 0x38 + i
, bd
->bi_s_version
[i
]);
76 for (i
= 0; i
< 32; i
++) {
77 stb_phys(cs
->as
, bdloc
+ 0x3C + i
, bd
->bi_r_version
[i
]);
79 stl_be_phys(cs
->as
, bdloc
+ 0x5C, bd
->bi_plb_busfreq
);
80 stl_be_phys(cs
->as
, bdloc
+ 0x60, bd
->bi_pci_busfreq
);
81 for (i
= 0; i
< 6; i
++) {
82 stb_phys(cs
->as
, bdloc
+ 0x64 + i
, bd
->bi_pci_enetaddr
[i
]);
85 if (flags
& 0x00000001) {
86 for (i
= 0; i
< 6; i
++)
87 stb_phys(cs
->as
, bdloc
+ n
++, bd
->bi_pci_enetaddr2
[i
]);
89 stl_be_phys(cs
->as
, bdloc
+ n
, bd
->bi_opbfreq
);
91 for (i
= 0; i
< 2; i
++) {
92 stl_be_phys(cs
->as
, bdloc
+ n
, bd
->bi_iic_fast
[i
]);
99 /*****************************************************************************/
100 /* Shared peripherals */
102 /*****************************************************************************/
103 /* Peripheral local bus arbitrer */
110 typedef struct ppc4xx_plb_t ppc4xx_plb_t
;
111 struct ppc4xx_plb_t
{
117 static uint32_t dcr_read_plb (void *opaque
, int dcrn
)
134 /* Avoid gcc warning */
142 static void dcr_write_plb (void *opaque
, int dcrn
, uint32_t val
)
149 /* We don't care about the actual parameters written as
150 * we don't manage any priorities on the bus
152 plb
->acr
= val
& 0xF8000000;
164 static void ppc4xx_plb_reset (void *opaque
)
169 plb
->acr
= 0x00000000;
170 plb
->bear
= 0x00000000;
171 plb
->besr
= 0x00000000;
174 static void ppc4xx_plb_init(CPUPPCState
*env
)
178 plb
= g_malloc0(sizeof(ppc4xx_plb_t
));
179 ppc_dcr_register(env
, PLB0_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
180 ppc_dcr_register(env
, PLB0_BEAR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
181 ppc_dcr_register(env
, PLB0_BESR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
182 qemu_register_reset(ppc4xx_plb_reset
, plb
);
185 /*****************************************************************************/
186 /* PLB to OPB bridge */
193 typedef struct ppc4xx_pob_t ppc4xx_pob_t
;
194 struct ppc4xx_pob_t
{
200 static uint32_t dcr_read_pob (void *opaque
, int dcrn
)
217 /* Avoid gcc warning */
225 static void dcr_write_pob (void *opaque
, int dcrn
, uint32_t val
)
245 static void ppc4xx_pob_reset (void *opaque
)
251 pob
->bear
= 0x00000000;
252 pob
->besr0
= 0x0000000;
253 pob
->besr1
= 0x0000000;
256 static void ppc4xx_pob_init(CPUPPCState
*env
)
260 pob
= g_malloc0(sizeof(ppc4xx_pob_t
));
261 ppc_dcr_register(env
, POB0_BEAR
, pob
, &dcr_read_pob
, &dcr_write_pob
);
262 ppc_dcr_register(env
, POB0_BESR0
, pob
, &dcr_read_pob
, &dcr_write_pob
);
263 ppc_dcr_register(env
, POB0_BESR1
, pob
, &dcr_read_pob
, &dcr_write_pob
);
264 qemu_register_reset(ppc4xx_pob_reset
, pob
);
267 /*****************************************************************************/
269 typedef struct ppc4xx_opba_t ppc4xx_opba_t
;
270 struct ppc4xx_opba_t
{
276 static uint32_t opba_readb (void *opaque
, hwaddr addr
)
282 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
300 static void opba_writeb (void *opaque
,
301 hwaddr addr
, uint32_t value
)
306 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
312 opba
->cr
= value
& 0xF8;
315 opba
->pr
= value
& 0xFF;
322 static uint32_t opba_readw (void *opaque
, hwaddr addr
)
327 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
329 ret
= opba_readb(opaque
, addr
) << 8;
330 ret
|= opba_readb(opaque
, addr
+ 1);
335 static void opba_writew (void *opaque
,
336 hwaddr addr
, uint32_t value
)
339 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
342 opba_writeb(opaque
, addr
, value
>> 8);
343 opba_writeb(opaque
, addr
+ 1, value
);
346 static uint32_t opba_readl (void *opaque
, hwaddr addr
)
351 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
353 ret
= opba_readb(opaque
, addr
) << 24;
354 ret
|= opba_readb(opaque
, addr
+ 1) << 16;
359 static void opba_writel (void *opaque
,
360 hwaddr addr
, uint32_t value
)
363 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
366 opba_writeb(opaque
, addr
, value
>> 24);
367 opba_writeb(opaque
, addr
+ 1, value
>> 16);
370 static const MemoryRegionOps opba_ops
= {
372 .read
= { opba_readb
, opba_readw
, opba_readl
, },
373 .write
= { opba_writeb
, opba_writew
, opba_writel
, },
375 .endianness
= DEVICE_NATIVE_ENDIAN
,
378 static void ppc4xx_opba_reset (void *opaque
)
383 opba
->cr
= 0x00; /* No dynamic priorities - park disabled */
387 static void ppc4xx_opba_init(hwaddr base
)
391 opba
= g_malloc0(sizeof(ppc4xx_opba_t
));
393 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
395 memory_region_init_io(&opba
->io
, NULL
, &opba_ops
, opba
, "opba", 0x002);
396 memory_region_add_subregion(get_system_memory(), base
, &opba
->io
);
397 qemu_register_reset(ppc4xx_opba_reset
, opba
);
400 /*****************************************************************************/
401 /* Code decompression controller */
404 /*****************************************************************************/
405 /* Peripheral controller */
406 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t
;
407 struct ppc4xx_ebc_t
{
418 EBC0_CFGADDR
= 0x012,
419 EBC0_CFGDATA
= 0x013,
422 static uint32_t dcr_read_ebc (void *opaque
, int dcrn
)
434 case 0x00: /* B0CR */
437 case 0x01: /* B1CR */
440 case 0x02: /* B2CR */
443 case 0x03: /* B3CR */
446 case 0x04: /* B4CR */
449 case 0x05: /* B5CR */
452 case 0x06: /* B6CR */
455 case 0x07: /* B7CR */
458 case 0x10: /* B0AP */
461 case 0x11: /* B1AP */
464 case 0x12: /* B2AP */
467 case 0x13: /* B3AP */
470 case 0x14: /* B4AP */
473 case 0x15: /* B5AP */
476 case 0x16: /* B6AP */
479 case 0x17: /* B7AP */
482 case 0x20: /* BEAR */
485 case 0x21: /* BESR0 */
488 case 0x22: /* BESR1 */
507 static void dcr_write_ebc (void *opaque
, int dcrn
, uint32_t val
)
518 case 0x00: /* B0CR */
520 case 0x01: /* B1CR */
522 case 0x02: /* B2CR */
524 case 0x03: /* B3CR */
526 case 0x04: /* B4CR */
528 case 0x05: /* B5CR */
530 case 0x06: /* B6CR */
532 case 0x07: /* B7CR */
534 case 0x10: /* B0AP */
536 case 0x11: /* B1AP */
538 case 0x12: /* B2AP */
540 case 0x13: /* B3AP */
542 case 0x14: /* B4AP */
544 case 0x15: /* B5AP */
546 case 0x16: /* B6AP */
548 case 0x17: /* B7AP */
550 case 0x20: /* BEAR */
552 case 0x21: /* BESR0 */
554 case 0x22: /* BESR1 */
567 static void ebc_reset (void *opaque
)
573 ebc
->addr
= 0x00000000;
574 ebc
->bap
[0] = 0x7F8FFE80;
575 ebc
->bcr
[0] = 0xFFE28000;
576 for (i
= 0; i
< 8; i
++) {
577 ebc
->bap
[i
] = 0x00000000;
578 ebc
->bcr
[i
] = 0x00000000;
580 ebc
->besr0
= 0x00000000;
581 ebc
->besr1
= 0x00000000;
582 ebc
->cfg
= 0x80400000;
585 static void ppc405_ebc_init(CPUPPCState
*env
)
589 ebc
= g_malloc0(sizeof(ppc4xx_ebc_t
));
590 qemu_register_reset(&ebc_reset
, ebc
);
591 ppc_dcr_register(env
, EBC0_CFGADDR
,
592 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
593 ppc_dcr_register(env
, EBC0_CFGDATA
,
594 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
597 /*****************************************************************************/
626 typedef struct ppc405_dma_t ppc405_dma_t
;
627 struct ppc405_dma_t
{
640 static uint32_t dcr_read_dma (void *opaque
, int dcrn
)
645 static void dcr_write_dma (void *opaque
, int dcrn
, uint32_t val
)
649 static void ppc405_dma_reset (void *opaque
)
655 for (i
= 0; i
< 4; i
++) {
656 dma
->cr
[i
] = 0x00000000;
657 dma
->ct
[i
] = 0x00000000;
658 dma
->da
[i
] = 0x00000000;
659 dma
->sa
[i
] = 0x00000000;
660 dma
->sg
[i
] = 0x00000000;
662 dma
->sr
= 0x00000000;
663 dma
->sgc
= 0x00000000;
664 dma
->slp
= 0x7C000000;
665 dma
->pol
= 0x00000000;
668 static void ppc405_dma_init(CPUPPCState
*env
, qemu_irq irqs
[4])
672 dma
= g_malloc0(sizeof(ppc405_dma_t
));
673 memcpy(dma
->irqs
, irqs
, 4 * sizeof(qemu_irq
));
674 qemu_register_reset(&ppc405_dma_reset
, dma
);
675 ppc_dcr_register(env
, DMA0_CR0
,
676 dma
, &dcr_read_dma
, &dcr_write_dma
);
677 ppc_dcr_register(env
, DMA0_CT0
,
678 dma
, &dcr_read_dma
, &dcr_write_dma
);
679 ppc_dcr_register(env
, DMA0_DA0
,
680 dma
, &dcr_read_dma
, &dcr_write_dma
);
681 ppc_dcr_register(env
, DMA0_SA0
,
682 dma
, &dcr_read_dma
, &dcr_write_dma
);
683 ppc_dcr_register(env
, DMA0_SG0
,
684 dma
, &dcr_read_dma
, &dcr_write_dma
);
685 ppc_dcr_register(env
, DMA0_CR1
,
686 dma
, &dcr_read_dma
, &dcr_write_dma
);
687 ppc_dcr_register(env
, DMA0_CT1
,
688 dma
, &dcr_read_dma
, &dcr_write_dma
);
689 ppc_dcr_register(env
, DMA0_DA1
,
690 dma
, &dcr_read_dma
, &dcr_write_dma
);
691 ppc_dcr_register(env
, DMA0_SA1
,
692 dma
, &dcr_read_dma
, &dcr_write_dma
);
693 ppc_dcr_register(env
, DMA0_SG1
,
694 dma
, &dcr_read_dma
, &dcr_write_dma
);
695 ppc_dcr_register(env
, DMA0_CR2
,
696 dma
, &dcr_read_dma
, &dcr_write_dma
);
697 ppc_dcr_register(env
, DMA0_CT2
,
698 dma
, &dcr_read_dma
, &dcr_write_dma
);
699 ppc_dcr_register(env
, DMA0_DA2
,
700 dma
, &dcr_read_dma
, &dcr_write_dma
);
701 ppc_dcr_register(env
, DMA0_SA2
,
702 dma
, &dcr_read_dma
, &dcr_write_dma
);
703 ppc_dcr_register(env
, DMA0_SG2
,
704 dma
, &dcr_read_dma
, &dcr_write_dma
);
705 ppc_dcr_register(env
, DMA0_CR3
,
706 dma
, &dcr_read_dma
, &dcr_write_dma
);
707 ppc_dcr_register(env
, DMA0_CT3
,
708 dma
, &dcr_read_dma
, &dcr_write_dma
);
709 ppc_dcr_register(env
, DMA0_DA3
,
710 dma
, &dcr_read_dma
, &dcr_write_dma
);
711 ppc_dcr_register(env
, DMA0_SA3
,
712 dma
, &dcr_read_dma
, &dcr_write_dma
);
713 ppc_dcr_register(env
, DMA0_SG3
,
714 dma
, &dcr_read_dma
, &dcr_write_dma
);
715 ppc_dcr_register(env
, DMA0_SR
,
716 dma
, &dcr_read_dma
, &dcr_write_dma
);
717 ppc_dcr_register(env
, DMA0_SGC
,
718 dma
, &dcr_read_dma
, &dcr_write_dma
);
719 ppc_dcr_register(env
, DMA0_SLP
,
720 dma
, &dcr_read_dma
, &dcr_write_dma
);
721 ppc_dcr_register(env
, DMA0_POL
,
722 dma
, &dcr_read_dma
, &dcr_write_dma
);
725 /*****************************************************************************/
727 typedef struct ppc405_gpio_t ppc405_gpio_t
;
728 struct ppc405_gpio_t
{
743 static uint32_t ppc405_gpio_readb (void *opaque
, hwaddr addr
)
746 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
752 static void ppc405_gpio_writeb (void *opaque
,
753 hwaddr addr
, uint32_t value
)
756 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
761 static uint32_t ppc405_gpio_readw (void *opaque
, hwaddr addr
)
764 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
770 static void ppc405_gpio_writew (void *opaque
,
771 hwaddr addr
, uint32_t value
)
774 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
779 static uint32_t ppc405_gpio_readl (void *opaque
, hwaddr addr
)
782 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
788 static void ppc405_gpio_writel (void *opaque
,
789 hwaddr addr
, uint32_t value
)
792 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
797 static const MemoryRegionOps ppc405_gpio_ops
= {
799 .read
= { ppc405_gpio_readb
, ppc405_gpio_readw
, ppc405_gpio_readl
, },
800 .write
= { ppc405_gpio_writeb
, ppc405_gpio_writew
, ppc405_gpio_writel
, },
802 .endianness
= DEVICE_NATIVE_ENDIAN
,
805 static void ppc405_gpio_reset (void *opaque
)
809 static void ppc405_gpio_init(hwaddr base
)
813 gpio
= g_malloc0(sizeof(ppc405_gpio_t
));
815 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
817 memory_region_init_io(&gpio
->io
, NULL
, &ppc405_gpio_ops
, gpio
, "pgio", 0x038);
818 memory_region_add_subregion(get_system_memory(), base
, &gpio
->io
);
819 qemu_register_reset(&ppc405_gpio_reset
, gpio
);
822 /*****************************************************************************/
826 OCM0_ISACNTL
= 0x019,
828 OCM0_DSACNTL
= 0x01B,
831 typedef struct ppc405_ocm_t ppc405_ocm_t
;
832 struct ppc405_ocm_t
{
834 MemoryRegion isarc_ram
;
835 MemoryRegion dsarc_ram
;
842 static void ocm_update_mappings (ppc405_ocm_t
*ocm
,
843 uint32_t isarc
, uint32_t isacntl
,
844 uint32_t dsarc
, uint32_t dsacntl
)
847 printf("OCM update ISA %08" PRIx32
" %08" PRIx32
" (%08" PRIx32
848 " %08" PRIx32
") DSA %08" PRIx32
" %08" PRIx32
849 " (%08" PRIx32
" %08" PRIx32
")\n",
850 isarc
, isacntl
, dsarc
, dsacntl
,
851 ocm
->isarc
, ocm
->isacntl
, ocm
->dsarc
, ocm
->dsacntl
);
853 if (ocm
->isarc
!= isarc
||
854 (ocm
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
855 if (ocm
->isacntl
& 0x80000000) {
856 /* Unmap previously assigned memory region */
857 printf("OCM unmap ISA %08" PRIx32
"\n", ocm
->isarc
);
858 memory_region_del_subregion(get_system_memory(), &ocm
->isarc_ram
);
860 if (isacntl
& 0x80000000) {
861 /* Map new instruction memory region */
863 printf("OCM map ISA %08" PRIx32
"\n", isarc
);
865 memory_region_add_subregion(get_system_memory(), isarc
,
869 if (ocm
->dsarc
!= dsarc
||
870 (ocm
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
871 if (ocm
->dsacntl
& 0x80000000) {
872 /* Beware not to unmap the region we just mapped */
873 if (!(isacntl
& 0x80000000) || ocm
->dsarc
!= isarc
) {
874 /* Unmap previously assigned memory region */
876 printf("OCM unmap DSA %08" PRIx32
"\n", ocm
->dsarc
);
878 memory_region_del_subregion(get_system_memory(),
882 if (dsacntl
& 0x80000000) {
883 /* Beware not to remap the region we just mapped */
884 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
885 /* Map new data memory region */
887 printf("OCM map DSA %08" PRIx32
"\n", dsarc
);
889 memory_region_add_subregion(get_system_memory(), dsarc
,
896 static uint32_t dcr_read_ocm (void *opaque
, int dcrn
)
923 static void dcr_write_ocm (void *opaque
, int dcrn
, uint32_t val
)
926 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
931 isacntl
= ocm
->isacntl
;
932 dsacntl
= ocm
->dsacntl
;
935 isarc
= val
& 0xFC000000;
938 isacntl
= val
& 0xC0000000;
941 isarc
= val
& 0xFC000000;
944 isacntl
= val
& 0xC0000000;
947 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
950 ocm
->isacntl
= isacntl
;
951 ocm
->dsacntl
= dsacntl
;
954 static void ocm_reset (void *opaque
)
957 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
961 isacntl
= 0x00000000;
963 dsacntl
= 0x00000000;
964 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
967 ocm
->isacntl
= isacntl
;
968 ocm
->dsacntl
= dsacntl
;
971 static void ppc405_ocm_init(CPUPPCState
*env
)
975 ocm
= g_malloc0(sizeof(ppc405_ocm_t
));
976 /* XXX: Size is 4096 or 0x04000000 */
977 memory_region_init_ram(&ocm
->isarc_ram
, NULL
, "ppc405.ocm", 4096);
978 vmstate_register_ram_global(&ocm
->isarc_ram
);
979 memory_region_init_alias(&ocm
->dsarc_ram
, NULL
, "ppc405.dsarc", &ocm
->isarc_ram
,
981 qemu_register_reset(&ocm_reset
, ocm
);
982 ppc_dcr_register(env
, OCM0_ISARC
,
983 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
984 ppc_dcr_register(env
, OCM0_ISACNTL
,
985 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
986 ppc_dcr_register(env
, OCM0_DSARC
,
987 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
988 ppc_dcr_register(env
, OCM0_DSACNTL
,
989 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
992 /*****************************************************************************/
994 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t
;
995 struct ppc4xx_i2c_t
{
1015 static uint32_t ppc4xx_i2c_readb (void *opaque
, hwaddr addr
)
1021 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1026 // i2c_readbyte(&i2c->mdata);
1066 ret
= i2c
->xtcntlss
;
1069 ret
= i2c
->directcntl
;
1076 printf("%s: addr " TARGET_FMT_plx
" %02" PRIx32
"\n", __func__
, addr
, ret
);
1082 static void ppc4xx_i2c_writeb (void *opaque
,
1083 hwaddr addr
, uint32_t value
)
1088 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1095 // i2c_sendbyte(&i2c->mdata);
1110 i2c
->mdcntl
= value
& 0xDF;
1113 i2c
->sts
&= ~(value
& 0x0A);
1116 i2c
->extsts
&= ~(value
& 0x8F);
1125 i2c
->clkdiv
= value
;
1128 i2c
->intrmsk
= value
;
1131 i2c
->xfrcnt
= value
& 0x77;
1134 i2c
->xtcntlss
= value
;
1137 i2c
->directcntl
= value
& 0x7;
1142 static uint32_t ppc4xx_i2c_readw (void *opaque
, hwaddr addr
)
1147 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1149 ret
= ppc4xx_i2c_readb(opaque
, addr
) << 8;
1150 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 1);
1155 static void ppc4xx_i2c_writew (void *opaque
,
1156 hwaddr addr
, uint32_t value
)
1159 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1162 ppc4xx_i2c_writeb(opaque
, addr
, value
>> 8);
1163 ppc4xx_i2c_writeb(opaque
, addr
+ 1, value
);
1166 static uint32_t ppc4xx_i2c_readl (void *opaque
, hwaddr addr
)
1171 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1173 ret
= ppc4xx_i2c_readb(opaque
, addr
) << 24;
1174 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 1) << 16;
1175 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 2) << 8;
1176 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 3);
1181 static void ppc4xx_i2c_writel (void *opaque
,
1182 hwaddr addr
, uint32_t value
)
1185 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1188 ppc4xx_i2c_writeb(opaque
, addr
, value
>> 24);
1189 ppc4xx_i2c_writeb(opaque
, addr
+ 1, value
>> 16);
1190 ppc4xx_i2c_writeb(opaque
, addr
+ 2, value
>> 8);
1191 ppc4xx_i2c_writeb(opaque
, addr
+ 3, value
);
1194 static const MemoryRegionOps i2c_ops
= {
1196 .read
= { ppc4xx_i2c_readb
, ppc4xx_i2c_readw
, ppc4xx_i2c_readl
, },
1197 .write
= { ppc4xx_i2c_writeb
, ppc4xx_i2c_writew
, ppc4xx_i2c_writel
, },
1199 .endianness
= DEVICE_NATIVE_ENDIAN
,
1202 static void ppc4xx_i2c_reset (void *opaque
)
1215 i2c
->directcntl
= 0x0F;
1218 static void ppc405_i2c_init(hwaddr base
, qemu_irq irq
)
1222 i2c
= g_malloc0(sizeof(ppc4xx_i2c_t
));
1225 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
1227 memory_region_init_io(&i2c
->iomem
, NULL
, &i2c_ops
, i2c
, "i2c", 0x011);
1228 memory_region_add_subregion(get_system_memory(), base
, &i2c
->iomem
);
1229 qemu_register_reset(ppc4xx_i2c_reset
, i2c
);
1232 /*****************************************************************************/
1233 /* General purpose timers */
1234 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t
;
1235 struct ppc4xx_gpt_t
{
1250 static uint32_t ppc4xx_gpt_readb (void *opaque
, hwaddr addr
)
1253 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1255 /* XXX: generate a bus fault */
1259 static void ppc4xx_gpt_writeb (void *opaque
,
1260 hwaddr addr
, uint32_t value
)
1263 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1266 /* XXX: generate a bus fault */
1269 static uint32_t ppc4xx_gpt_readw (void *opaque
, hwaddr addr
)
1272 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1274 /* XXX: generate a bus fault */
1278 static void ppc4xx_gpt_writew (void *opaque
,
1279 hwaddr addr
, uint32_t value
)
1282 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1285 /* XXX: generate a bus fault */
1288 static int ppc4xx_gpt_compare (ppc4xx_gpt_t
*gpt
, int n
)
1294 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t
*gpt
, int n
, int level
)
1299 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t
*gpt
)
1305 for (i
= 0; i
< 5; i
++) {
1306 if (gpt
->oe
& mask
) {
1307 /* Output is enabled */
1308 if (ppc4xx_gpt_compare(gpt
, i
)) {
1309 /* Comparison is OK */
1310 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
);
1312 /* Comparison is KO */
1313 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
? 0 : 1);
1320 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t
*gpt
)
1326 for (i
= 0; i
< 5; i
++) {
1327 if (gpt
->is
& gpt
->im
& mask
)
1328 qemu_irq_raise(gpt
->irqs
[i
]);
1330 qemu_irq_lower(gpt
->irqs
[i
]);
1335 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t
*gpt
)
1340 static uint32_t ppc4xx_gpt_readl (void *opaque
, hwaddr addr
)
1347 printf("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1352 /* Time base counter */
1353 ret
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + gpt
->tb_offset
,
1354 gpt
->tb_freq
, get_ticks_per_sec());
1365 /* Interrupt mask */
1370 /* Interrupt status */
1374 /* Interrupt enable */
1379 idx
= (addr
- 0x80) >> 2;
1380 ret
= gpt
->comp
[idx
];
1384 idx
= (addr
- 0xC0) >> 2;
1385 ret
= gpt
->mask
[idx
];
1395 static void ppc4xx_gpt_writel (void *opaque
,
1396 hwaddr addr
, uint32_t value
)
1402 printf("%s: addr " TARGET_FMT_plx
" val %08" PRIx32
"\n", __func__
, addr
,
1408 /* Time base counter */
1409 gpt
->tb_offset
= muldiv64(value
, get_ticks_per_sec(), gpt
->tb_freq
)
1410 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1411 ppc4xx_gpt_compute_timer(gpt
);
1415 gpt
->oe
= value
& 0xF8000000;
1416 ppc4xx_gpt_set_outputs(gpt
);
1420 gpt
->ol
= value
& 0xF8000000;
1421 ppc4xx_gpt_set_outputs(gpt
);
1424 /* Interrupt mask */
1425 gpt
->im
= value
& 0x0000F800;
1428 /* Interrupt status set */
1429 gpt
->is
|= value
& 0x0000F800;
1430 ppc4xx_gpt_set_irqs(gpt
);
1433 /* Interrupt status clear */
1434 gpt
->is
&= ~(value
& 0x0000F800);
1435 ppc4xx_gpt_set_irqs(gpt
);
1438 /* Interrupt enable */
1439 gpt
->ie
= value
& 0x0000F800;
1440 ppc4xx_gpt_set_irqs(gpt
);
1444 idx
= (addr
- 0x80) >> 2;
1445 gpt
->comp
[idx
] = value
& 0xF8000000;
1446 ppc4xx_gpt_compute_timer(gpt
);
1450 idx
= (addr
- 0xC0) >> 2;
1451 gpt
->mask
[idx
] = value
& 0xF8000000;
1452 ppc4xx_gpt_compute_timer(gpt
);
1457 static const MemoryRegionOps gpt_ops
= {
1459 .read
= { ppc4xx_gpt_readb
, ppc4xx_gpt_readw
, ppc4xx_gpt_readl
, },
1460 .write
= { ppc4xx_gpt_writeb
, ppc4xx_gpt_writew
, ppc4xx_gpt_writel
, },
1462 .endianness
= DEVICE_NATIVE_ENDIAN
,
1465 static void ppc4xx_gpt_cb (void *opaque
)
1470 ppc4xx_gpt_set_irqs(gpt
);
1471 ppc4xx_gpt_set_outputs(gpt
);
1472 ppc4xx_gpt_compute_timer(gpt
);
1475 static void ppc4xx_gpt_reset (void *opaque
)
1481 timer_del(gpt
->timer
);
1482 gpt
->oe
= 0x00000000;
1483 gpt
->ol
= 0x00000000;
1484 gpt
->im
= 0x00000000;
1485 gpt
->is
= 0x00000000;
1486 gpt
->ie
= 0x00000000;
1487 for (i
= 0; i
< 5; i
++) {
1488 gpt
->comp
[i
] = 0x00000000;
1489 gpt
->mask
[i
] = 0x00000000;
1493 static void ppc4xx_gpt_init(hwaddr base
, qemu_irq irqs
[5])
1498 gpt
= g_malloc0(sizeof(ppc4xx_gpt_t
));
1499 for (i
= 0; i
< 5; i
++) {
1500 gpt
->irqs
[i
] = irqs
[i
];
1502 gpt
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &ppc4xx_gpt_cb
, gpt
);
1504 printf("%s: offset " TARGET_FMT_plx
"\n", __func__
, base
);
1506 memory_region_init_io(&gpt
->iomem
, NULL
, &gpt_ops
, gpt
, "gpt", 0x0d4);
1507 memory_region_add_subregion(get_system_memory(), base
, &gpt
->iomem
);
1508 qemu_register_reset(ppc4xx_gpt_reset
, gpt
);
1511 /*****************************************************************************/
1517 MAL0_TXCASR
= 0x184,
1518 MAL0_TXCARR
= 0x185,
1519 MAL0_TXEOBISR
= 0x186,
1520 MAL0_TXDEIR
= 0x187,
1521 MAL0_RXCASR
= 0x190,
1522 MAL0_RXCARR
= 0x191,
1523 MAL0_RXEOBISR
= 0x192,
1524 MAL0_RXDEIR
= 0x193,
1525 MAL0_TXCTP0R
= 0x1A0,
1526 MAL0_TXCTP1R
= 0x1A1,
1527 MAL0_TXCTP2R
= 0x1A2,
1528 MAL0_TXCTP3R
= 0x1A3,
1529 MAL0_RXCTP0R
= 0x1C0,
1530 MAL0_RXCTP1R
= 0x1C1,
1535 typedef struct ppc40x_mal_t ppc40x_mal_t
;
1536 struct ppc40x_mal_t
{
1554 static void ppc40x_mal_reset (void *opaque
);
1556 static uint32_t dcr_read_mal (void *opaque
, int dcrn
)
1579 ret
= mal
->txeobisr
;
1591 ret
= mal
->rxeobisr
;
1597 ret
= mal
->txctpr
[0];
1600 ret
= mal
->txctpr
[1];
1603 ret
= mal
->txctpr
[2];
1606 ret
= mal
->txctpr
[3];
1609 ret
= mal
->rxctpr
[0];
1612 ret
= mal
->rxctpr
[1];
1628 static void dcr_write_mal (void *opaque
, int dcrn
, uint32_t val
)
1636 if (val
& 0x80000000)
1637 ppc40x_mal_reset(mal
);
1638 mal
->cfg
= val
& 0x00FFC087;
1645 mal
->ier
= val
& 0x0000001F;
1648 mal
->txcasr
= val
& 0xF0000000;
1651 mal
->txcarr
= val
& 0xF0000000;
1655 mal
->txeobisr
&= ~val
;
1659 mal
->txdeir
&= ~val
;
1662 mal
->rxcasr
= val
& 0xC0000000;
1665 mal
->rxcarr
= val
& 0xC0000000;
1669 mal
->rxeobisr
&= ~val
;
1673 mal
->rxdeir
&= ~val
;
1687 mal
->txctpr
[idx
] = val
;
1695 mal
->rxctpr
[idx
] = val
;
1699 goto update_rx_size
;
1703 mal
->rcbs
[idx
] = val
& 0x000000FF;
1708 static void ppc40x_mal_reset (void *opaque
)
1713 mal
->cfg
= 0x0007C000;
1714 mal
->esr
= 0x00000000;
1715 mal
->ier
= 0x00000000;
1716 mal
->rxcasr
= 0x00000000;
1717 mal
->rxdeir
= 0x00000000;
1718 mal
->rxeobisr
= 0x00000000;
1719 mal
->txcasr
= 0x00000000;
1720 mal
->txdeir
= 0x00000000;
1721 mal
->txeobisr
= 0x00000000;
1724 static void ppc405_mal_init(CPUPPCState
*env
, qemu_irq irqs
[4])
1729 mal
= g_malloc0(sizeof(ppc40x_mal_t
));
1730 for (i
= 0; i
< 4; i
++)
1731 mal
->irqs
[i
] = irqs
[i
];
1732 qemu_register_reset(&ppc40x_mal_reset
, mal
);
1733 ppc_dcr_register(env
, MAL0_CFG
,
1734 mal
, &dcr_read_mal
, &dcr_write_mal
);
1735 ppc_dcr_register(env
, MAL0_ESR
,
1736 mal
, &dcr_read_mal
, &dcr_write_mal
);
1737 ppc_dcr_register(env
, MAL0_IER
,
1738 mal
, &dcr_read_mal
, &dcr_write_mal
);
1739 ppc_dcr_register(env
, MAL0_TXCASR
,
1740 mal
, &dcr_read_mal
, &dcr_write_mal
);
1741 ppc_dcr_register(env
, MAL0_TXCARR
,
1742 mal
, &dcr_read_mal
, &dcr_write_mal
);
1743 ppc_dcr_register(env
, MAL0_TXEOBISR
,
1744 mal
, &dcr_read_mal
, &dcr_write_mal
);
1745 ppc_dcr_register(env
, MAL0_TXDEIR
,
1746 mal
, &dcr_read_mal
, &dcr_write_mal
);
1747 ppc_dcr_register(env
, MAL0_RXCASR
,
1748 mal
, &dcr_read_mal
, &dcr_write_mal
);
1749 ppc_dcr_register(env
, MAL0_RXCARR
,
1750 mal
, &dcr_read_mal
, &dcr_write_mal
);
1751 ppc_dcr_register(env
, MAL0_RXEOBISR
,
1752 mal
, &dcr_read_mal
, &dcr_write_mal
);
1753 ppc_dcr_register(env
, MAL0_RXDEIR
,
1754 mal
, &dcr_read_mal
, &dcr_write_mal
);
1755 ppc_dcr_register(env
, MAL0_TXCTP0R
,
1756 mal
, &dcr_read_mal
, &dcr_write_mal
);
1757 ppc_dcr_register(env
, MAL0_TXCTP1R
,
1758 mal
, &dcr_read_mal
, &dcr_write_mal
);
1759 ppc_dcr_register(env
, MAL0_TXCTP2R
,
1760 mal
, &dcr_read_mal
, &dcr_write_mal
);
1761 ppc_dcr_register(env
, MAL0_TXCTP3R
,
1762 mal
, &dcr_read_mal
, &dcr_write_mal
);
1763 ppc_dcr_register(env
, MAL0_RXCTP0R
,
1764 mal
, &dcr_read_mal
, &dcr_write_mal
);
1765 ppc_dcr_register(env
, MAL0_RXCTP1R
,
1766 mal
, &dcr_read_mal
, &dcr_write_mal
);
1767 ppc_dcr_register(env
, MAL0_RCBS0
,
1768 mal
, &dcr_read_mal
, &dcr_write_mal
);
1769 ppc_dcr_register(env
, MAL0_RCBS1
,
1770 mal
, &dcr_read_mal
, &dcr_write_mal
);
1773 /*****************************************************************************/
1775 void ppc40x_core_reset(PowerPCCPU
*cpu
)
1777 CPUPPCState
*env
= &cpu
->env
;
1780 printf("Reset PowerPC core\n");
1781 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_RESET
);
1782 dbsr
= env
->spr
[SPR_40x_DBSR
];
1783 dbsr
&= ~0x00000300;
1785 env
->spr
[SPR_40x_DBSR
] = dbsr
;
1788 void ppc40x_chip_reset(PowerPCCPU
*cpu
)
1790 CPUPPCState
*env
= &cpu
->env
;
1793 printf("Reset PowerPC chip\n");
1794 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_RESET
);
1795 /* XXX: TODO reset all internal peripherals */
1796 dbsr
= env
->spr
[SPR_40x_DBSR
];
1797 dbsr
&= ~0x00000300;
1799 env
->spr
[SPR_40x_DBSR
] = dbsr
;
1802 void ppc40x_system_reset(PowerPCCPU
*cpu
)
1804 printf("Reset PowerPC system\n");
1805 qemu_system_reset_request();
1808 void store_40x_dbcr0 (CPUPPCState
*env
, uint32_t val
)
1810 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
1812 switch ((val
>> 28) & 0x3) {
1818 ppc40x_core_reset(cpu
);
1822 ppc40x_chip_reset(cpu
);
1826 ppc40x_system_reset(cpu
);
1831 /*****************************************************************************/
1834 PPC405CR_CPC0_PLLMR
= 0x0B0,
1835 PPC405CR_CPC0_CR0
= 0x0B1,
1836 PPC405CR_CPC0_CR1
= 0x0B2,
1837 PPC405CR_CPC0_PSR
= 0x0B4,
1838 PPC405CR_CPC0_JTAGID
= 0x0B5,
1839 PPC405CR_CPC0_ER
= 0x0B9,
1840 PPC405CR_CPC0_FR
= 0x0BA,
1841 PPC405CR_CPC0_SR
= 0x0BB,
1845 PPC405CR_CPU_CLK
= 0,
1846 PPC405CR_TMR_CLK
= 1,
1847 PPC405CR_PLB_CLK
= 2,
1848 PPC405CR_SDRAM_CLK
= 3,
1849 PPC405CR_OPB_CLK
= 4,
1850 PPC405CR_EXT_CLK
= 5,
1851 PPC405CR_UART_CLK
= 6,
1852 PPC405CR_CLK_NB
= 7,
1855 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t
;
1856 struct ppc405cr_cpc_t
{
1857 clk_setup_t clk_setup
[PPC405CR_CLK_NB
];
1868 static void ppc405cr_clk_setup (ppc405cr_cpc_t
*cpc
)
1870 uint64_t VCO_out
, PLL_out
;
1871 uint32_t CPU_clk
, TMR_clk
, SDRAM_clk
, PLB_clk
, OPB_clk
, EXT_clk
, UART_clk
;
1874 D0
= ((cpc
->pllmr
>> 26) & 0x3) + 1; /* CBDV */
1875 if (cpc
->pllmr
& 0x80000000) {
1876 D1
= (((cpc
->pllmr
>> 20) - 1) & 0xF) + 1; /* FBDV */
1877 D2
= 8 - ((cpc
->pllmr
>> 16) & 0x7); /* FWDVA */
1879 VCO_out
= cpc
->sysclk
* M
;
1880 if (VCO_out
< 400000000 || VCO_out
> 800000000) {
1881 /* PLL cannot lock */
1882 cpc
->pllmr
&= ~0x80000000;
1885 PLL_out
= VCO_out
/ D2
;
1890 PLL_out
= cpc
->sysclk
* M
;
1893 if (cpc
->cr1
& 0x00800000)
1894 TMR_clk
= cpc
->sysclk
; /* Should have a separate clock */
1897 PLB_clk
= CPU_clk
/ D0
;
1898 SDRAM_clk
= PLB_clk
;
1899 D0
= ((cpc
->pllmr
>> 10) & 0x3) + 1;
1900 OPB_clk
= PLB_clk
/ D0
;
1901 D0
= ((cpc
->pllmr
>> 24) & 0x3) + 2;
1902 EXT_clk
= PLB_clk
/ D0
;
1903 D0
= ((cpc
->cr0
>> 1) & 0x1F) + 1;
1904 UART_clk
= CPU_clk
/ D0
;
1905 /* Setup CPU clocks */
1906 clk_setup(&cpc
->clk_setup
[PPC405CR_CPU_CLK
], CPU_clk
);
1907 /* Setup time-base clock */
1908 clk_setup(&cpc
->clk_setup
[PPC405CR_TMR_CLK
], TMR_clk
);
1909 /* Setup PLB clock */
1910 clk_setup(&cpc
->clk_setup
[PPC405CR_PLB_CLK
], PLB_clk
);
1911 /* Setup SDRAM clock */
1912 clk_setup(&cpc
->clk_setup
[PPC405CR_SDRAM_CLK
], SDRAM_clk
);
1913 /* Setup OPB clock */
1914 clk_setup(&cpc
->clk_setup
[PPC405CR_OPB_CLK
], OPB_clk
);
1915 /* Setup external clock */
1916 clk_setup(&cpc
->clk_setup
[PPC405CR_EXT_CLK
], EXT_clk
);
1917 /* Setup UART clock */
1918 clk_setup(&cpc
->clk_setup
[PPC405CR_UART_CLK
], UART_clk
);
1921 static uint32_t dcr_read_crcpc (void *opaque
, int dcrn
)
1923 ppc405cr_cpc_t
*cpc
;
1928 case PPC405CR_CPC0_PLLMR
:
1931 case PPC405CR_CPC0_CR0
:
1934 case PPC405CR_CPC0_CR1
:
1937 case PPC405CR_CPC0_PSR
:
1940 case PPC405CR_CPC0_JTAGID
:
1943 case PPC405CR_CPC0_ER
:
1946 case PPC405CR_CPC0_FR
:
1949 case PPC405CR_CPC0_SR
:
1950 ret
= ~(cpc
->er
| cpc
->fr
) & 0xFFFF0000;
1953 /* Avoid gcc warning */
1961 static void dcr_write_crcpc (void *opaque
, int dcrn
, uint32_t val
)
1963 ppc405cr_cpc_t
*cpc
;
1967 case PPC405CR_CPC0_PLLMR
:
1968 cpc
->pllmr
= val
& 0xFFF77C3F;
1970 case PPC405CR_CPC0_CR0
:
1971 cpc
->cr0
= val
& 0x0FFFFFFE;
1973 case PPC405CR_CPC0_CR1
:
1974 cpc
->cr1
= val
& 0x00800000;
1976 case PPC405CR_CPC0_PSR
:
1979 case PPC405CR_CPC0_JTAGID
:
1982 case PPC405CR_CPC0_ER
:
1983 cpc
->er
= val
& 0xBFFC0000;
1985 case PPC405CR_CPC0_FR
:
1986 cpc
->fr
= val
& 0xBFFC0000;
1988 case PPC405CR_CPC0_SR
:
1994 static void ppc405cr_cpc_reset (void *opaque
)
1996 ppc405cr_cpc_t
*cpc
;
2000 /* Compute PLLMR value from PSR settings */
2001 cpc
->pllmr
= 0x80000000;
2003 switch ((cpc
->psr
>> 30) & 3) {
2006 cpc
->pllmr
&= ~0x80000000;
2010 cpc
->pllmr
|= 5 << 16;
2014 cpc
->pllmr
|= 4 << 16;
2018 cpc
->pllmr
|= 2 << 16;
2022 D
= (cpc
->psr
>> 28) & 3;
2023 cpc
->pllmr
|= (D
+ 1) << 20;
2025 D
= (cpc
->psr
>> 25) & 7;
2040 D
= (cpc
->psr
>> 23) & 3;
2041 cpc
->pllmr
|= D
<< 26;
2043 D
= (cpc
->psr
>> 21) & 3;
2044 cpc
->pllmr
|= D
<< 10;
2046 D
= (cpc
->psr
>> 17) & 3;
2047 cpc
->pllmr
|= D
<< 24;
2048 cpc
->cr0
= 0x0000003C;
2049 cpc
->cr1
= 0x2B0D8800;
2050 cpc
->er
= 0x00000000;
2051 cpc
->fr
= 0x00000000;
2052 ppc405cr_clk_setup(cpc
);
2055 static void ppc405cr_clk_init (ppc405cr_cpc_t
*cpc
)
2059 /* XXX: this should be read from IO pins */
2060 cpc
->psr
= 0x00000000; /* 8 bits ROM */
2062 D
= 0x2; /* Divide by 4 */
2063 cpc
->psr
|= D
<< 30;
2065 D
= 0x1; /* Divide by 2 */
2066 cpc
->psr
|= D
<< 28;
2068 D
= 0x1; /* Divide by 2 */
2069 cpc
->psr
|= D
<< 23;
2071 D
= 0x5; /* M = 16 */
2072 cpc
->psr
|= D
<< 25;
2074 D
= 0x1; /* Divide by 2 */
2075 cpc
->psr
|= D
<< 21;
2077 D
= 0x2; /* Divide by 4 */
2078 cpc
->psr
|= D
<< 17;
2081 static void ppc405cr_cpc_init (CPUPPCState
*env
, clk_setup_t clk_setup
[7],
2084 ppc405cr_cpc_t
*cpc
;
2086 cpc
= g_malloc0(sizeof(ppc405cr_cpc_t
));
2087 memcpy(cpc
->clk_setup
, clk_setup
,
2088 PPC405CR_CLK_NB
* sizeof(clk_setup_t
));
2089 cpc
->sysclk
= sysclk
;
2090 cpc
->jtagid
= 0x42051049;
2091 ppc_dcr_register(env
, PPC405CR_CPC0_PSR
, cpc
,
2092 &dcr_read_crcpc
, &dcr_write_crcpc
);
2093 ppc_dcr_register(env
, PPC405CR_CPC0_CR0
, cpc
,
2094 &dcr_read_crcpc
, &dcr_write_crcpc
);
2095 ppc_dcr_register(env
, PPC405CR_CPC0_CR1
, cpc
,
2096 &dcr_read_crcpc
, &dcr_write_crcpc
);
2097 ppc_dcr_register(env
, PPC405CR_CPC0_JTAGID
, cpc
,
2098 &dcr_read_crcpc
, &dcr_write_crcpc
);
2099 ppc_dcr_register(env
, PPC405CR_CPC0_PLLMR
, cpc
,
2100 &dcr_read_crcpc
, &dcr_write_crcpc
);
2101 ppc_dcr_register(env
, PPC405CR_CPC0_ER
, cpc
,
2102 &dcr_read_crcpc
, &dcr_write_crcpc
);
2103 ppc_dcr_register(env
, PPC405CR_CPC0_FR
, cpc
,
2104 &dcr_read_crcpc
, &dcr_write_crcpc
);
2105 ppc_dcr_register(env
, PPC405CR_CPC0_SR
, cpc
,
2106 &dcr_read_crcpc
, &dcr_write_crcpc
);
2107 ppc405cr_clk_init(cpc
);
2108 qemu_register_reset(ppc405cr_cpc_reset
, cpc
);
2111 CPUPPCState
*ppc405cr_init(MemoryRegion
*address_space_mem
,
2112 MemoryRegion ram_memories
[4],
2113 hwaddr ram_bases
[4],
2114 hwaddr ram_sizes
[4],
2115 uint32_t sysclk
, qemu_irq
**picp
,
2118 clk_setup_t clk_setup
[PPC405CR_CLK_NB
];
2119 qemu_irq dma_irqs
[4];
2122 qemu_irq
*pic
, *irqs
;
2124 memset(clk_setup
, 0, sizeof(clk_setup
));
2125 cpu
= ppc4xx_init("405cr", &clk_setup
[PPC405CR_CPU_CLK
],
2126 &clk_setup
[PPC405CR_TMR_CLK
], sysclk
);
2128 /* Memory mapped devices registers */
2130 ppc4xx_plb_init(env
);
2131 /* PLB to OPB bridge */
2132 ppc4xx_pob_init(env
);
2134 ppc4xx_opba_init(0xef600600);
2135 /* Universal interrupt controller */
2136 irqs
= g_malloc0(sizeof(qemu_irq
) * PPCUIC_OUTPUT_NB
);
2137 irqs
[PPCUIC_OUTPUT_INT
] =
2138 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_INT
];
2139 irqs
[PPCUIC_OUTPUT_CINT
] =
2140 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_CINT
];
2141 pic
= ppcuic_init(env
, irqs
, 0x0C0, 0, 1);
2143 /* SDRAM controller */
2144 ppc4xx_sdram_init(env
, pic
[14], 1, ram_memories
,
2145 ram_bases
, ram_sizes
, do_init
);
2146 /* External bus controller */
2147 ppc405_ebc_init(env
);
2148 /* DMA controller */
2149 dma_irqs
[0] = pic
[26];
2150 dma_irqs
[1] = pic
[25];
2151 dma_irqs
[2] = pic
[24];
2152 dma_irqs
[3] = pic
[23];
2153 ppc405_dma_init(env
, dma_irqs
);
2155 if (serial_hds
[0] != NULL
) {
2156 serial_mm_init(address_space_mem
, 0xef600300, 0, pic
[0],
2157 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[0],
2160 if (serial_hds
[1] != NULL
) {
2161 serial_mm_init(address_space_mem
, 0xef600400, 0, pic
[1],
2162 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[1],
2165 /* IIC controller */
2166 ppc405_i2c_init(0xef600500, pic
[2]);
2168 ppc405_gpio_init(0xef600700);
2170 ppc405cr_cpc_init(env
, clk_setup
, sysclk
);
2175 /*****************************************************************************/
2179 PPC405EP_CPC0_PLLMR0
= 0x0F0,
2180 PPC405EP_CPC0_BOOT
= 0x0F1,
2181 PPC405EP_CPC0_EPCTL
= 0x0F3,
2182 PPC405EP_CPC0_PLLMR1
= 0x0F4,
2183 PPC405EP_CPC0_UCR
= 0x0F5,
2184 PPC405EP_CPC0_SRR
= 0x0F6,
2185 PPC405EP_CPC0_JTAGID
= 0x0F7,
2186 PPC405EP_CPC0_PCI
= 0x0F9,
2188 PPC405EP_CPC0_ER
= xxx
,
2189 PPC405EP_CPC0_FR
= xxx
,
2190 PPC405EP_CPC0_SR
= xxx
,
2195 PPC405EP_CPU_CLK
= 0,
2196 PPC405EP_PLB_CLK
= 1,
2197 PPC405EP_OPB_CLK
= 2,
2198 PPC405EP_EBC_CLK
= 3,
2199 PPC405EP_MAL_CLK
= 4,
2200 PPC405EP_PCI_CLK
= 5,
2201 PPC405EP_UART0_CLK
= 6,
2202 PPC405EP_UART1_CLK
= 7,
2203 PPC405EP_CLK_NB
= 8,
2206 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t
;
2207 struct ppc405ep_cpc_t
{
2209 clk_setup_t clk_setup
[PPC405EP_CLK_NB
];
2217 /* Clock and power management */
2223 static void ppc405ep_compute_clocks (ppc405ep_cpc_t
*cpc
)
2225 uint32_t CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
;
2226 uint32_t UART0_clk
, UART1_clk
;
2227 uint64_t VCO_out
, PLL_out
;
2231 if ((cpc
->pllmr
[1] & 0x80000000) && !(cpc
->pllmr
[1] & 0x40000000)) {
2232 M
= (((cpc
->pllmr
[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2233 #ifdef DEBUG_CLOCKS_LL
2234 printf("FBMUL %01" PRIx32
" %d\n", (cpc
->pllmr
[1] >> 20) & 0xF, M
);
2236 D
= 8 - ((cpc
->pllmr
[1] >> 16) & 0x7); /* FWDA */
2237 #ifdef DEBUG_CLOCKS_LL
2238 printf("FWDA %01" PRIx32
" %d\n", (cpc
->pllmr
[1] >> 16) & 0x7, D
);
2240 VCO_out
= cpc
->sysclk
* M
* D
;
2241 if (VCO_out
< 500000000UL || VCO_out
> 1000000000UL) {
2242 /* Error - unlock the PLL */
2243 printf("VCO out of range %" PRIu64
"\n", VCO_out
);
2245 cpc
->pllmr
[1] &= ~0x80000000;
2249 PLL_out
= VCO_out
/ D
;
2250 /* Pretend the PLL is locked */
2251 cpc
->boot
|= 0x00000001;
2256 PLL_out
= cpc
->sysclk
;
2257 if (cpc
->pllmr
[1] & 0x40000000) {
2258 /* Pretend the PLL is not locked */
2259 cpc
->boot
&= ~0x00000001;
2262 /* Now, compute all other clocks */
2263 D
= ((cpc
->pllmr
[0] >> 20) & 0x3) + 1; /* CCDV */
2264 #ifdef DEBUG_CLOCKS_LL
2265 printf("CCDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 20) & 0x3, D
);
2267 CPU_clk
= PLL_out
/ D
;
2268 D
= ((cpc
->pllmr
[0] >> 16) & 0x3) + 1; /* CBDV */
2269 #ifdef DEBUG_CLOCKS_LL
2270 printf("CBDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 16) & 0x3, D
);
2272 PLB_clk
= CPU_clk
/ D
;
2273 D
= ((cpc
->pllmr
[0] >> 12) & 0x3) + 1; /* OPDV */
2274 #ifdef DEBUG_CLOCKS_LL
2275 printf("OPDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 12) & 0x3, D
);
2277 OPB_clk
= PLB_clk
/ D
;
2278 D
= ((cpc
->pllmr
[0] >> 8) & 0x3) + 2; /* EPDV */
2279 #ifdef DEBUG_CLOCKS_LL
2280 printf("EPDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 8) & 0x3, D
);
2282 EBC_clk
= PLB_clk
/ D
;
2283 D
= ((cpc
->pllmr
[0] >> 4) & 0x3) + 1; /* MPDV */
2284 #ifdef DEBUG_CLOCKS_LL
2285 printf("MPDV %01" PRIx32
" %d\n", (cpc
->pllmr
[0] >> 4) & 0x3, D
);
2287 MAL_clk
= PLB_clk
/ D
;
2288 D
= (cpc
->pllmr
[0] & 0x3) + 1; /* PPDV */
2289 #ifdef DEBUG_CLOCKS_LL
2290 printf("PPDV %01" PRIx32
" %d\n", cpc
->pllmr
[0] & 0x3, D
);
2292 PCI_clk
= PLB_clk
/ D
;
2293 D
= ((cpc
->ucr
- 1) & 0x7F) + 1; /* U0DIV */
2294 #ifdef DEBUG_CLOCKS_LL
2295 printf("U0DIV %01" PRIx32
" %d\n", cpc
->ucr
& 0x7F, D
);
2297 UART0_clk
= PLL_out
/ D
;
2298 D
= (((cpc
->ucr
>> 8) - 1) & 0x7F) + 1; /* U1DIV */
2299 #ifdef DEBUG_CLOCKS_LL
2300 printf("U1DIV %01" PRIx32
" %d\n", (cpc
->ucr
>> 8) & 0x7F, D
);
2302 UART1_clk
= PLL_out
/ D
;
2304 printf("Setup PPC405EP clocks - sysclk %" PRIu32
" VCO %" PRIu64
2305 " PLL out %" PRIu64
" Hz\n", cpc
->sysclk
, VCO_out
, PLL_out
);
2306 printf("CPU %" PRIu32
" PLB %" PRIu32
" OPB %" PRIu32
" EBC %" PRIu32
2307 " MAL %" PRIu32
" PCI %" PRIu32
" UART0 %" PRIu32
2308 " UART1 %" PRIu32
"\n",
2309 CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
,
2310 UART0_clk
, UART1_clk
);
2312 /* Setup CPU clocks */
2313 clk_setup(&cpc
->clk_setup
[PPC405EP_CPU_CLK
], CPU_clk
);
2314 /* Setup PLB clock */
2315 clk_setup(&cpc
->clk_setup
[PPC405EP_PLB_CLK
], PLB_clk
);
2316 /* Setup OPB clock */
2317 clk_setup(&cpc
->clk_setup
[PPC405EP_OPB_CLK
], OPB_clk
);
2318 /* Setup external clock */
2319 clk_setup(&cpc
->clk_setup
[PPC405EP_EBC_CLK
], EBC_clk
);
2320 /* Setup MAL clock */
2321 clk_setup(&cpc
->clk_setup
[PPC405EP_MAL_CLK
], MAL_clk
);
2322 /* Setup PCI clock */
2323 clk_setup(&cpc
->clk_setup
[PPC405EP_PCI_CLK
], PCI_clk
);
2324 /* Setup UART0 clock */
2325 clk_setup(&cpc
->clk_setup
[PPC405EP_UART0_CLK
], UART0_clk
);
2326 /* Setup UART1 clock */
2327 clk_setup(&cpc
->clk_setup
[PPC405EP_UART1_CLK
], UART1_clk
);
2330 static uint32_t dcr_read_epcpc (void *opaque
, int dcrn
)
2332 ppc405ep_cpc_t
*cpc
;
2337 case PPC405EP_CPC0_BOOT
:
2340 case PPC405EP_CPC0_EPCTL
:
2343 case PPC405EP_CPC0_PLLMR0
:
2344 ret
= cpc
->pllmr
[0];
2346 case PPC405EP_CPC0_PLLMR1
:
2347 ret
= cpc
->pllmr
[1];
2349 case PPC405EP_CPC0_UCR
:
2352 case PPC405EP_CPC0_SRR
:
2355 case PPC405EP_CPC0_JTAGID
:
2358 case PPC405EP_CPC0_PCI
:
2362 /* Avoid gcc warning */
2370 static void dcr_write_epcpc (void *opaque
, int dcrn
, uint32_t val
)
2372 ppc405ep_cpc_t
*cpc
;
2376 case PPC405EP_CPC0_BOOT
:
2377 /* Read-only register */
2379 case PPC405EP_CPC0_EPCTL
:
2380 /* Don't care for now */
2381 cpc
->epctl
= val
& 0xC00000F3;
2383 case PPC405EP_CPC0_PLLMR0
:
2384 cpc
->pllmr
[0] = val
& 0x00633333;
2385 ppc405ep_compute_clocks(cpc
);
2387 case PPC405EP_CPC0_PLLMR1
:
2388 cpc
->pllmr
[1] = val
& 0xC0F73FFF;
2389 ppc405ep_compute_clocks(cpc
);
2391 case PPC405EP_CPC0_UCR
:
2392 /* UART control - don't care for now */
2393 cpc
->ucr
= val
& 0x003F7F7F;
2395 case PPC405EP_CPC0_SRR
:
2398 case PPC405EP_CPC0_JTAGID
:
2401 case PPC405EP_CPC0_PCI
:
2407 static void ppc405ep_cpc_reset (void *opaque
)
2409 ppc405ep_cpc_t
*cpc
= opaque
;
2411 cpc
->boot
= 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2412 cpc
->epctl
= 0x00000000;
2413 cpc
->pllmr
[0] = 0x00011010;
2414 cpc
->pllmr
[1] = 0x40000000;
2415 cpc
->ucr
= 0x00000000;
2416 cpc
->srr
= 0x00040000;
2417 cpc
->pci
= 0x00000000;
2418 cpc
->er
= 0x00000000;
2419 cpc
->fr
= 0x00000000;
2420 cpc
->sr
= 0x00000000;
2421 ppc405ep_compute_clocks(cpc
);
2424 /* XXX: sysclk should be between 25 and 100 MHz */
2425 static void ppc405ep_cpc_init (CPUPPCState
*env
, clk_setup_t clk_setup
[8],
2428 ppc405ep_cpc_t
*cpc
;
2430 cpc
= g_malloc0(sizeof(ppc405ep_cpc_t
));
2431 memcpy(cpc
->clk_setup
, clk_setup
,
2432 PPC405EP_CLK_NB
* sizeof(clk_setup_t
));
2433 cpc
->jtagid
= 0x20267049;
2434 cpc
->sysclk
= sysclk
;
2435 qemu_register_reset(&ppc405ep_cpc_reset
, cpc
);
2436 ppc_dcr_register(env
, PPC405EP_CPC0_BOOT
, cpc
,
2437 &dcr_read_epcpc
, &dcr_write_epcpc
);
2438 ppc_dcr_register(env
, PPC405EP_CPC0_EPCTL
, cpc
,
2439 &dcr_read_epcpc
, &dcr_write_epcpc
);
2440 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR0
, cpc
,
2441 &dcr_read_epcpc
, &dcr_write_epcpc
);
2442 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR1
, cpc
,
2443 &dcr_read_epcpc
, &dcr_write_epcpc
);
2444 ppc_dcr_register(env
, PPC405EP_CPC0_UCR
, cpc
,
2445 &dcr_read_epcpc
, &dcr_write_epcpc
);
2446 ppc_dcr_register(env
, PPC405EP_CPC0_SRR
, cpc
,
2447 &dcr_read_epcpc
, &dcr_write_epcpc
);
2448 ppc_dcr_register(env
, PPC405EP_CPC0_JTAGID
, cpc
,
2449 &dcr_read_epcpc
, &dcr_write_epcpc
);
2450 ppc_dcr_register(env
, PPC405EP_CPC0_PCI
, cpc
,
2451 &dcr_read_epcpc
, &dcr_write_epcpc
);
2453 ppc_dcr_register(env
, PPC405EP_CPC0_ER
, cpc
,
2454 &dcr_read_epcpc
, &dcr_write_epcpc
);
2455 ppc_dcr_register(env
, PPC405EP_CPC0_FR
, cpc
,
2456 &dcr_read_epcpc
, &dcr_write_epcpc
);
2457 ppc_dcr_register(env
, PPC405EP_CPC0_SR
, cpc
,
2458 &dcr_read_epcpc
, &dcr_write_epcpc
);
2462 CPUPPCState
*ppc405ep_init(MemoryRegion
*address_space_mem
,
2463 MemoryRegion ram_memories
[2],
2464 hwaddr ram_bases
[2],
2465 hwaddr ram_sizes
[2],
2466 uint32_t sysclk
, qemu_irq
**picp
,
2469 clk_setup_t clk_setup
[PPC405EP_CLK_NB
], tlb_clk_setup
;
2470 qemu_irq dma_irqs
[4], gpt_irqs
[5], mal_irqs
[4];
2473 qemu_irq
*pic
, *irqs
;
2475 memset(clk_setup
, 0, sizeof(clk_setup
));
2477 cpu
= ppc4xx_init("405ep", &clk_setup
[PPC405EP_CPU_CLK
],
2478 &tlb_clk_setup
, sysclk
);
2480 clk_setup
[PPC405EP_CPU_CLK
].cb
= tlb_clk_setup
.cb
;
2481 clk_setup
[PPC405EP_CPU_CLK
].opaque
= tlb_clk_setup
.opaque
;
2482 /* Internal devices init */
2483 /* Memory mapped devices registers */
2485 ppc4xx_plb_init(env
);
2486 /* PLB to OPB bridge */
2487 ppc4xx_pob_init(env
);
2489 ppc4xx_opba_init(0xef600600);
2490 /* Initialize timers */
2491 ppc_booke_timers_init(cpu
, sysclk
, 0);
2492 /* Universal interrupt controller */
2493 irqs
= g_malloc0(sizeof(qemu_irq
) * PPCUIC_OUTPUT_NB
);
2494 irqs
[PPCUIC_OUTPUT_INT
] =
2495 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_INT
];
2496 irqs
[PPCUIC_OUTPUT_CINT
] =
2497 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_CINT
];
2498 pic
= ppcuic_init(env
, irqs
, 0x0C0, 0, 1);
2500 /* SDRAM controller */
2501 /* XXX 405EP has no ECC interrupt */
2502 ppc4xx_sdram_init(env
, pic
[17], 2, ram_memories
,
2503 ram_bases
, ram_sizes
, do_init
);
2504 /* External bus controller */
2505 ppc405_ebc_init(env
);
2506 /* DMA controller */
2507 dma_irqs
[0] = pic
[5];
2508 dma_irqs
[1] = pic
[6];
2509 dma_irqs
[2] = pic
[7];
2510 dma_irqs
[3] = pic
[8];
2511 ppc405_dma_init(env
, dma_irqs
);
2512 /* IIC controller */
2513 ppc405_i2c_init(0xef600500, pic
[2]);
2515 ppc405_gpio_init(0xef600700);
2517 if (serial_hds
[0] != NULL
) {
2518 serial_mm_init(address_space_mem
, 0xef600300, 0, pic
[0],
2519 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[0],
2522 if (serial_hds
[1] != NULL
) {
2523 serial_mm_init(address_space_mem
, 0xef600400, 0, pic
[1],
2524 PPC_SERIAL_MM_BAUDBASE
, serial_hds
[1],
2528 ppc405_ocm_init(env
);
2530 gpt_irqs
[0] = pic
[19];
2531 gpt_irqs
[1] = pic
[20];
2532 gpt_irqs
[2] = pic
[21];
2533 gpt_irqs
[3] = pic
[22];
2534 gpt_irqs
[4] = pic
[23];
2535 ppc4xx_gpt_init(0xef600000, gpt_irqs
);
2537 /* Uses pic[3], pic[16], pic[18] */
2539 mal_irqs
[0] = pic
[11];
2540 mal_irqs
[1] = pic
[12];
2541 mal_irqs
[2] = pic
[13];
2542 mal_irqs
[3] = pic
[14];
2543 ppc405_mal_init(env
, mal_irqs
);
2545 /* Uses pic[9], pic[15], pic[17] */
2547 ppc405ep_cpc_init(env
, clk_setup
, sysclk
);