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target-m68k: Reorg flags handling
[qemu/ar7.git] / target-m68k / translate.c
blob85d5c95bc3f48c3818635150ba172b881fedcfb1
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 //#define DEBUG_DISPATCH 1
37
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
42
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
46 #include "qregs.def"
47 #undef DEFO32
48 #undef DEFO64
49 #undef DEFF64
50
51 static TCGv_i32 cpu_halted;
52 static TCGv_i32 cpu_exception_index;
53
54 static TCGv_env cpu_env;
55
56 static char cpu_reg_names[3*8*3 + 5*4];
57 static TCGv cpu_dregs[8];
58 static TCGv cpu_aregs[8];
59 static TCGv_i64 cpu_fregs[8];
60 static TCGv_i64 cpu_macc[4];
61
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) cpu_aregs[REG(insn, pos)]
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP cpu_aregs[7]
68
69 static TCGv NULL_QREG;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy;
73
74 #include "exec/gen-icount.h"
75
76 void m68k_tcg_init(void)
77 {
78 char *p;
79 int i;
80
81 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
82 tcg_ctx.tcg_env = cpu_env;
83
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
91 #include "qregs.def"
92 #undef DEFO32
93 #undef DEFO64
94 #undef DEFF64
95
96 cpu_halted = tcg_global_mem_new_i32(cpu_env,
97 -offsetof(M68kCPU, env) +
98 offsetof(CPUState, halted), "HALTED");
99 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
100 -offsetof(M68kCPU, env) +
101 offsetof(CPUState, exception_index),
102 "EXCEPTION");
103
104 p = cpu_reg_names;
105 for (i = 0; i < 8; i++) {
106 sprintf(p, "D%d", i);
107 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
108 offsetof(CPUM68KState, dregs[i]), p);
109 p += 3;
110 sprintf(p, "A%d", i);
111 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUM68KState, aregs[i]), p);
113 p += 3;
114 sprintf(p, "F%d", i);
115 cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
116 offsetof(CPUM68KState, fregs[i]), p);
117 p += 3;
118 }
119 for (i = 0; i < 4; i++) {
120 sprintf(p, "ACC%d", i);
121 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
122 offsetof(CPUM68KState, macc[i]), p);
123 p += 5;
124 }
125
126 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
127 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
128 }
129
130 /* internal defines */
131 typedef struct DisasContext {
132 CPUM68KState *env;
133 target_ulong insn_pc; /* Start of the current instruction. */
134 target_ulong pc;
135 int is_jmp;
136 CCOp cc_op; /* Current CC operation */
137 int cc_op_synced;
138 int user;
139 uint32_t fpcr;
140 struct TranslationBlock *tb;
141 int singlestep_enabled;
142 TCGv_i64 mactmp;
143 int done_mac;
144 } DisasContext;
145
146 #define DISAS_JUMP_NEXT 4
147
148 #if defined(CONFIG_USER_ONLY)
149 #define IS_USER(s) 1
150 #else
151 #define IS_USER(s) s->user
152 #endif
153
154 /* XXX: move that elsewhere */
155 /* ??? Fix exceptions. */
156 static void *gen_throws_exception;
157 #define gen_last_qop NULL
158
159 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
160
161 #ifdef DEBUG_DISPATCH
162 #define DISAS_INSN(name) \
163 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
164 uint16_t insn); \
165 static void disas_##name(CPUM68KState *env, DisasContext *s, \
166 uint16_t insn) \
167 { \
168 qemu_log("Dispatch " #name "\n"); \
169 real_disas_##name(env, s, insn); \
170 } \
171 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
172 uint16_t insn)
173 #else
174 #define DISAS_INSN(name) \
175 static void disas_##name(CPUM68KState *env, DisasContext *s, \
176 uint16_t insn)
177 #endif
178
179 static const uint8_t cc_op_live[CC_OP_NB] = {
180 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
181 [CC_OP_ADD] = CCF_X | CCF_N | CCF_V,
182 [CC_OP_SUB] = CCF_X | CCF_N | CCF_V,
183 [CC_OP_CMP] = CCF_X | CCF_N | CCF_V,
184 [CC_OP_LOGIC] = CCF_X | CCF_N
185 };
186
187 static void set_cc_op(DisasContext *s, CCOp op)
188 {
189 CCOp old_op = s->cc_op;
190 int dead;
191
192 if (old_op == op) {
193 return;
194 }
195 s->cc_op = op;
196 s->cc_op_synced = 0;
197
198 /* Discard CC computation that will no longer be used.
199 Note that X and N are never dead. */
200 dead = cc_op_live[old_op] & ~cc_op_live[op];
201 if (dead & CCF_C) {
202 tcg_gen_discard_i32(QREG_CC_C);
203 }
204 if (dead & CCF_Z) {
205 tcg_gen_discard_i32(QREG_CC_Z);
206 }
207 if (dead & CCF_V) {
208 tcg_gen_discard_i32(QREG_CC_V);
209 }
210 }
211
212 /* Update the CPU env CC_OP state. */
213 static void update_cc_op(DisasContext *s)
214 {
215 if (!s->cc_op_synced) {
216 s->cc_op_synced = 1;
217 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
218 }
219 }
220
221 /* Generate a load from the specified address. Narrow values are
222 sign extended to full register width. */
223 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
224 {
225 TCGv tmp;
226 int index = IS_USER(s);
227 tmp = tcg_temp_new_i32();
228 switch(opsize) {
229 case OS_BYTE:
230 if (sign)
231 tcg_gen_qemu_ld8s(tmp, addr, index);
232 else
233 tcg_gen_qemu_ld8u(tmp, addr, index);
234 break;
235 case OS_WORD:
236 if (sign)
237 tcg_gen_qemu_ld16s(tmp, addr, index);
238 else
239 tcg_gen_qemu_ld16u(tmp, addr, index);
240 break;
241 case OS_LONG:
242 case OS_SINGLE:
243 tcg_gen_qemu_ld32u(tmp, addr, index);
244 break;
245 default:
246 g_assert_not_reached();
247 }
248 gen_throws_exception = gen_last_qop;
249 return tmp;
250 }
251
252 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
253 {
254 TCGv_i64 tmp;
255 int index = IS_USER(s);
256 tmp = tcg_temp_new_i64();
257 tcg_gen_qemu_ldf64(tmp, addr, index);
258 gen_throws_exception = gen_last_qop;
259 return tmp;
260 }
261
262 /* Generate a store. */
263 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
264 {
265 int index = IS_USER(s);
266 switch(opsize) {
267 case OS_BYTE:
268 tcg_gen_qemu_st8(val, addr, index);
269 break;
270 case OS_WORD:
271 tcg_gen_qemu_st16(val, addr, index);
272 break;
273 case OS_LONG:
274 case OS_SINGLE:
275 tcg_gen_qemu_st32(val, addr, index);
276 break;
277 default:
278 g_assert_not_reached();
279 }
280 gen_throws_exception = gen_last_qop;
281 }
282
283 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
284 {
285 int index = IS_USER(s);
286 tcg_gen_qemu_stf64(val, addr, index);
287 gen_throws_exception = gen_last_qop;
288 }
289
290 typedef enum {
291 EA_STORE,
292 EA_LOADU,
293 EA_LOADS
294 } ea_what;
295
296 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
297 otherwise generate a store. */
298 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
299 ea_what what)
300 {
301 if (what == EA_STORE) {
302 gen_store(s, opsize, addr, val);
303 return store_dummy;
304 } else {
305 return gen_load(s, opsize, addr, what == EA_LOADS);
306 }
307 }
308
309 /* Read a 16-bit immediate constant */
310 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
311 {
312 uint16_t im;
313 im = cpu_lduw_code(env, s->pc);
314 s->pc += 2;
315 return im;
316 }
317
318 /* Read an 8-bit immediate constant */
319 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
320 {
321 return read_im16(env, s);
322 }
323
324 /* Read a 32-bit immediate constant. */
325 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
326 {
327 uint32_t im;
328 im = read_im16(env, s) << 16;
329 im |= 0xffff & read_im16(env, s);
330 return im;
331 }
332
333 /* Calculate and address index. */
334 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
335 {
336 TCGv add;
337 int scale;
338
339 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
340 if ((ext & 0x800) == 0) {
341 tcg_gen_ext16s_i32(tmp, add);
342 add = tmp;
343 }
344 scale = (ext >> 9) & 3;
345 if (scale != 0) {
346 tcg_gen_shli_i32(tmp, add, scale);
347 add = tmp;
348 }
349 return add;
350 }
351
352 /* Handle a base + index + displacement effective addresss.
353 A NULL_QREG base means pc-relative. */
354 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
355 {
356 uint32_t offset;
357 uint16_t ext;
358 TCGv add;
359 TCGv tmp;
360 uint32_t bd, od;
361
362 offset = s->pc;
363 ext = read_im16(env, s);
364
365 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
366 return NULL_QREG;
367
368 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
369 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
370 ext &= ~(3 << 9);
371 }
372
373 if (ext & 0x100) {
374 /* full extension word format */
375 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
376 return NULL_QREG;
377
378 if ((ext & 0x30) > 0x10) {
379 /* base displacement */
380 if ((ext & 0x30) == 0x20) {
381 bd = (int16_t)read_im16(env, s);
382 } else {
383 bd = read_im32(env, s);
384 }
385 } else {
386 bd = 0;
387 }
388 tmp = tcg_temp_new();
389 if ((ext & 0x44) == 0) {
390 /* pre-index */
391 add = gen_addr_index(ext, tmp);
392 } else {
393 add = NULL_QREG;
394 }
395 if ((ext & 0x80) == 0) {
396 /* base not suppressed */
397 if (IS_NULL_QREG(base)) {
398 base = tcg_const_i32(offset + bd);
399 bd = 0;
400 }
401 if (!IS_NULL_QREG(add)) {
402 tcg_gen_add_i32(tmp, add, base);
403 add = tmp;
404 } else {
405 add = base;
406 }
407 }
408 if (!IS_NULL_QREG(add)) {
409 if (bd != 0) {
410 tcg_gen_addi_i32(tmp, add, bd);
411 add = tmp;
412 }
413 } else {
414 add = tcg_const_i32(bd);
415 }
416 if ((ext & 3) != 0) {
417 /* memory indirect */
418 base = gen_load(s, OS_LONG, add, 0);
419 if ((ext & 0x44) == 4) {
420 add = gen_addr_index(ext, tmp);
421 tcg_gen_add_i32(tmp, add, base);
422 add = tmp;
423 } else {
424 add = base;
425 }
426 if ((ext & 3) > 1) {
427 /* outer displacement */
428 if ((ext & 3) == 2) {
429 od = (int16_t)read_im16(env, s);
430 } else {
431 od = read_im32(env, s);
432 }
433 } else {
434 od = 0;
435 }
436 if (od != 0) {
437 tcg_gen_addi_i32(tmp, add, od);
438 add = tmp;
439 }
440 }
441 } else {
442 /* brief extension word format */
443 tmp = tcg_temp_new();
444 add = gen_addr_index(ext, tmp);
445 if (!IS_NULL_QREG(base)) {
446 tcg_gen_add_i32(tmp, add, base);
447 if ((int8_t)ext)
448 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
449 } else {
450 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
451 }
452 add = tmp;
453 }
454 return add;
455 }
456
457 /* Evaluate all the CC flags. */
458
459 static void gen_flush_flags(DisasContext *s)
460 {
461 TCGv tmp;
462
463 switch (s->cc_op) {
464 case CC_OP_FLAGS:
465 return;
466 case CC_OP_DYNAMIC:
467 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
468 break;
469 default:
470 tmp = tcg_const_i32(s->cc_op);
471 gen_helper_flush_flags(cpu_env, tmp);
472 tcg_temp_free(tmp);
473 break;
474 }
475
476 /* Note that flush_flags also assigned to env->cc_op. */
477 s->cc_op = CC_OP_FLAGS;
478 s->cc_op_synced = 1;
479 }
480
481 /* Sign or zero extend a value. */
482
483 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
484 {
485 switch (opsize) {
486 case OS_BYTE:
487 if (sign) {
488 tcg_gen_ext8s_i32(res, val);
489 } else {
490 tcg_gen_ext8u_i32(res, val);
491 }
492 break;
493 case OS_WORD:
494 if (sign) {
495 tcg_gen_ext16s_i32(res, val);
496 } else {
497 tcg_gen_ext16u_i32(res, val);
498 }
499 break;
500 case OS_LONG:
501 tcg_gen_mov_i32(res, val);
502 break;
503 default:
504 g_assert_not_reached();
505 }
506 }
507
508 static TCGv gen_extend(TCGv val, int opsize, int sign)
509 {
510 TCGv tmp;
511
512 if (opsize == OS_LONG) {
513 tmp = val;
514 } else {
515 tmp = tcg_temp_new();
516 gen_ext(tmp, val, opsize, sign);
517 }
518
519 return tmp;
520 }
521
522 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
523 {
524 gen_ext(QREG_CC_N, val, opsize, 1);
525 set_cc_op(s, CC_OP_LOGIC);
526 }
527
528 static void gen_update_cc_add(TCGv dest, TCGv src)
529 {
530 tcg_gen_mov_i32(QREG_CC_N, dest);
531 tcg_gen_mov_i32(QREG_CC_V, src);
532 }
533
534 static inline int opsize_bytes(int opsize)
535 {
536 switch (opsize) {
537 case OS_BYTE: return 1;
538 case OS_WORD: return 2;
539 case OS_LONG: return 4;
540 case OS_SINGLE: return 4;
541 case OS_DOUBLE: return 8;
542 case OS_EXTENDED: return 12;
543 case OS_PACKED: return 12;
544 default:
545 g_assert_not_reached();
546 }
547 }
548
549 static inline int insn_opsize(int insn)
550 {
551 switch ((insn >> 6) & 3) {
552 case 0: return OS_BYTE;
553 case 1: return OS_WORD;
554 case 2: return OS_LONG;
555 default:
556 g_assert_not_reached();
557 }
558 }
559
560 /* Assign value to a register. If the width is less than the register width
561 only the low part of the register is set. */
562 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
563 {
564 TCGv tmp;
565 switch (opsize) {
566 case OS_BYTE:
567 tcg_gen_andi_i32(reg, reg, 0xffffff00);
568 tmp = tcg_temp_new();
569 tcg_gen_ext8u_i32(tmp, val);
570 tcg_gen_or_i32(reg, reg, tmp);
571 break;
572 case OS_WORD:
573 tcg_gen_andi_i32(reg, reg, 0xffff0000);
574 tmp = tcg_temp_new();
575 tcg_gen_ext16u_i32(tmp, val);
576 tcg_gen_or_i32(reg, reg, tmp);
577 break;
578 case OS_LONG:
579 case OS_SINGLE:
580 tcg_gen_mov_i32(reg, val);
581 break;
582 default:
583 g_assert_not_reached();
584 }
585 }
586
587 /* Generate code for an "effective address". Does not adjust the base
588 register for autoincrement addressing modes. */
589 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
590 int opsize)
591 {
592 TCGv reg;
593 TCGv tmp;
594 uint16_t ext;
595 uint32_t offset;
596
597 switch ((insn >> 3) & 7) {
598 case 0: /* Data register direct. */
599 case 1: /* Address register direct. */
600 return NULL_QREG;
601 case 2: /* Indirect register */
602 case 3: /* Indirect postincrement. */
603 return AREG(insn, 0);
604 case 4: /* Indirect predecrememnt. */
605 reg = AREG(insn, 0);
606 tmp = tcg_temp_new();
607 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
608 return tmp;
609 case 5: /* Indirect displacement. */
610 reg = AREG(insn, 0);
611 tmp = tcg_temp_new();
612 ext = read_im16(env, s);
613 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
614 return tmp;
615 case 6: /* Indirect index + displacement. */
616 reg = AREG(insn, 0);
617 return gen_lea_indexed(env, s, reg);
618 case 7: /* Other */
619 switch (insn & 7) {
620 case 0: /* Absolute short. */
621 offset = (int16_t)read_im16(env, s);
622 return tcg_const_i32(offset);
623 case 1: /* Absolute long. */
624 offset = read_im32(env, s);
625 return tcg_const_i32(offset);
626 case 2: /* pc displacement */
627 offset = s->pc;
628 offset += (int16_t)read_im16(env, s);
629 return tcg_const_i32(offset);
630 case 3: /* pc index+displacement. */
631 return gen_lea_indexed(env, s, NULL_QREG);
632 case 4: /* Immediate. */
633 default:
634 return NULL_QREG;
635 }
636 }
637 /* Should never happen. */
638 return NULL_QREG;
639 }
640
641 /* Helper function for gen_ea. Reuse the computed address between the
642 for read/write operands. */
643 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
644 uint16_t insn, int opsize, TCGv val,
645 TCGv *addrp, ea_what what)
646 {
647 TCGv tmp;
648
649 if (addrp && what == EA_STORE) {
650 tmp = *addrp;
651 } else {
652 tmp = gen_lea(env, s, insn, opsize);
653 if (IS_NULL_QREG(tmp))
654 return tmp;
655 if (addrp)
656 *addrp = tmp;
657 }
658 return gen_ldst(s, opsize, tmp, val, what);
659 }
660
661 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
662 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
663 ADDRP is non-null for readwrite operands. */
664 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
665 int opsize, TCGv val, TCGv *addrp, ea_what what)
666 {
667 TCGv reg;
668 TCGv result;
669 uint32_t offset;
670
671 switch ((insn >> 3) & 7) {
672 case 0: /* Data register direct. */
673 reg = DREG(insn, 0);
674 if (what == EA_STORE) {
675 gen_partset_reg(opsize, reg, val);
676 return store_dummy;
677 } else {
678 return gen_extend(reg, opsize, what == EA_LOADS);
679 }
680 case 1: /* Address register direct. */
681 reg = AREG(insn, 0);
682 if (what == EA_STORE) {
683 tcg_gen_mov_i32(reg, val);
684 return store_dummy;
685 } else {
686 return gen_extend(reg, opsize, what == EA_LOADS);
687 }
688 case 2: /* Indirect register */
689 reg = AREG(insn, 0);
690 return gen_ldst(s, opsize, reg, val, what);
691 case 3: /* Indirect postincrement. */
692 reg = AREG(insn, 0);
693 result = gen_ldst(s, opsize, reg, val, what);
694 /* ??? This is not exception safe. The instruction may still
695 fault after this point. */
696 if (what == EA_STORE || !addrp)
697 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
698 return result;
699 case 4: /* Indirect predecrememnt. */
700 {
701 TCGv tmp;
702 if (addrp && what == EA_STORE) {
703 tmp = *addrp;
704 } else {
705 tmp = gen_lea(env, s, insn, opsize);
706 if (IS_NULL_QREG(tmp))
707 return tmp;
708 if (addrp)
709 *addrp = tmp;
710 }
711 result = gen_ldst(s, opsize, tmp, val, what);
712 /* ??? This is not exception safe. The instruction may still
713 fault after this point. */
714 if (what == EA_STORE || !addrp) {
715 reg = AREG(insn, 0);
716 tcg_gen_mov_i32(reg, tmp);
717 }
718 }
719 return result;
720 case 5: /* Indirect displacement. */
721 case 6: /* Indirect index + displacement. */
722 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
723 case 7: /* Other */
724 switch (insn & 7) {
725 case 0: /* Absolute short. */
726 case 1: /* Absolute long. */
727 case 2: /* pc displacement */
728 case 3: /* pc index+displacement. */
729 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
730 case 4: /* Immediate. */
731 /* Sign extend values for consistency. */
732 switch (opsize) {
733 case OS_BYTE:
734 if (what == EA_LOADS) {
735 offset = (int8_t)read_im8(env, s);
736 } else {
737 offset = read_im8(env, s);
738 }
739 break;
740 case OS_WORD:
741 if (what == EA_LOADS) {
742 offset = (int16_t)read_im16(env, s);
743 } else {
744 offset = read_im16(env, s);
745 }
746 break;
747 case OS_LONG:
748 offset = read_im32(env, s);
749 break;
750 default:
751 g_assert_not_reached();
752 }
753 return tcg_const_i32(offset);
754 default:
755 return NULL_QREG;
756 }
757 }
758 /* Should never happen. */
759 return NULL_QREG;
760 }
761
762 /* This generates a conditional branch, clobbering all temporaries. */
763 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
764 {
765 TCGv tmp, tmp2;
766 TCGCond tcond;
767
768 /* TODO: Optimize compare/branch pairs rather than always flushing
769 flag state to CC_OP_FLAGS. */
770 gen_flush_flags(s);
771 update_cc_op(s);
772 switch (cond) {
773 case 0: /* T */
774 tcg_gen_br(l1);
775 return;
776 case 1: /* F */
777 return;
778 case 2: /* HI (!C && !Z) -> !(C || Z)*/
779 case 3: /* LS (C || Z) */
780 tmp = tcg_temp_new();
781 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
782 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
783 tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
784 break;
785 case 4: /* CC (!C) */
786 case 5: /* CS (C) */
787 tmp = QREG_CC_C;
788 tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
789 break;
790 case 6: /* NE (!Z) */
791 case 7: /* EQ (Z) */
792 tmp = QREG_CC_Z;
793 tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE);
794 break;
795 case 8: /* VC (!V) */
796 case 9: /* VS (V) */
797 tmp = QREG_CC_V;
798 tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
799 break;
800 case 10: /* PL (!N) */
801 case 11: /* MI (N) */
802 tmp = QREG_CC_N;
803 tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
804 break;
805 case 12: /* GE (!(N ^ V)) */
806 case 13: /* LT (N ^ V) */
807 tmp = tcg_temp_new();
808 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
809 tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
810 break;
811 case 14: /* GT (!(Z || (N ^ V))) */
812 case 15: /* LE (Z || (N ^ V)) */
813 tmp = tcg_temp_new();
814 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
815 tcg_gen_neg_i32(tmp, tmp);
816 tmp2 = tcg_temp_new();
817 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
818 tcg_gen_or_i32(tmp, tmp, tmp2);
819 tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
820 break;
821 default:
822 /* Should ever happen. */
823 abort();
824 }
825 tcg_gen_brcondi_i32(tcond, tmp, 0, l1);
826 }
827
828 DISAS_INSN(scc)
829 {
830 TCGLabel *l1;
831 int cond;
832 TCGv reg;
833
834 l1 = gen_new_label();
835 cond = (insn >> 8) & 0xf;
836 reg = DREG(insn, 0);
837 tcg_gen_andi_i32(reg, reg, 0xffffff00);
838 /* This is safe because we modify the reg directly, with no other values
839 live. */
840 gen_jmpcc(s, cond ^ 1, l1);
841 tcg_gen_ori_i32(reg, reg, 0xff);
842 gen_set_label(l1);
843 }
844
845 /* Force a TB lookup after an instruction that changes the CPU state. */
846 static void gen_lookup_tb(DisasContext *s)
847 {
848 update_cc_op(s);
849 tcg_gen_movi_i32(QREG_PC, s->pc);
850 s->is_jmp = DISAS_UPDATE;
851 }
852
853 /* Generate a jump to an immediate address. */
854 static void gen_jmp_im(DisasContext *s, uint32_t dest)
855 {
856 update_cc_op(s);
857 tcg_gen_movi_i32(QREG_PC, dest);
858 s->is_jmp = DISAS_JUMP;
859 }
860
861 /* Generate a jump to the address in qreg DEST. */
862 static void gen_jmp(DisasContext *s, TCGv dest)
863 {
864 update_cc_op(s);
865 tcg_gen_mov_i32(QREG_PC, dest);
866 s->is_jmp = DISAS_JUMP;
867 }
868
869 static void gen_exception(DisasContext *s, uint32_t where, int nr)
870 {
871 update_cc_op(s);
872 gen_jmp_im(s, where);
873 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
874 }
875
876 static inline void gen_addr_fault(DisasContext *s)
877 {
878 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
879 }
880
881 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
882 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
883 op_sign ? EA_LOADS : EA_LOADU); \
884 if (IS_NULL_QREG(result)) { \
885 gen_addr_fault(s); \
886 return; \
887 } \
888 } while (0)
889
890 #define DEST_EA(env, insn, opsize, val, addrp) do { \
891 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
892 if (IS_NULL_QREG(ea_result)) { \
893 gen_addr_fault(s); \
894 return; \
895 } \
896 } while (0)
897
898 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
899 {
900 #ifndef CONFIG_USER_ONLY
901 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
902 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
903 #else
904 return true;
905 #endif
906 }
907
908 /* Generate a jump to an immediate address. */
909 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
910 {
911 if (unlikely(s->singlestep_enabled)) {
912 gen_exception(s, dest, EXCP_DEBUG);
913 } else if (use_goto_tb(s, dest)) {
914 tcg_gen_goto_tb(n);
915 tcg_gen_movi_i32(QREG_PC, dest);
916 tcg_gen_exit_tb((uintptr_t)s->tb + n);
917 } else {
918 gen_jmp_im(s, dest);
919 tcg_gen_exit_tb(0);
920 }
921 s->is_jmp = DISAS_TB_JUMP;
922 }
923
924 DISAS_INSN(undef_mac)
925 {
926 gen_exception(s, s->pc - 2, EXCP_LINEA);
927 }
928
929 DISAS_INSN(undef_fpu)
930 {
931 gen_exception(s, s->pc - 2, EXCP_LINEF);
932 }
933
934 DISAS_INSN(undef)
935 {
936 M68kCPU *cpu = m68k_env_get_cpu(env);
937
938 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
939 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
940 }
941
942 DISAS_INSN(mulw)
943 {
944 TCGv reg;
945 TCGv tmp;
946 TCGv src;
947 int sign;
948
949 sign = (insn & 0x100) != 0;
950 reg = DREG(insn, 9);
951 tmp = tcg_temp_new();
952 if (sign)
953 tcg_gen_ext16s_i32(tmp, reg);
954 else
955 tcg_gen_ext16u_i32(tmp, reg);
956 SRC_EA(env, src, OS_WORD, sign, NULL);
957 tcg_gen_mul_i32(tmp, tmp, src);
958 tcg_gen_mov_i32(reg, tmp);
959 gen_logic_cc(s, tmp, OS_WORD);
960 }
961
962 DISAS_INSN(divw)
963 {
964 TCGv reg;
965 TCGv tmp;
966 TCGv src;
967 int sign;
968
969 sign = (insn & 0x100) != 0;
970 reg = DREG(insn, 9);
971 if (sign) {
972 tcg_gen_ext16s_i32(QREG_DIV1, reg);
973 } else {
974 tcg_gen_ext16u_i32(QREG_DIV1, reg);
975 }
976 SRC_EA(env, src, OS_WORD, sign, NULL);
977 tcg_gen_mov_i32(QREG_DIV2, src);
978 if (sign) {
979 gen_helper_divs(cpu_env, tcg_const_i32(1));
980 } else {
981 gen_helper_divu(cpu_env, tcg_const_i32(1));
982 }
983
984 tmp = tcg_temp_new();
985 src = tcg_temp_new();
986 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
987 tcg_gen_shli_i32(src, QREG_DIV2, 16);
988 tcg_gen_or_i32(reg, tmp, src);
989
990 set_cc_op(s, CC_OP_FLAGS);
991 }
992
993 DISAS_INSN(divl)
994 {
995 TCGv num;
996 TCGv den;
997 TCGv reg;
998 uint16_t ext;
999
1000 ext = read_im16(env, s);
1001 if (ext & 0x87f8) {
1002 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1003 return;
1004 }
1005 num = DREG(ext, 12);
1006 reg = DREG(ext, 0);
1007 tcg_gen_mov_i32(QREG_DIV1, num);
1008 SRC_EA(env, den, OS_LONG, 0, NULL);
1009 tcg_gen_mov_i32(QREG_DIV2, den);
1010 if (ext & 0x0800) {
1011 gen_helper_divs(cpu_env, tcg_const_i32(0));
1012 } else {
1013 gen_helper_divu(cpu_env, tcg_const_i32(0));
1014 }
1015 if ((ext & 7) == ((ext >> 12) & 7)) {
1016 /* div */
1017 tcg_gen_mov_i32 (reg, QREG_DIV1);
1018 } else {
1019 /* rem */
1020 tcg_gen_mov_i32 (reg, QREG_DIV2);
1021 }
1022 set_cc_op(s, CC_OP_FLAGS);
1023 }
1024
1025 DISAS_INSN(addsub)
1026 {
1027 TCGv reg;
1028 TCGv dest;
1029 TCGv src;
1030 TCGv tmp;
1031 TCGv addr;
1032 int add;
1033
1034 add = (insn & 0x4000) != 0;
1035 reg = DREG(insn, 9);
1036 dest = tcg_temp_new();
1037 if (insn & 0x100) {
1038 SRC_EA(env, tmp, OS_LONG, 0, &addr);
1039 src = reg;
1040 } else {
1041 tmp = reg;
1042 SRC_EA(env, src, OS_LONG, 0, NULL);
1043 }
1044 if (add) {
1045 tcg_gen_add_i32(dest, tmp, src);
1046 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1047 set_cc_op(s, CC_OP_ADD);
1048 } else {
1049 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1050 tcg_gen_sub_i32(dest, tmp, src);
1051 set_cc_op(s, CC_OP_SUB);
1052 }
1053 gen_update_cc_add(dest, src);
1054 if (insn & 0x100) {
1055 DEST_EA(env, insn, OS_LONG, dest, &addr);
1056 } else {
1057 tcg_gen_mov_i32(reg, dest);
1058 }
1059 }
1060
1061
1062 /* Reverse the order of the bits in REG. */
1063 DISAS_INSN(bitrev)
1064 {
1065 TCGv reg;
1066 reg = DREG(insn, 0);
1067 gen_helper_bitrev(reg, reg);
1068 }
1069
1070 DISAS_INSN(bitop_reg)
1071 {
1072 int opsize;
1073 int op;
1074 TCGv src1;
1075 TCGv src2;
1076 TCGv tmp;
1077 TCGv addr;
1078 TCGv dest;
1079
1080 if ((insn & 0x38) != 0)
1081 opsize = OS_BYTE;
1082 else
1083 opsize = OS_LONG;
1084 op = (insn >> 6) & 3;
1085
1086 gen_flush_flags(s);
1087
1088 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1089 src2 = DREG(insn, 9);
1090 dest = tcg_temp_new();
1091
1092 tmp = tcg_temp_new();
1093 if (opsize == OS_BYTE)
1094 tcg_gen_andi_i32(tmp, src2, 7);
1095 else
1096 tcg_gen_andi_i32(tmp, src2, 31);
1097
1098 src2 = tcg_const_i32(1);
1099 tcg_gen_shl_i32(src2, src2, tmp);
1100 tcg_temp_free(tmp);
1101
1102 tcg_gen_and_i32(QREG_CC_Z, src1, src2);
1103
1104 switch (op) {
1105 case 1: /* bchg */
1106 tcg_gen_xor_i32(dest, src1, src2);
1107 break;
1108 case 2: /* bclr */
1109 tcg_gen_andc_i32(dest, src1, src2);
1110 break;
1111 case 3: /* bset */
1112 tcg_gen_or_i32(dest, src1, src2);
1113 break;
1114 default: /* btst */
1115 break;
1116 }
1117 tcg_temp_free(src2);
1118 if (op) {
1119 DEST_EA(env, insn, opsize, dest, &addr);
1120 }
1121 tcg_temp_free(dest);
1122 }
1123
1124 DISAS_INSN(sats)
1125 {
1126 TCGv reg;
1127 reg = DREG(insn, 0);
1128 gen_flush_flags(s);
1129 gen_helper_sats(reg, reg, QREG_CC_V);
1130 gen_logic_cc(s, reg, OS_LONG);
1131 }
1132
1133 static void gen_push(DisasContext *s, TCGv val)
1134 {
1135 TCGv tmp;
1136
1137 tmp = tcg_temp_new();
1138 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1139 gen_store(s, OS_LONG, tmp, val);
1140 tcg_gen_mov_i32(QREG_SP, tmp);
1141 }
1142
1143 DISAS_INSN(movem)
1144 {
1145 TCGv addr;
1146 int i;
1147 uint16_t mask;
1148 TCGv reg;
1149 TCGv tmp;
1150 int is_load;
1151
1152 mask = read_im16(env, s);
1153 tmp = gen_lea(env, s, insn, OS_LONG);
1154 if (IS_NULL_QREG(tmp)) {
1155 gen_addr_fault(s);
1156 return;
1157 }
1158 addr = tcg_temp_new();
1159 tcg_gen_mov_i32(addr, tmp);
1160 is_load = ((insn & 0x0400) != 0);
1161 for (i = 0; i < 16; i++, mask >>= 1) {
1162 if (mask & 1) {
1163 if (i < 8)
1164 reg = DREG(i, 0);
1165 else
1166 reg = AREG(i, 0);
1167 if (is_load) {
1168 tmp = gen_load(s, OS_LONG, addr, 0);
1169 tcg_gen_mov_i32(reg, tmp);
1170 } else {
1171 gen_store(s, OS_LONG, addr, reg);
1172 }
1173 if (mask != 1)
1174 tcg_gen_addi_i32(addr, addr, 4);
1175 }
1176 }
1177 }
1178
1179 DISAS_INSN(bitop_im)
1180 {
1181 int opsize;
1182 int op;
1183 TCGv src1;
1184 uint32_t mask;
1185 int bitnum;
1186 TCGv tmp;
1187 TCGv addr;
1188
1189 if ((insn & 0x38) != 0)
1190 opsize = OS_BYTE;
1191 else
1192 opsize = OS_LONG;
1193 op = (insn >> 6) & 3;
1194
1195 bitnum = read_im16(env, s);
1196 if (bitnum & 0xff00) {
1197 disas_undef(env, s, insn);
1198 return;
1199 }
1200
1201 gen_flush_flags(s);
1202
1203 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1204
1205 if (opsize == OS_BYTE)
1206 bitnum &= 7;
1207 else
1208 bitnum &= 31;
1209 mask = 1 << bitnum;
1210
1211 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
1212
1213 if (op) {
1214 tmp = tcg_temp_new();
1215 switch (op) {
1216 case 1: /* bchg */
1217 tcg_gen_xori_i32(tmp, src1, mask);
1218 break;
1219 case 2: /* bclr */
1220 tcg_gen_andi_i32(tmp, src1, ~mask);
1221 break;
1222 case 3: /* bset */
1223 tcg_gen_ori_i32(tmp, src1, mask);
1224 break;
1225 default: /* btst */
1226 break;
1227 }
1228 DEST_EA(env, insn, opsize, tmp, &addr);
1229 tcg_temp_free(tmp);
1230 }
1231 }
1232
1233 DISAS_INSN(arith_im)
1234 {
1235 int op;
1236 uint32_t im;
1237 TCGv src1;
1238 TCGv dest;
1239 TCGv addr;
1240
1241 op = (insn >> 9) & 7;
1242 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1243 im = read_im32(env, s);
1244 dest = tcg_temp_new();
1245 switch (op) {
1246 case 0: /* ori */
1247 tcg_gen_ori_i32(dest, src1, im);
1248 gen_logic_cc(s, dest, OS_LONG);
1249 break;
1250 case 1: /* andi */
1251 tcg_gen_andi_i32(dest, src1, im);
1252 gen_logic_cc(s, dest, OS_LONG);
1253 break;
1254 case 2: /* subi */
1255 tcg_gen_mov_i32(dest, src1);
1256 tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
1257 tcg_gen_subi_i32(dest, dest, im);
1258 gen_update_cc_add(dest, tcg_const_i32(im));
1259 set_cc_op(s, CC_OP_SUB);
1260 break;
1261 case 3: /* addi */
1262 tcg_gen_mov_i32(dest, src1);
1263 tcg_gen_addi_i32(dest, dest, im);
1264 gen_update_cc_add(dest, tcg_const_i32(im));
1265 tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
1266 set_cc_op(s, CC_OP_ADD);
1267 break;
1268 case 5: /* eori */
1269 tcg_gen_xori_i32(dest, src1, im);
1270 gen_logic_cc(s, dest, OS_LONG);
1271 break;
1272 case 6: /* cmpi */
1273 gen_update_cc_add(src1, tcg_const_i32(im));
1274 set_cc_op(s, CC_OP_CMP);
1275 break;
1276 default:
1277 abort();
1278 }
1279 if (op != 6) {
1280 DEST_EA(env, insn, OS_LONG, dest, &addr);
1281 }
1282 }
1283
1284 DISAS_INSN(byterev)
1285 {
1286 TCGv reg;
1287
1288 reg = DREG(insn, 0);
1289 tcg_gen_bswap32_i32(reg, reg);
1290 }
1291
1292 DISAS_INSN(move)
1293 {
1294 TCGv src;
1295 TCGv dest;
1296 int op;
1297 int opsize;
1298
1299 switch (insn >> 12) {
1300 case 1: /* move.b */
1301 opsize = OS_BYTE;
1302 break;
1303 case 2: /* move.l */
1304 opsize = OS_LONG;
1305 break;
1306 case 3: /* move.w */
1307 opsize = OS_WORD;
1308 break;
1309 default:
1310 abort();
1311 }
1312 SRC_EA(env, src, opsize, 1, NULL);
1313 op = (insn >> 6) & 7;
1314 if (op == 1) {
1315 /* movea */
1316 /* The value will already have been sign extended. */
1317 dest = AREG(insn, 9);
1318 tcg_gen_mov_i32(dest, src);
1319 } else {
1320 /* normal move */
1321 uint16_t dest_ea;
1322 dest_ea = ((insn >> 9) & 7) | (op << 3);
1323 DEST_EA(env, dest_ea, opsize, src, NULL);
1324 /* This will be correct because loads sign extend. */
1325 gen_logic_cc(s, src, opsize);
1326 }
1327 }
1328
1329 DISAS_INSN(negx)
1330 {
1331 TCGv reg;
1332
1333 gen_flush_flags(s);
1334 reg = DREG(insn, 0);
1335 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1336 }
1337
1338 DISAS_INSN(lea)
1339 {
1340 TCGv reg;
1341 TCGv tmp;
1342
1343 reg = AREG(insn, 9);
1344 tmp = gen_lea(env, s, insn, OS_LONG);
1345 if (IS_NULL_QREG(tmp)) {
1346 gen_addr_fault(s);
1347 return;
1348 }
1349 tcg_gen_mov_i32(reg, tmp);
1350 }
1351
1352 DISAS_INSN(clr)
1353 {
1354 int opsize;
1355
1356 opsize = insn_opsize(insn);
1357 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1358 gen_logic_cc(s, tcg_const_i32(0), opsize);
1359 }
1360
1361 static TCGv gen_get_ccr(DisasContext *s)
1362 {
1363 TCGv dest;
1364
1365 gen_flush_flags(s);
1366 update_cc_op(s);
1367 dest = tcg_temp_new();
1368 gen_helper_get_ccr(dest, cpu_env);
1369 return dest;
1370 }
1371
1372 DISAS_INSN(move_from_ccr)
1373 {
1374 TCGv ccr;
1375
1376 ccr = gen_get_ccr(s);
1377 DEST_EA(env, insn, OS_WORD, ccr, NULL);
1378 }
1379
1380 DISAS_INSN(neg)
1381 {
1382 TCGv reg;
1383 TCGv src1;
1384
1385 reg = DREG(insn, 0);
1386 src1 = tcg_temp_new();
1387 tcg_gen_mov_i32(src1, reg);
1388 tcg_gen_neg_i32(reg, src1);
1389 gen_update_cc_add(reg, src1);
1390 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0);
1391 set_cc_op(s, CC_OP_SUB);
1392 }
1393
1394 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1395 {
1396 if (ccr_only) {
1397 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
1398 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
1399 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
1400 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
1401 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
1402 } else {
1403 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
1404 }
1405 set_cc_op(s, CC_OP_FLAGS);
1406 }
1407
1408 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1409 int ccr_only)
1410 {
1411 if ((insn & 0x38) == 0) {
1412 if (ccr_only) {
1413 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
1414 } else {
1415 gen_helper_set_sr(cpu_env, DREG(insn, 0));
1416 }
1417 set_cc_op(s, CC_OP_FLAGS);
1418 } else if ((insn & 0x3f) == 0x3c) {
1419 uint16_t val;
1420 val = read_im16(env, s);
1421 gen_set_sr_im(s, val, ccr_only);
1422 } else {
1423 disas_undef(env, s, insn);
1424 }
1425 }
1426
1427
1428 DISAS_INSN(move_to_ccr)
1429 {
1430 gen_set_sr(env, s, insn, 1);
1431 }
1432
1433 DISAS_INSN(not)
1434 {
1435 TCGv reg;
1436
1437 reg = DREG(insn, 0);
1438 tcg_gen_not_i32(reg, reg);
1439 gen_logic_cc(s, reg, OS_LONG);
1440 }
1441
1442 DISAS_INSN(swap)
1443 {
1444 TCGv src1;
1445 TCGv src2;
1446 TCGv reg;
1447
1448 src1 = tcg_temp_new();
1449 src2 = tcg_temp_new();
1450 reg = DREG(insn, 0);
1451 tcg_gen_shli_i32(src1, reg, 16);
1452 tcg_gen_shri_i32(src2, reg, 16);
1453 tcg_gen_or_i32(reg, src1, src2);
1454 gen_logic_cc(s, reg, OS_LONG);
1455 }
1456
1457 DISAS_INSN(pea)
1458 {
1459 TCGv tmp;
1460
1461 tmp = gen_lea(env, s, insn, OS_LONG);
1462 if (IS_NULL_QREG(tmp)) {
1463 gen_addr_fault(s);
1464 return;
1465 }
1466 gen_push(s, tmp);
1467 }
1468
1469 DISAS_INSN(ext)
1470 {
1471 int op;
1472 TCGv reg;
1473 TCGv tmp;
1474
1475 reg = DREG(insn, 0);
1476 op = (insn >> 6) & 7;
1477 tmp = tcg_temp_new();
1478 if (op == 3)
1479 tcg_gen_ext16s_i32(tmp, reg);
1480 else
1481 tcg_gen_ext8s_i32(tmp, reg);
1482 if (op == 2)
1483 gen_partset_reg(OS_WORD, reg, tmp);
1484 else
1485 tcg_gen_mov_i32(reg, tmp);
1486 gen_logic_cc(s, tmp, OS_LONG);
1487 }
1488
1489 DISAS_INSN(tst)
1490 {
1491 int opsize;
1492 TCGv tmp;
1493
1494 opsize = insn_opsize(insn);
1495 SRC_EA(env, tmp, opsize, 1, NULL);
1496 gen_logic_cc(s, tmp, opsize);
1497 }
1498
1499 DISAS_INSN(pulse)
1500 {
1501 /* Implemented as a NOP. */
1502 }
1503
1504 DISAS_INSN(illegal)
1505 {
1506 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1507 }
1508
1509 /* ??? This should be atomic. */
1510 DISAS_INSN(tas)
1511 {
1512 TCGv dest;
1513 TCGv src1;
1514 TCGv addr;
1515
1516 dest = tcg_temp_new();
1517 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1518 gen_logic_cc(s, src1, OS_BYTE);
1519 tcg_gen_ori_i32(dest, src1, 0x80);
1520 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1521 }
1522
1523 DISAS_INSN(mull)
1524 {
1525 uint16_t ext;
1526 TCGv reg;
1527 TCGv src1;
1528 TCGv dest;
1529
1530 /* The upper 32 bits of the product are discarded, so
1531 muls.l and mulu.l are functionally equivalent. */
1532 ext = read_im16(env, s);
1533 if (ext & 0x87ff) {
1534 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1535 return;
1536 }
1537 reg = DREG(ext, 12);
1538 SRC_EA(env, src1, OS_LONG, 0, NULL);
1539 dest = tcg_temp_new();
1540 tcg_gen_mul_i32(dest, src1, reg);
1541 tcg_gen_mov_i32(reg, dest);
1542 /* Unlike m68k, coldfire always clears the overflow bit. */
1543 gen_logic_cc(s, dest, OS_LONG);
1544 }
1545
1546 DISAS_INSN(link)
1547 {
1548 int16_t offset;
1549 TCGv reg;
1550 TCGv tmp;
1551
1552 offset = cpu_ldsw_code(env, s->pc);
1553 s->pc += 2;
1554 reg = AREG(insn, 0);
1555 tmp = tcg_temp_new();
1556 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1557 gen_store(s, OS_LONG, tmp, reg);
1558 if ((insn & 7) != 7)
1559 tcg_gen_mov_i32(reg, tmp);
1560 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1561 }
1562
1563 DISAS_INSN(unlk)
1564 {
1565 TCGv src;
1566 TCGv reg;
1567 TCGv tmp;
1568
1569 src = tcg_temp_new();
1570 reg = AREG(insn, 0);
1571 tcg_gen_mov_i32(src, reg);
1572 tmp = gen_load(s, OS_LONG, src, 0);
1573 tcg_gen_mov_i32(reg, tmp);
1574 tcg_gen_addi_i32(QREG_SP, src, 4);
1575 }
1576
1577 DISAS_INSN(nop)
1578 {
1579 }
1580
1581 DISAS_INSN(rts)
1582 {
1583 TCGv tmp;
1584
1585 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1586 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1587 gen_jmp(s, tmp);
1588 }
1589
1590 DISAS_INSN(jump)
1591 {
1592 TCGv tmp;
1593
1594 /* Load the target address first to ensure correct exception
1595 behavior. */
1596 tmp = gen_lea(env, s, insn, OS_LONG);
1597 if (IS_NULL_QREG(tmp)) {
1598 gen_addr_fault(s);
1599 return;
1600 }
1601 if ((insn & 0x40) == 0) {
1602 /* jsr */
1603 gen_push(s, tcg_const_i32(s->pc));
1604 }
1605 gen_jmp(s, tmp);
1606 }
1607
1608 DISAS_INSN(addsubq)
1609 {
1610 TCGv src1;
1611 TCGv src2;
1612 TCGv dest;
1613 int val;
1614 TCGv addr;
1615
1616 SRC_EA(env, src1, OS_LONG, 0, &addr);
1617 val = (insn >> 9) & 7;
1618 if (val == 0)
1619 val = 8;
1620 dest = tcg_temp_new();
1621 tcg_gen_mov_i32(dest, src1);
1622 if ((insn & 0x38) == 0x08) {
1623 /* Don't update condition codes if the destination is an
1624 address register. */
1625 if (insn & 0x0100) {
1626 tcg_gen_subi_i32(dest, dest, val);
1627 } else {
1628 tcg_gen_addi_i32(dest, dest, val);
1629 }
1630 } else {
1631 src2 = tcg_const_i32(val);
1632 if (insn & 0x0100) {
1633 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2);
1634 tcg_gen_sub_i32(dest, dest, src2);
1635 set_cc_op(s, CC_OP_SUB);
1636 } else {
1637 tcg_gen_add_i32(dest, dest, src2);
1638 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2);
1639 set_cc_op(s, CC_OP_ADD);
1640 }
1641 gen_update_cc_add(dest, src2);
1642 }
1643 DEST_EA(env, insn, OS_LONG, dest, &addr);
1644 }
1645
1646 DISAS_INSN(tpf)
1647 {
1648 switch (insn & 7) {
1649 case 2: /* One extension word. */
1650 s->pc += 2;
1651 break;
1652 case 3: /* Two extension words. */
1653 s->pc += 4;
1654 break;
1655 case 4: /* No extension words. */
1656 break;
1657 default:
1658 disas_undef(env, s, insn);
1659 }
1660 }
1661
1662 DISAS_INSN(branch)
1663 {
1664 int32_t offset;
1665 uint32_t base;
1666 int op;
1667 TCGLabel *l1;
1668
1669 base = s->pc;
1670 op = (insn >> 8) & 0xf;
1671 offset = (int8_t)insn;
1672 if (offset == 0) {
1673 offset = (int16_t)read_im16(env, s);
1674 } else if (offset == -1) {
1675 offset = read_im32(env, s);
1676 }
1677 if (op == 1) {
1678 /* bsr */
1679 gen_push(s, tcg_const_i32(s->pc));
1680 }
1681 update_cc_op(s);
1682 if (op > 1) {
1683 /* Bcc */
1684 l1 = gen_new_label();
1685 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1686 gen_jmp_tb(s, 1, base + offset);
1687 gen_set_label(l1);
1688 gen_jmp_tb(s, 0, s->pc);
1689 } else {
1690 /* Unconditional branch. */
1691 gen_jmp_tb(s, 0, base + offset);
1692 }
1693 }
1694
1695 DISAS_INSN(moveq)
1696 {
1697 uint32_t val;
1698
1699 val = (int8_t)insn;
1700 tcg_gen_movi_i32(DREG(insn, 9), val);
1701 gen_logic_cc(s, tcg_const_i32(val), OS_LONG);
1702 }
1703
1704 DISAS_INSN(mvzs)
1705 {
1706 int opsize;
1707 TCGv src;
1708 TCGv reg;
1709
1710 if (insn & 0x40)
1711 opsize = OS_WORD;
1712 else
1713 opsize = OS_BYTE;
1714 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1715 reg = DREG(insn, 9);
1716 tcg_gen_mov_i32(reg, src);
1717 gen_logic_cc(s, src, opsize);
1718 }
1719
1720 DISAS_INSN(or)
1721 {
1722 TCGv reg;
1723 TCGv dest;
1724 TCGv src;
1725 TCGv addr;
1726
1727 reg = DREG(insn, 9);
1728 dest = tcg_temp_new();
1729 if (insn & 0x100) {
1730 SRC_EA(env, src, OS_LONG, 0, &addr);
1731 tcg_gen_or_i32(dest, src, reg);
1732 DEST_EA(env, insn, OS_LONG, dest, &addr);
1733 } else {
1734 SRC_EA(env, src, OS_LONG, 0, NULL);
1735 tcg_gen_or_i32(dest, src, reg);
1736 tcg_gen_mov_i32(reg, dest);
1737 }
1738 gen_logic_cc(s, dest, OS_LONG);
1739 }
1740
1741 DISAS_INSN(suba)
1742 {
1743 TCGv src;
1744 TCGv reg;
1745
1746 SRC_EA(env, src, OS_LONG, 0, NULL);
1747 reg = AREG(insn, 9);
1748 tcg_gen_sub_i32(reg, reg, src);
1749 }
1750
1751 DISAS_INSN(subx)
1752 {
1753 TCGv reg;
1754 TCGv src;
1755
1756 gen_flush_flags(s);
1757 reg = DREG(insn, 9);
1758 src = DREG(insn, 0);
1759 gen_helper_subx_cc(reg, cpu_env, reg, src);
1760 }
1761
1762 DISAS_INSN(mov3q)
1763 {
1764 TCGv src;
1765 int val;
1766
1767 val = (insn >> 9) & 7;
1768 if (val == 0)
1769 val = -1;
1770 src = tcg_const_i32(val);
1771 gen_logic_cc(s, src, OS_LONG);
1772 DEST_EA(env, insn, OS_LONG, src, NULL);
1773 }
1774
1775 DISAS_INSN(cmp)
1776 {
1777 TCGv src;
1778 TCGv reg;
1779 int opsize;
1780
1781 opsize = insn_opsize(insn);
1782 SRC_EA(env, src, opsize, -1, NULL);
1783 reg = DREG(insn, 9);
1784 gen_update_cc_add(reg, src);
1785 set_cc_op(s, CC_OP_CMP);
1786 }
1787
1788 DISAS_INSN(cmpa)
1789 {
1790 int opsize;
1791 TCGv src;
1792 TCGv reg;
1793
1794 if (insn & 0x100) {
1795 opsize = OS_LONG;
1796 } else {
1797 opsize = OS_WORD;
1798 }
1799 SRC_EA(env, src, opsize, 1, NULL);
1800 reg = AREG(insn, 9);
1801 gen_update_cc_add(reg, src);
1802 set_cc_op(s, CC_OP_CMP);
1803 }
1804
1805 DISAS_INSN(eor)
1806 {
1807 TCGv src;
1808 TCGv reg;
1809 TCGv dest;
1810 TCGv addr;
1811
1812 SRC_EA(env, src, OS_LONG, 0, &addr);
1813 reg = DREG(insn, 9);
1814 dest = tcg_temp_new();
1815 tcg_gen_xor_i32(dest, src, reg);
1816 gen_logic_cc(s, dest, OS_LONG);
1817 DEST_EA(env, insn, OS_LONG, dest, &addr);
1818 }
1819
1820 DISAS_INSN(and)
1821 {
1822 TCGv src;
1823 TCGv reg;
1824 TCGv dest;
1825 TCGv addr;
1826
1827 reg = DREG(insn, 9);
1828 dest = tcg_temp_new();
1829 if (insn & 0x100) {
1830 SRC_EA(env, src, OS_LONG, 0, &addr);
1831 tcg_gen_and_i32(dest, src, reg);
1832 DEST_EA(env, insn, OS_LONG, dest, &addr);
1833 } else {
1834 SRC_EA(env, src, OS_LONG, 0, NULL);
1835 tcg_gen_and_i32(dest, src, reg);
1836 tcg_gen_mov_i32(reg, dest);
1837 }
1838 gen_logic_cc(s, dest, OS_LONG);
1839 }
1840
1841 DISAS_INSN(adda)
1842 {
1843 TCGv src;
1844 TCGv reg;
1845
1846 SRC_EA(env, src, OS_LONG, 0, NULL);
1847 reg = AREG(insn, 9);
1848 tcg_gen_add_i32(reg, reg, src);
1849 }
1850
1851 DISAS_INSN(addx)
1852 {
1853 TCGv reg;
1854 TCGv src;
1855
1856 gen_flush_flags(s);
1857 reg = DREG(insn, 9);
1858 src = DREG(insn, 0);
1859 gen_helper_addx_cc(reg, cpu_env, reg, src);
1860 }
1861
1862 /* TODO: This could be implemented without helper functions. */
1863 DISAS_INSN(shift_im)
1864 {
1865 TCGv reg;
1866 int tmp;
1867 TCGv shift;
1868
1869 set_cc_op(s, CC_OP_FLAGS);
1870
1871 reg = DREG(insn, 0);
1872 tmp = (insn >> 9) & 7;
1873 if (tmp == 0)
1874 tmp = 8;
1875 shift = tcg_const_i32(tmp);
1876 /* No need to flush flags becuse we know we will set C flag. */
1877 if (insn & 0x100) {
1878 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1879 } else {
1880 if (insn & 8) {
1881 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1882 } else {
1883 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1884 }
1885 }
1886 }
1887
1888 DISAS_INSN(shift_reg)
1889 {
1890 TCGv reg;
1891 TCGv shift;
1892
1893 reg = DREG(insn, 0);
1894 shift = DREG(insn, 9);
1895 if (insn & 0x100) {
1896 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1897 } else {
1898 if (insn & 8) {
1899 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1900 } else {
1901 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1902 }
1903 }
1904 set_cc_op(s, CC_OP_FLAGS);
1905 }
1906
1907 DISAS_INSN(ff1)
1908 {
1909 TCGv reg;
1910 reg = DREG(insn, 0);
1911 gen_logic_cc(s, reg, OS_LONG);
1912 gen_helper_ff1(reg, reg);
1913 }
1914
1915 static TCGv gen_get_sr(DisasContext *s)
1916 {
1917 TCGv ccr;
1918 TCGv sr;
1919
1920 ccr = gen_get_ccr(s);
1921 sr = tcg_temp_new();
1922 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1923 tcg_gen_or_i32(sr, sr, ccr);
1924 return sr;
1925 }
1926
1927 DISAS_INSN(strldsr)
1928 {
1929 uint16_t ext;
1930 uint32_t addr;
1931
1932 addr = s->pc - 2;
1933 ext = read_im16(env, s);
1934 if (ext != 0x46FC) {
1935 gen_exception(s, addr, EXCP_UNSUPPORTED);
1936 return;
1937 }
1938 ext = read_im16(env, s);
1939 if (IS_USER(s) || (ext & SR_S) == 0) {
1940 gen_exception(s, addr, EXCP_PRIVILEGE);
1941 return;
1942 }
1943 gen_push(s, gen_get_sr(s));
1944 gen_set_sr_im(s, ext, 0);
1945 }
1946
1947 DISAS_INSN(move_from_sr)
1948 {
1949 TCGv sr;
1950
1951 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
1952 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1953 return;
1954 }
1955 sr = gen_get_sr(s);
1956 DEST_EA(env, insn, OS_WORD, sr, NULL);
1957 }
1958
1959 DISAS_INSN(move_to_sr)
1960 {
1961 if (IS_USER(s)) {
1962 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1963 return;
1964 }
1965 gen_set_sr(env, s, insn, 0);
1966 gen_lookup_tb(s);
1967 }
1968
1969 DISAS_INSN(move_from_usp)
1970 {
1971 if (IS_USER(s)) {
1972 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1973 return;
1974 }
1975 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
1976 offsetof(CPUM68KState, sp[M68K_USP]));
1977 }
1978
1979 DISAS_INSN(move_to_usp)
1980 {
1981 if (IS_USER(s)) {
1982 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1983 return;
1984 }
1985 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
1986 offsetof(CPUM68KState, sp[M68K_USP]));
1987 }
1988
1989 DISAS_INSN(halt)
1990 {
1991 gen_exception(s, s->pc, EXCP_HALT_INSN);
1992 }
1993
1994 DISAS_INSN(stop)
1995 {
1996 uint16_t ext;
1997
1998 if (IS_USER(s)) {
1999 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2000 return;
2001 }
2002
2003 ext = read_im16(env, s);
2004
2005 gen_set_sr_im(s, ext, 0);
2006 tcg_gen_movi_i32(cpu_halted, 1);
2007 gen_exception(s, s->pc, EXCP_HLT);
2008 }
2009
2010 DISAS_INSN(rte)
2011 {
2012 if (IS_USER(s)) {
2013 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2014 return;
2015 }
2016 gen_exception(s, s->pc - 2, EXCP_RTE);
2017 }
2018
2019 DISAS_INSN(movec)
2020 {
2021 uint16_t ext;
2022 TCGv reg;
2023
2024 if (IS_USER(s)) {
2025 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2026 return;
2027 }
2028
2029 ext = read_im16(env, s);
2030
2031 if (ext & 0x8000) {
2032 reg = AREG(ext, 12);
2033 } else {
2034 reg = DREG(ext, 12);
2035 }
2036 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2037 gen_lookup_tb(s);
2038 }
2039
2040 DISAS_INSN(intouch)
2041 {
2042 if (IS_USER(s)) {
2043 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2044 return;
2045 }
2046 /* ICache fetch. Implement as no-op. */
2047 }
2048
2049 DISAS_INSN(cpushl)
2050 {
2051 if (IS_USER(s)) {
2052 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2053 return;
2054 }
2055 /* Cache push/invalidate. Implement as no-op. */
2056 }
2057
2058 DISAS_INSN(wddata)
2059 {
2060 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2061 }
2062
2063 DISAS_INSN(wdebug)
2064 {
2065 M68kCPU *cpu = m68k_env_get_cpu(env);
2066
2067 if (IS_USER(s)) {
2068 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2069 return;
2070 }
2071 /* TODO: Implement wdebug. */
2072 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2073 }
2074
2075 DISAS_INSN(trap)
2076 {
2077 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2078 }
2079
2080 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2081 immediately before the next FP instruction is executed. */
2082 DISAS_INSN(fpu)
2083 {
2084 uint16_t ext;
2085 int32_t offset;
2086 int opmode;
2087 TCGv_i64 src;
2088 TCGv_i64 dest;
2089 TCGv_i64 res;
2090 TCGv tmp32;
2091 int round;
2092 int set_dest;
2093 int opsize;
2094
2095 ext = read_im16(env, s);
2096 opmode = ext & 0x7f;
2097 switch ((ext >> 13) & 7) {
2098 case 0: case 2:
2099 break;
2100 case 1:
2101 goto undef;
2102 case 3: /* fmove out */
2103 src = FREG(ext, 7);
2104 tmp32 = tcg_temp_new_i32();
2105 /* fmove */
2106 /* ??? TODO: Proper behavior on overflow. */
2107 switch ((ext >> 10) & 7) {
2108 case 0:
2109 opsize = OS_LONG;
2110 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2111 break;
2112 case 1:
2113 opsize = OS_SINGLE;
2114 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2115 break;
2116 case 4:
2117 opsize = OS_WORD;
2118 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2119 break;
2120 case 5: /* OS_DOUBLE */
2121 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2122 switch ((insn >> 3) & 7) {
2123 case 2:
2124 case 3:
2125 break;
2126 case 4:
2127 tcg_gen_addi_i32(tmp32, tmp32, -8);
2128 break;
2129 case 5:
2130 offset = cpu_ldsw_code(env, s->pc);
2131 s->pc += 2;
2132 tcg_gen_addi_i32(tmp32, tmp32, offset);
2133 break;
2134 default:
2135 goto undef;
2136 }
2137 gen_store64(s, tmp32, src);
2138 switch ((insn >> 3) & 7) {
2139 case 3:
2140 tcg_gen_addi_i32(tmp32, tmp32, 8);
2141 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2142 break;
2143 case 4:
2144 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2145 break;
2146 }
2147 tcg_temp_free_i32(tmp32);
2148 return;
2149 case 6:
2150 opsize = OS_BYTE;
2151 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2152 break;
2153 default:
2154 goto undef;
2155 }
2156 DEST_EA(env, insn, opsize, tmp32, NULL);
2157 tcg_temp_free_i32(tmp32);
2158 return;
2159 case 4: /* fmove to control register. */
2160 switch ((ext >> 10) & 7) {
2161 case 4: /* FPCR */
2162 /* Not implemented. Ignore writes. */
2163 break;
2164 case 1: /* FPIAR */
2165 case 2: /* FPSR */
2166 default:
2167 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2168 (ext >> 10) & 7);
2169 }
2170 break;
2171 case 5: /* fmove from control register. */
2172 switch ((ext >> 10) & 7) {
2173 case 4: /* FPCR */
2174 /* Not implemented. Always return zero. */
2175 tmp32 = tcg_const_i32(0);
2176 break;
2177 case 1: /* FPIAR */
2178 case 2: /* FPSR */
2179 default:
2180 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2181 (ext >> 10) & 7);
2182 goto undef;
2183 }
2184 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2185 break;
2186 case 6: /* fmovem */
2187 case 7:
2188 {
2189 TCGv addr;
2190 uint16_t mask;
2191 int i;
2192 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2193 goto undef;
2194 tmp32 = gen_lea(env, s, insn, OS_LONG);
2195 if (IS_NULL_QREG(tmp32)) {
2196 gen_addr_fault(s);
2197 return;
2198 }
2199 addr = tcg_temp_new_i32();
2200 tcg_gen_mov_i32(addr, tmp32);
2201 mask = 0x80;
2202 for (i = 0; i < 8; i++) {
2203 if (ext & mask) {
2204 dest = FREG(i, 0);
2205 if (ext & (1 << 13)) {
2206 /* store */
2207 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2208 } else {
2209 /* load */
2210 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2211 }
2212 if (ext & (mask - 1))
2213 tcg_gen_addi_i32(addr, addr, 8);
2214 }
2215 mask >>= 1;
2216 }
2217 tcg_temp_free_i32(addr);
2218 }
2219 return;
2220 }
2221 if (ext & (1 << 14)) {
2222 /* Source effective address. */
2223 switch ((ext >> 10) & 7) {
2224 case 0: opsize = OS_LONG; break;
2225 case 1: opsize = OS_SINGLE; break;
2226 case 4: opsize = OS_WORD; break;
2227 case 5: opsize = OS_DOUBLE; break;
2228 case 6: opsize = OS_BYTE; break;
2229 default:
2230 goto undef;
2231 }
2232 if (opsize == OS_DOUBLE) {
2233 tmp32 = tcg_temp_new_i32();
2234 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2235 switch ((insn >> 3) & 7) {
2236 case 2:
2237 case 3:
2238 break;
2239 case 4:
2240 tcg_gen_addi_i32(tmp32, tmp32, -8);
2241 break;
2242 case 5:
2243 offset = cpu_ldsw_code(env, s->pc);
2244 s->pc += 2;
2245 tcg_gen_addi_i32(tmp32, tmp32, offset);
2246 break;
2247 case 7:
2248 offset = cpu_ldsw_code(env, s->pc);
2249 offset += s->pc - 2;
2250 s->pc += 2;
2251 tcg_gen_addi_i32(tmp32, tmp32, offset);
2252 break;
2253 default:
2254 goto undef;
2255 }
2256 src = gen_load64(s, tmp32);
2257 switch ((insn >> 3) & 7) {
2258 case 3:
2259 tcg_gen_addi_i32(tmp32, tmp32, 8);
2260 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2261 break;
2262 case 4:
2263 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2264 break;
2265 }
2266 tcg_temp_free_i32(tmp32);
2267 } else {
2268 SRC_EA(env, tmp32, opsize, 1, NULL);
2269 src = tcg_temp_new_i64();
2270 switch (opsize) {
2271 case OS_LONG:
2272 case OS_WORD:
2273 case OS_BYTE:
2274 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2275 break;
2276 case OS_SINGLE:
2277 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2278 break;
2279 }
2280 }
2281 } else {
2282 /* Source register. */
2283 src = FREG(ext, 10);
2284 }
2285 dest = FREG(ext, 7);
2286 res = tcg_temp_new_i64();
2287 if (opmode != 0x3a)
2288 tcg_gen_mov_f64(res, dest);
2289 round = 1;
2290 set_dest = 1;
2291 switch (opmode) {
2292 case 0: case 0x40: case 0x44: /* fmove */
2293 tcg_gen_mov_f64(res, src);
2294 break;
2295 case 1: /* fint */
2296 gen_helper_iround_f64(res, cpu_env, src);
2297 round = 0;
2298 break;
2299 case 3: /* fintrz */
2300 gen_helper_itrunc_f64(res, cpu_env, src);
2301 round = 0;
2302 break;
2303 case 4: case 0x41: case 0x45: /* fsqrt */
2304 gen_helper_sqrt_f64(res, cpu_env, src);
2305 break;
2306 case 0x18: case 0x58: case 0x5c: /* fabs */
2307 gen_helper_abs_f64(res, src);
2308 break;
2309 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2310 gen_helper_chs_f64(res, src);
2311 break;
2312 case 0x20: case 0x60: case 0x64: /* fdiv */
2313 gen_helper_div_f64(res, cpu_env, res, src);
2314 break;
2315 case 0x22: case 0x62: case 0x66: /* fadd */
2316 gen_helper_add_f64(res, cpu_env, res, src);
2317 break;
2318 case 0x23: case 0x63: case 0x67: /* fmul */
2319 gen_helper_mul_f64(res, cpu_env, res, src);
2320 break;
2321 case 0x28: case 0x68: case 0x6c: /* fsub */
2322 gen_helper_sub_f64(res, cpu_env, res, src);
2323 break;
2324 case 0x38: /* fcmp */
2325 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2326 set_dest = 0;
2327 round = 0;
2328 break;
2329 case 0x3a: /* ftst */
2330 tcg_gen_mov_f64(res, src);
2331 set_dest = 0;
2332 round = 0;
2333 break;
2334 default:
2335 goto undef;
2336 }
2337 if (ext & (1 << 14)) {
2338 tcg_temp_free_i64(src);
2339 }
2340 if (round) {
2341 if (opmode & 0x40) {
2342 if ((opmode & 0x4) != 0)
2343 round = 0;
2344 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2345 round = 0;
2346 }
2347 }
2348 if (round) {
2349 TCGv tmp = tcg_temp_new_i32();
2350 gen_helper_f64_to_f32(tmp, cpu_env, res);
2351 gen_helper_f32_to_f64(res, cpu_env, tmp);
2352 tcg_temp_free_i32(tmp);
2353 }
2354 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2355 if (set_dest) {
2356 tcg_gen_mov_f64(dest, res);
2357 }
2358 tcg_temp_free_i64(res);
2359 return;
2360 undef:
2361 /* FIXME: Is this right for offset addressing modes? */
2362 s->pc -= 2;
2363 disas_undef_fpu(env, s, insn);
2364 }
2365
2366 DISAS_INSN(fbcc)
2367 {
2368 uint32_t offset;
2369 uint32_t addr;
2370 TCGv flag;
2371 TCGLabel *l1;
2372
2373 addr = s->pc;
2374 offset = cpu_ldsw_code(env, s->pc);
2375 s->pc += 2;
2376 if (insn & (1 << 6)) {
2377 offset = (offset << 16) | read_im16(env, s);
2378 }
2379
2380 l1 = gen_new_label();
2381 /* TODO: Raise BSUN exception. */
2382 flag = tcg_temp_new();
2383 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2384 /* Jump to l1 if condition is true. */
2385 switch (insn & 0xf) {
2386 case 0: /* f */
2387 break;
2388 case 1: /* eq (=0) */
2389 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2390 break;
2391 case 2: /* ogt (=1) */
2392 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2393 break;
2394 case 3: /* oge (=0 or =1) */
2395 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2396 break;
2397 case 4: /* olt (=-1) */
2398 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2399 break;
2400 case 5: /* ole (=-1 or =0) */
2401 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2402 break;
2403 case 6: /* ogl (=-1 or =1) */
2404 tcg_gen_andi_i32(flag, flag, 1);
2405 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2406 break;
2407 case 7: /* or (=2) */
2408 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2409 break;
2410 case 8: /* un (<2) */
2411 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2412 break;
2413 case 9: /* ueq (=0 or =2) */
2414 tcg_gen_andi_i32(flag, flag, 1);
2415 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2416 break;
2417 case 10: /* ugt (>0) */
2418 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2419 break;
2420 case 11: /* uge (>=0) */
2421 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2422 break;
2423 case 12: /* ult (=-1 or =2) */
2424 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2425 break;
2426 case 13: /* ule (!=1) */
2427 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2428 break;
2429 case 14: /* ne (!=0) */
2430 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2431 break;
2432 case 15: /* t */
2433 tcg_gen_br(l1);
2434 break;
2435 }
2436 gen_jmp_tb(s, 0, s->pc);
2437 gen_set_label(l1);
2438 gen_jmp_tb(s, 1, addr + offset);
2439 }
2440
2441 DISAS_INSN(frestore)
2442 {
2443 M68kCPU *cpu = m68k_env_get_cpu(env);
2444
2445 /* TODO: Implement frestore. */
2446 cpu_abort(CPU(cpu), "FRESTORE not implemented");
2447 }
2448
2449 DISAS_INSN(fsave)
2450 {
2451 M68kCPU *cpu = m68k_env_get_cpu(env);
2452
2453 /* TODO: Implement fsave. */
2454 cpu_abort(CPU(cpu), "FSAVE not implemented");
2455 }
2456
2457 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2458 {
2459 TCGv tmp = tcg_temp_new();
2460 if (s->env->macsr & MACSR_FI) {
2461 if (upper)
2462 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2463 else
2464 tcg_gen_shli_i32(tmp, val, 16);
2465 } else if (s->env->macsr & MACSR_SU) {
2466 if (upper)
2467 tcg_gen_sari_i32(tmp, val, 16);
2468 else
2469 tcg_gen_ext16s_i32(tmp, val);
2470 } else {
2471 if (upper)
2472 tcg_gen_shri_i32(tmp, val, 16);
2473 else
2474 tcg_gen_ext16u_i32(tmp, val);
2475 }
2476 return tmp;
2477 }
2478
2479 static void gen_mac_clear_flags(void)
2480 {
2481 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2482 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2483 }
2484
2485 DISAS_INSN(mac)
2486 {
2487 TCGv rx;
2488 TCGv ry;
2489 uint16_t ext;
2490 int acc;
2491 TCGv tmp;
2492 TCGv addr;
2493 TCGv loadval;
2494 int dual;
2495 TCGv saved_flags;
2496
2497 if (!s->done_mac) {
2498 s->mactmp = tcg_temp_new_i64();
2499 s->done_mac = 1;
2500 }
2501
2502 ext = read_im16(env, s);
2503
2504 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2505 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2506 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2507 disas_undef(env, s, insn);
2508 return;
2509 }
2510 if (insn & 0x30) {
2511 /* MAC with load. */
2512 tmp = gen_lea(env, s, insn, OS_LONG);
2513 addr = tcg_temp_new();
2514 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2515 /* Load the value now to ensure correct exception behavior.
2516 Perform writeback after reading the MAC inputs. */
2517 loadval = gen_load(s, OS_LONG, addr, 0);
2518
2519 acc ^= 1;
2520 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2521 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2522 } else {
2523 loadval = addr = NULL_QREG;
2524 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2525 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2526 }
2527
2528 gen_mac_clear_flags();
2529 #if 0
2530 l1 = -1;
2531 /* Disabled because conditional branches clobber temporary vars. */
2532 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2533 /* Skip the multiply if we know we will ignore it. */
2534 l1 = gen_new_label();
2535 tmp = tcg_temp_new();
2536 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2537 gen_op_jmp_nz32(tmp, l1);
2538 }
2539 #endif
2540
2541 if ((ext & 0x0800) == 0) {
2542 /* Word. */
2543 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2544 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2545 }
2546 if (s->env->macsr & MACSR_FI) {
2547 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2548 } else {
2549 if (s->env->macsr & MACSR_SU)
2550 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2551 else
2552 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2553 switch ((ext >> 9) & 3) {
2554 case 1:
2555 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2556 break;
2557 case 3:
2558 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2559 break;
2560 }
2561 }
2562
2563 if (dual) {
2564 /* Save the overflow flag from the multiply. */
2565 saved_flags = tcg_temp_new();
2566 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2567 } else {
2568 saved_flags = NULL_QREG;
2569 }
2570
2571 #if 0
2572 /* Disabled because conditional branches clobber temporary vars. */
2573 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2574 /* Skip the accumulate if the value is already saturated. */
2575 l1 = gen_new_label();
2576 tmp = tcg_temp_new();
2577 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2578 gen_op_jmp_nz32(tmp, l1);
2579 }
2580 #endif
2581
2582 if (insn & 0x100)
2583 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2584 else
2585 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2586
2587 if (s->env->macsr & MACSR_FI)
2588 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2589 else if (s->env->macsr & MACSR_SU)
2590 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2591 else
2592 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2593
2594 #if 0
2595 /* Disabled because conditional branches clobber temporary vars. */
2596 if (l1 != -1)
2597 gen_set_label(l1);
2598 #endif
2599
2600 if (dual) {
2601 /* Dual accumulate variant. */
2602 acc = (ext >> 2) & 3;
2603 /* Restore the overflow flag from the multiplier. */
2604 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2605 #if 0
2606 /* Disabled because conditional branches clobber temporary vars. */
2607 if ((s->env->macsr & MACSR_OMC) != 0) {
2608 /* Skip the accumulate if the value is already saturated. */
2609 l1 = gen_new_label();
2610 tmp = tcg_temp_new();
2611 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2612 gen_op_jmp_nz32(tmp, l1);
2613 }
2614 #endif
2615 if (ext & 2)
2616 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2617 else
2618 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2619 if (s->env->macsr & MACSR_FI)
2620 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2621 else if (s->env->macsr & MACSR_SU)
2622 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2623 else
2624 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2625 #if 0
2626 /* Disabled because conditional branches clobber temporary vars. */
2627 if (l1 != -1)
2628 gen_set_label(l1);
2629 #endif
2630 }
2631 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2632
2633 if (insn & 0x30) {
2634 TCGv rw;
2635 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2636 tcg_gen_mov_i32(rw, loadval);
2637 /* FIXME: Should address writeback happen with the masked or
2638 unmasked value? */
2639 switch ((insn >> 3) & 7) {
2640 case 3: /* Post-increment. */
2641 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2642 break;
2643 case 4: /* Pre-decrement. */
2644 tcg_gen_mov_i32(AREG(insn, 0), addr);
2645 }
2646 }
2647 }
2648
2649 DISAS_INSN(from_mac)
2650 {
2651 TCGv rx;
2652 TCGv_i64 acc;
2653 int accnum;
2654
2655 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2656 accnum = (insn >> 9) & 3;
2657 acc = MACREG(accnum);
2658 if (s->env->macsr & MACSR_FI) {
2659 gen_helper_get_macf(rx, cpu_env, acc);
2660 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2661 tcg_gen_extrl_i64_i32(rx, acc);
2662 } else if (s->env->macsr & MACSR_SU) {
2663 gen_helper_get_macs(rx, acc);
2664 } else {
2665 gen_helper_get_macu(rx, acc);
2666 }
2667 if (insn & 0x40) {
2668 tcg_gen_movi_i64(acc, 0);
2669 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2670 }
2671 }
2672
2673 DISAS_INSN(move_mac)
2674 {
2675 /* FIXME: This can be done without a helper. */
2676 int src;
2677 TCGv dest;
2678 src = insn & 3;
2679 dest = tcg_const_i32((insn >> 9) & 3);
2680 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2681 gen_mac_clear_flags();
2682 gen_helper_mac_set_flags(cpu_env, dest);
2683 }
2684
2685 DISAS_INSN(from_macsr)
2686 {
2687 TCGv reg;
2688
2689 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2690 tcg_gen_mov_i32(reg, QREG_MACSR);
2691 }
2692
2693 DISAS_INSN(from_mask)
2694 {
2695 TCGv reg;
2696 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2697 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2698 }
2699
2700 DISAS_INSN(from_mext)
2701 {
2702 TCGv reg;
2703 TCGv acc;
2704 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2705 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2706 if (s->env->macsr & MACSR_FI)
2707 gen_helper_get_mac_extf(reg, cpu_env, acc);
2708 else
2709 gen_helper_get_mac_exti(reg, cpu_env, acc);
2710 }
2711
2712 DISAS_INSN(macsr_to_ccr)
2713 {
2714 TCGv tmp = tcg_temp_new();
2715 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
2716 gen_helper_set_sr(cpu_env, tmp);
2717 tcg_temp_free(tmp);
2718 set_cc_op(s, CC_OP_FLAGS);
2719 }
2720
2721 DISAS_INSN(to_mac)
2722 {
2723 TCGv_i64 acc;
2724 TCGv val;
2725 int accnum;
2726 accnum = (insn >> 9) & 3;
2727 acc = MACREG(accnum);
2728 SRC_EA(env, val, OS_LONG, 0, NULL);
2729 if (s->env->macsr & MACSR_FI) {
2730 tcg_gen_ext_i32_i64(acc, val);
2731 tcg_gen_shli_i64(acc, acc, 8);
2732 } else if (s->env->macsr & MACSR_SU) {
2733 tcg_gen_ext_i32_i64(acc, val);
2734 } else {
2735 tcg_gen_extu_i32_i64(acc, val);
2736 }
2737 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2738 gen_mac_clear_flags();
2739 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2740 }
2741
2742 DISAS_INSN(to_macsr)
2743 {
2744 TCGv val;
2745 SRC_EA(env, val, OS_LONG, 0, NULL);
2746 gen_helper_set_macsr(cpu_env, val);
2747 gen_lookup_tb(s);
2748 }
2749
2750 DISAS_INSN(to_mask)
2751 {
2752 TCGv val;
2753 SRC_EA(env, val, OS_LONG, 0, NULL);
2754 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2755 }
2756
2757 DISAS_INSN(to_mext)
2758 {
2759 TCGv val;
2760 TCGv acc;
2761 SRC_EA(env, val, OS_LONG, 0, NULL);
2762 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2763 if (s->env->macsr & MACSR_FI)
2764 gen_helper_set_mac_extf(cpu_env, val, acc);
2765 else if (s->env->macsr & MACSR_SU)
2766 gen_helper_set_mac_exts(cpu_env, val, acc);
2767 else
2768 gen_helper_set_mac_extu(cpu_env, val, acc);
2769 }
2770
2771 static disas_proc opcode_table[65536];
2772
2773 static void
2774 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2775 {
2776 int i;
2777 int from;
2778 int to;
2779
2780 /* Sanity check. All set bits must be included in the mask. */
2781 if (opcode & ~mask) {
2782 fprintf(stderr,
2783 "qemu internal error: bogus opcode definition %04x/%04x\n",
2784 opcode, mask);
2785 abort();
2786 }
2787 /* This could probably be cleverer. For now just optimize the case where
2788 the top bits are known. */
2789 /* Find the first zero bit in the mask. */
2790 i = 0x8000;
2791 while ((i & mask) != 0)
2792 i >>= 1;
2793 /* Iterate over all combinations of this and lower bits. */
2794 if (i == 0)
2795 i = 1;
2796 else
2797 i <<= 1;
2798 from = opcode & ~(i - 1);
2799 to = from + i;
2800 for (i = from; i < to; i++) {
2801 if ((i & mask) == opcode)
2802 opcode_table[i] = proc;
2803 }
2804 }
2805
2806 /* Register m68k opcode handlers. Order is important.
2807 Later insn override earlier ones. */
2808 void register_m68k_insns (CPUM68KState *env)
2809 {
2810 /* Build the opcode table only once to avoid
2811 multithreading issues. */
2812 if (opcode_table[0] != NULL) {
2813 return;
2814 }
2815
2816 /* use BASE() for instruction available
2817 * for CF_ISA_A and M68000.
2818 */
2819 #define BASE(name, opcode, mask) \
2820 register_opcode(disas_##name, 0x##opcode, 0x##mask)
2821 #define INSN(name, opcode, mask, feature) do { \
2822 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2823 BASE(name, opcode, mask); \
2824 } while(0)
2825 BASE(undef, 0000, 0000);
2826 INSN(arith_im, 0080, fff8, CF_ISA_A);
2827 INSN(arith_im, 0000, ff00, M68000);
2828 INSN(undef, 00c0, ffc0, M68000);
2829 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2830 BASE(bitop_reg, 0100, f1c0);
2831 BASE(bitop_reg, 0140, f1c0);
2832 BASE(bitop_reg, 0180, f1c0);
2833 BASE(bitop_reg, 01c0, f1c0);
2834 INSN(arith_im, 0280, fff8, CF_ISA_A);
2835 INSN(arith_im, 0200, ff00, M68000);
2836 INSN(undef, 02c0, ffc0, M68000);
2837 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2838 INSN(arith_im, 0480, fff8, CF_ISA_A);
2839 INSN(arith_im, 0400, ff00, M68000);
2840 INSN(undef, 04c0, ffc0, M68000);
2841 INSN(arith_im, 0600, ff00, M68000);
2842 INSN(undef, 06c0, ffc0, M68000);
2843 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2844 INSN(arith_im, 0680, fff8, CF_ISA_A);
2845 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2846 INSN(arith_im, 0c00, ff00, M68000);
2847 BASE(bitop_im, 0800, ffc0);
2848 BASE(bitop_im, 0840, ffc0);
2849 BASE(bitop_im, 0880, ffc0);
2850 BASE(bitop_im, 08c0, ffc0);
2851 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2852 INSN(arith_im, 0a00, ff00, M68000);
2853 BASE(move, 1000, f000);
2854 BASE(move, 2000, f000);
2855 BASE(move, 3000, f000);
2856 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2857 INSN(negx, 4080, fff8, CF_ISA_A);
2858 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2859 INSN(move_from_sr, 40c0, ffc0, M68000);
2860 BASE(lea, 41c0, f1c0);
2861 BASE(clr, 4200, ff00);
2862 BASE(undef, 42c0, ffc0);
2863 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2864 INSN(move_from_ccr, 42c0, ffc0, M68000);
2865 INSN(neg, 4480, fff8, CF_ISA_A);
2866 INSN(neg, 4400, ff00, M68000);
2867 INSN(undef, 44c0, ffc0, M68000);
2868 BASE(move_to_ccr, 44c0, ffc0);
2869 INSN(not, 4680, fff8, CF_ISA_A);
2870 INSN(not, 4600, ff00, M68000);
2871 INSN(undef, 46c0, ffc0, M68000);
2872 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2873 BASE(pea, 4840, ffc0);
2874 BASE(swap, 4840, fff8);
2875 BASE(movem, 48c0, fbc0);
2876 BASE(ext, 4880, fff8);
2877 BASE(ext, 48c0, fff8);
2878 BASE(ext, 49c0, fff8);
2879 BASE(tst, 4a00, ff00);
2880 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2881 INSN(tas, 4ac0, ffc0, M68000);
2882 INSN(halt, 4ac8, ffff, CF_ISA_A);
2883 INSN(pulse, 4acc, ffff, CF_ISA_A);
2884 BASE(illegal, 4afc, ffff);
2885 INSN(mull, 4c00, ffc0, CF_ISA_A);
2886 INSN(mull, 4c00, ffc0, LONG_MULDIV);
2887 INSN(divl, 4c40, ffc0, CF_ISA_A);
2888 INSN(divl, 4c40, ffc0, LONG_MULDIV);
2889 INSN(sats, 4c80, fff8, CF_ISA_B);
2890 BASE(trap, 4e40, fff0);
2891 BASE(link, 4e50, fff8);
2892 BASE(unlk, 4e58, fff8);
2893 INSN(move_to_usp, 4e60, fff8, USP);
2894 INSN(move_from_usp, 4e68, fff8, USP);
2895 BASE(nop, 4e71, ffff);
2896 BASE(stop, 4e72, ffff);
2897 BASE(rte, 4e73, ffff);
2898 BASE(rts, 4e75, ffff);
2899 INSN(movec, 4e7b, ffff, CF_ISA_A);
2900 BASE(jump, 4e80, ffc0);
2901 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2902 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2903 INSN(jump, 4ec0, ffc0, M68000);
2904 INSN(addsubq, 5000, f080, M68000);
2905 INSN(addsubq, 5080, f0c0, M68000);
2906 INSN(scc, 50c0, f0f8, CF_ISA_A);
2907 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2908 INSN(tpf, 51f8, fff8, CF_ISA_A);
2909
2910 /* Branch instructions. */
2911 BASE(branch, 6000, f000);
2912 /* Disable long branch instructions, then add back the ones we want. */
2913 BASE(undef, 60ff, f0ff); /* All long branches. */
2914 INSN(branch, 60ff, f0ff, CF_ISA_B);
2915 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2916 INSN(branch, 60ff, ffff, BRAL);
2917 INSN(branch, 60ff, f0ff, BCCL);
2918
2919 BASE(moveq, 7000, f100);
2920 INSN(mvzs, 7100, f100, CF_ISA_B);
2921 BASE(or, 8000, f000);
2922 BASE(divw, 80c0, f0c0);
2923 BASE(addsub, 9000, f000);
2924 INSN(subx, 9180, f1f8, CF_ISA_A);
2925 INSN(suba, 91c0, f1c0, CF_ISA_A);
2926
2927 BASE(undef_mac, a000, f000);
2928 INSN(mac, a000, f100, CF_EMAC);
2929 INSN(from_mac, a180, f9b0, CF_EMAC);
2930 INSN(move_mac, a110, f9fc, CF_EMAC);
2931 INSN(from_macsr,a980, f9f0, CF_EMAC);
2932 INSN(from_mask, ad80, fff0, CF_EMAC);
2933 INSN(from_mext, ab80, fbf0, CF_EMAC);
2934 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2935 INSN(to_mac, a100, f9c0, CF_EMAC);
2936 INSN(to_macsr, a900, ffc0, CF_EMAC);
2937 INSN(to_mext, ab00, fbc0, CF_EMAC);
2938 INSN(to_mask, ad00, ffc0, CF_EMAC);
2939
2940 INSN(mov3q, a140, f1c0, CF_ISA_B);
2941 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2942 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2943 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2944 INSN(cmp, b080, f1c0, CF_ISA_A);
2945 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2946 INSN(cmp, b000, f100, M68000);
2947 INSN(eor, b100, f100, M68000);
2948 INSN(cmpa, b0c0, f0c0, M68000);
2949 INSN(eor, b180, f1c0, CF_ISA_A);
2950 BASE(and, c000, f000);
2951 BASE(mulw, c0c0, f0c0);
2952 BASE(addsub, d000, f000);
2953 INSN(addx, d180, f1f8, CF_ISA_A);
2954 INSN(adda, d1c0, f1c0, CF_ISA_A);
2955 INSN(adda, d0c0, f0c0, M68000);
2956 INSN(shift_im, e080, f0f0, CF_ISA_A);
2957 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2958 INSN(undef_fpu, f000, f000, CF_ISA_A);
2959 INSN(fpu, f200, ffc0, CF_FPU);
2960 INSN(fbcc, f280, ffc0, CF_FPU);
2961 INSN(frestore, f340, ffc0, CF_FPU);
2962 INSN(fsave, f340, ffc0, CF_FPU);
2963 INSN(intouch, f340, ffc0, CF_ISA_A);
2964 INSN(cpushl, f428, ff38, CF_ISA_A);
2965 INSN(wddata, fb00, ff00, CF_ISA_A);
2966 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2967 #undef INSN
2968 }
2969
2970 /* ??? Some of this implementation is not exception safe. We should always
2971 write back the result to memory before setting the condition codes. */
2972 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
2973 {
2974 uint16_t insn;
2975
2976 insn = read_im16(env, s);
2977
2978 opcode_table[insn](env, s, insn);
2979 }
2980
2981 /* generate intermediate code for basic block 'tb'. */
2982 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
2983 {
2984 M68kCPU *cpu = m68k_env_get_cpu(env);
2985 CPUState *cs = CPU(cpu);
2986 DisasContext dc1, *dc = &dc1;
2987 target_ulong pc_start;
2988 int pc_offset;
2989 int num_insns;
2990 int max_insns;
2991
2992 /* generate intermediate code */
2993 pc_start = tb->pc;
2994
2995 dc->tb = tb;
2996
2997 dc->env = env;
2998 dc->is_jmp = DISAS_NEXT;
2999 dc->pc = pc_start;
3000 dc->cc_op = CC_OP_DYNAMIC;
3001 dc->cc_op_synced = 1;
3002 dc->singlestep_enabled = cs->singlestep_enabled;
3003 dc->fpcr = env->fpcr;
3004 dc->user = (env->sr & SR_S) == 0;
3005 dc->done_mac = 0;
3006 num_insns = 0;
3007 max_insns = tb->cflags & CF_COUNT_MASK;
3008 if (max_insns == 0) {
3009 max_insns = CF_COUNT_MASK;
3010 }
3011 if (max_insns > TCG_MAX_INSNS) {
3012 max_insns = TCG_MAX_INSNS;
3013 }
3014
3015 gen_tb_start(tb);
3016 do {
3017 pc_offset = dc->pc - pc_start;
3018 gen_throws_exception = NULL;
3019 tcg_gen_insn_start(dc->pc, dc->cc_op);
3020 num_insns++;
3021
3022 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3023 gen_exception(dc, dc->pc, EXCP_DEBUG);
3024 dc->is_jmp = DISAS_JUMP;
3025 /* The address covered by the breakpoint must be included in
3026 [tb->pc, tb->pc + tb->size) in order to for it to be
3027 properly cleared -- thus we increment the PC here so that
3028 the logic setting tb->size below does the right thing. */
3029 dc->pc += 2;
3030 break;
3031 }
3032
3033 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3034 gen_io_start();
3035 }
3036
3037 dc->insn_pc = dc->pc;
3038 disas_m68k_insn(env, dc);
3039 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3040 !cs->singlestep_enabled &&
3041 !singlestep &&
3042 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3043 num_insns < max_insns);
3044
3045 if (tb->cflags & CF_LAST_IO)
3046 gen_io_end();
3047 if (unlikely(cs->singlestep_enabled)) {
3048 /* Make sure the pc is updated, and raise a debug exception. */
3049 if (!dc->is_jmp) {
3050 update_cc_op(dc);
3051 tcg_gen_movi_i32(QREG_PC, dc->pc);
3052 }
3053 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3054 } else {
3055 switch(dc->is_jmp) {
3056 case DISAS_NEXT:
3057 update_cc_op(dc);
3058 gen_jmp_tb(dc, 0, dc->pc);
3059 break;
3060 default:
3061 case DISAS_JUMP:
3062 case DISAS_UPDATE:
3063 update_cc_op(dc);
3064 /* indicate that the hash table must be used to find the next TB */
3065 tcg_gen_exit_tb(0);
3066 break;
3067 case DISAS_TB_JUMP:
3068 /* nothing more to generate */
3069 break;
3070 }
3071 }
3072 gen_tb_end(tb, num_insns);
3073
3074 #ifdef DEBUG_DISAS
3075 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3076 && qemu_log_in_addr_range(pc_start)) {
3077 qemu_log("----------------\n");
3078 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3079 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3080 qemu_log("\n");
3081 }
3082 #endif
3083 tb->size = dc->pc - pc_start;
3084 tb->icount = num_insns;
3085 }
3086
3087 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3088 int flags)
3089 {
3090 M68kCPU *cpu = M68K_CPU(cs);
3091 CPUM68KState *env = &cpu->env;
3092 int i;
3093 uint16_t sr;
3094 CPU_DoubleU u;
3095 for (i = 0; i < 8; i++)
3096 {
3097 u.d = env->fregs[i];
3098 cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3099 i, env->dregs[i], i, env->aregs[i],
3100 i, u.l.upper, u.l.lower, *(double *)&u.d);
3101 }
3102 cpu_fprintf (f, "PC = %08x ", env->pc);
3103 sr = env->sr | cpu_m68k_get_ccr(env);
3104 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
3105 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3106 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3107 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3108 }
3109
3110 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3111 target_ulong *data)
3112 {
3113 int cc_op = data[1];
3114 env->pc = data[0];
3115 if (cc_op != CC_OP_DYNAMIC) {
3116 env->cc_op = cc_op;
3117 }
3118 }
AR7 emulation for QEMU