target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers
[qemu/ar7.git] / hw / arm / boot.c
blobe56c42ac22cf57d0ffe8166f42f1e55c0cf2b1a2
1 /*
2 * ARM kernel loader.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 #include "qemu/osdep.h"
11 #include "qemu-common.h"
12 #include "qemu/datadir.h"
13 #include "qemu/error-report.h"
14 #include "qapi/error.h"
15 #include <libfdt.h>
16 #include "hw/arm/boot.h"
17 #include "hw/arm/linux-boot-if.h"
18 #include "sysemu/kvm.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/numa.h"
21 #include "hw/boards.h"
22 #include "sysemu/reset.h"
23 #include "hw/loader.h"
24 #include "elf.h"
25 #include "sysemu/device_tree.h"
26 #include "qemu/config-file.h"
27 #include "qemu/option.h"
28 #include "exec/address-spaces.h"
29 #include "qemu/units.h"
31 /* Kernel boot protocol is specified in the kernel docs
32 * Documentation/arm/Booting and Documentation/arm64/booting.txt
33 * They have different preferred image load offsets from system RAM base.
35 #define KERNEL_ARGS_ADDR 0x100
36 #define KERNEL_NOLOAD_ADDR 0x02000000
37 #define KERNEL_LOAD_ADDR 0x00010000
38 #define KERNEL64_LOAD_ADDR 0x00080000
40 #define ARM64_TEXT_OFFSET_OFFSET 8
41 #define ARM64_MAGIC_OFFSET 56
43 #define BOOTLOADER_MAX_SIZE (4 * KiB)
45 AddressSpace *arm_boot_address_space(ARMCPU *cpu,
46 const struct arm_boot_info *info)
48 /* Return the address space to use for bootloader reads and writes.
49 * We prefer the secure address space if the CPU has it and we're
50 * going to boot the guest into it.
52 int asidx;
53 CPUState *cs = CPU(cpu);
55 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {
56 asidx = ARMASIdx_S;
57 } else {
58 asidx = ARMASIdx_NS;
61 return cpu_get_address_space(cs, asidx);
64 typedef enum {
65 FIXUP_NONE = 0, /* do nothing */
66 FIXUP_TERMINATOR, /* end of insns */
67 FIXUP_BOARDID, /* overwrite with board ID number */
68 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
69 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
70 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
71 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
72 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
73 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
74 FIXUP_BOOTREG, /* overwrite with boot register address */
75 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
76 FIXUP_MAX,
77 } FixupType;
79 typedef struct ARMInsnFixup {
80 uint32_t insn;
81 FixupType fixup;
82 } ARMInsnFixup;
84 static const ARMInsnFixup bootloader_aarch64[] = {
85 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
86 { 0xaa1f03e1 }, /* mov x1, xzr */
87 { 0xaa1f03e2 }, /* mov x2, xzr */
88 { 0xaa1f03e3 }, /* mov x3, xzr */
89 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
90 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
91 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
92 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
93 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */
94 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */
95 { 0, FIXUP_TERMINATOR }
98 /* A very small bootloader: call the board-setup code (if needed),
99 * set r0-r2, then jump to the kernel.
100 * If we're not calling boot setup code then we don't copy across
101 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array.
104 static const ARMInsnFixup bootloader[] = {
105 { 0xe28fe004 }, /* add lr, pc, #4 */
106 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */
107 { 0, FIXUP_BOARD_SETUP },
108 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
109 { 0xe3a00000 }, /* mov r0, #0 */
110 { 0xe59f1004 }, /* ldr r1, [pc, #4] */
111 { 0xe59f2004 }, /* ldr r2, [pc, #4] */
112 { 0xe59ff004 }, /* ldr pc, [pc, #4] */
113 { 0, FIXUP_BOARDID },
114 { 0, FIXUP_ARGPTR_LO },
115 { 0, FIXUP_ENTRYPOINT_LO },
116 { 0, FIXUP_TERMINATOR }
119 /* Handling for secondary CPU boot in a multicore system.
120 * Unlike the uniprocessor/primary CPU boot, this is platform
121 * dependent. The default code here is based on the secondary
122 * CPU boot protocol used on realview/vexpress boards, with
123 * some parameterisation to increase its flexibility.
124 * QEMU platform models for which this code is not appropriate
125 * should override write_secondary_boot and secondary_cpu_reset_hook
126 * instead.
128 * This code enables the interrupt controllers for the secondary
129 * CPUs and then puts all the secondary CPUs into a loop waiting
130 * for an interprocessor interrupt and polling a configurable
131 * location for the kernel secondary CPU entry point.
133 #define DSB_INSN 0xf57ff04f
134 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
136 static const ARMInsnFixup smpboot[] = {
137 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
138 { 0xe59f0028 }, /* ldr r0, bootreg_addr */
139 { 0xe3a01001 }, /* mov r1, #1 */
140 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
141 { 0xe3a010ff }, /* mov r1, #0xff */
142 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
143 { 0, FIXUP_DSB }, /* dsb */
144 { 0xe320f003 }, /* wfi */
145 { 0xe5901000 }, /* ldr r1, [r0] */
146 { 0xe1110001 }, /* tst r1, r1 */
147 { 0x0afffffb }, /* beq <wfi> */
148 { 0xe12fff11 }, /* bx r1 */
149 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */
150 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */
151 { 0, FIXUP_TERMINATOR }
154 static void write_bootloader(const char *name, hwaddr addr,
155 const ARMInsnFixup *insns, uint32_t *fixupcontext,
156 AddressSpace *as)
158 /* Fix up the specified bootloader fragment and write it into
159 * guest memory using rom_add_blob_fixed(). fixupcontext is
160 * an array giving the values to write in for the fixup types
161 * which write a value into the code array.
163 int i, len;
164 uint32_t *code;
166 len = 0;
167 while (insns[len].fixup != FIXUP_TERMINATOR) {
168 len++;
171 code = g_new0(uint32_t, len);
173 for (i = 0; i < len; i++) {
174 uint32_t insn = insns[i].insn;
175 FixupType fixup = insns[i].fixup;
177 switch (fixup) {
178 case FIXUP_NONE:
179 break;
180 case FIXUP_BOARDID:
181 case FIXUP_BOARD_SETUP:
182 case FIXUP_ARGPTR_LO:
183 case FIXUP_ARGPTR_HI:
184 case FIXUP_ENTRYPOINT_LO:
185 case FIXUP_ENTRYPOINT_HI:
186 case FIXUP_GIC_CPU_IF:
187 case FIXUP_BOOTREG:
188 case FIXUP_DSB:
189 insn = fixupcontext[fixup];
190 break;
191 default:
192 abort();
194 code[i] = tswap32(insn);
197 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
199 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
201 g_free(code);
204 static void default_write_secondary(ARMCPU *cpu,
205 const struct arm_boot_info *info)
207 uint32_t fixupcontext[FIXUP_MAX];
208 AddressSpace *as = arm_boot_address_space(cpu, info);
210 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
211 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
212 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
213 fixupcontext[FIXUP_DSB] = DSB_INSN;
214 } else {
215 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
218 write_bootloader("smpboot", info->smp_loader_start,
219 smpboot, fixupcontext, as);
222 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
223 const struct arm_boot_info *info,
224 hwaddr mvbar_addr)
226 AddressSpace *as = arm_boot_address_space(cpu, info);
227 int n;
228 uint32_t mvbar_blob[] = {
229 /* mvbar_addr: secure monitor vectors
230 * Default unimplemented and unused vectors to spin. Makes it
231 * easier to debug (as opposed to the CPU running away).
233 0xeafffffe, /* (spin) */
234 0xeafffffe, /* (spin) */
235 0xe1b0f00e, /* movs pc, lr ;SMC exception return */
236 0xeafffffe, /* (spin) */
237 0xeafffffe, /* (spin) */
238 0xeafffffe, /* (spin) */
239 0xeafffffe, /* (spin) */
240 0xeafffffe, /* (spin) */
242 uint32_t board_setup_blob[] = {
243 /* board setup addr */
244 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */
245 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */
246 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */
247 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */
248 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
249 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
250 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */
251 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */
252 0xe1a0100e, /* mov r1, lr ;save LR across SMC */
253 0xe1600070, /* smc #0 ;call monitor to flush SCR */
254 0xe1a0f001, /* mov pc, r1 ;return */
257 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */
258 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
260 /* check that these blobs don't overlap */
261 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
262 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
264 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
265 mvbar_blob[n] = tswap32(mvbar_blob[n]);
267 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
268 mvbar_addr, as);
270 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
271 board_setup_blob[n] = tswap32(board_setup_blob[n]);
273 rom_add_blob_fixed_as("board-setup", board_setup_blob,
274 sizeof(board_setup_blob), info->board_setup_addr, as);
277 static void default_reset_secondary(ARMCPU *cpu,
278 const struct arm_boot_info *info)
280 AddressSpace *as = arm_boot_address_space(cpu, info);
281 CPUState *cs = CPU(cpu);
283 address_space_stl_notdirty(as, info->smp_bootreg_addr,
284 0, MEMTXATTRS_UNSPECIFIED, NULL);
285 cpu_set_pc(cs, info->smp_loader_start);
288 static inline bool have_dtb(const struct arm_boot_info *info)
290 return info->dtb_filename || info->get_dtb;
293 #define WRITE_WORD(p, value) do { \
294 address_space_stl_notdirty(as, p, value, \
295 MEMTXATTRS_UNSPECIFIED, NULL); \
296 p += 4; \
297 } while (0)
299 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
301 int initrd_size = info->initrd_size;
302 hwaddr base = info->loader_start;
303 hwaddr p;
305 p = base + KERNEL_ARGS_ADDR;
306 /* ATAG_CORE */
307 WRITE_WORD(p, 5);
308 WRITE_WORD(p, 0x54410001);
309 WRITE_WORD(p, 1);
310 WRITE_WORD(p, 0x1000);
311 WRITE_WORD(p, 0);
312 /* ATAG_MEM */
313 /* TODO: handle multiple chips on one ATAG list */
314 WRITE_WORD(p, 4);
315 WRITE_WORD(p, 0x54410002);
316 WRITE_WORD(p, info->ram_size);
317 WRITE_WORD(p, info->loader_start);
318 if (initrd_size) {
319 /* ATAG_INITRD2 */
320 WRITE_WORD(p, 4);
321 WRITE_WORD(p, 0x54420005);
322 WRITE_WORD(p, info->initrd_start);
323 WRITE_WORD(p, initrd_size);
325 if (info->kernel_cmdline && *info->kernel_cmdline) {
326 /* ATAG_CMDLINE */
327 int cmdline_size;
329 cmdline_size = strlen(info->kernel_cmdline);
330 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
331 info->kernel_cmdline, cmdline_size + 1);
332 cmdline_size = (cmdline_size >> 2) + 1;
333 WRITE_WORD(p, cmdline_size + 2);
334 WRITE_WORD(p, 0x54410009);
335 p += cmdline_size * 4;
337 if (info->atag_board) {
338 /* ATAG_BOARD */
339 int atag_board_len;
340 uint8_t atag_board_buf[0x1000];
342 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
343 WRITE_WORD(p, (atag_board_len + 8) >> 2);
344 WRITE_WORD(p, 0x414f4d50);
345 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
346 atag_board_buf, atag_board_len);
347 p += atag_board_len;
349 /* ATAG_END */
350 WRITE_WORD(p, 0);
351 WRITE_WORD(p, 0);
354 static void set_kernel_args_old(const struct arm_boot_info *info,
355 AddressSpace *as)
357 hwaddr p;
358 const char *s;
359 int initrd_size = info->initrd_size;
360 hwaddr base = info->loader_start;
362 /* see linux/include/asm-arm/setup.h */
363 p = base + KERNEL_ARGS_ADDR;
364 /* page_size */
365 WRITE_WORD(p, 4096);
366 /* nr_pages */
367 WRITE_WORD(p, info->ram_size / 4096);
368 /* ramdisk_size */
369 WRITE_WORD(p, 0);
370 #define FLAG_READONLY 1
371 #define FLAG_RDLOAD 4
372 #define FLAG_RDPROMPT 8
373 /* flags */
374 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
375 /* rootdev */
376 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
377 /* video_num_cols */
378 WRITE_WORD(p, 0);
379 /* video_num_rows */
380 WRITE_WORD(p, 0);
381 /* video_x */
382 WRITE_WORD(p, 0);
383 /* video_y */
384 WRITE_WORD(p, 0);
385 /* memc_control_reg */
386 WRITE_WORD(p, 0);
387 /* unsigned char sounddefault */
388 /* unsigned char adfsdrives */
389 /* unsigned char bytes_per_char_h */
390 /* unsigned char bytes_per_char_v */
391 WRITE_WORD(p, 0);
392 /* pages_in_bank[4] */
393 WRITE_WORD(p, 0);
394 WRITE_WORD(p, 0);
395 WRITE_WORD(p, 0);
396 WRITE_WORD(p, 0);
397 /* pages_in_vram */
398 WRITE_WORD(p, 0);
399 /* initrd_start */
400 if (initrd_size) {
401 WRITE_WORD(p, info->initrd_start);
402 } else {
403 WRITE_WORD(p, 0);
405 /* initrd_size */
406 WRITE_WORD(p, initrd_size);
407 /* rd_start */
408 WRITE_WORD(p, 0);
409 /* system_rev */
410 WRITE_WORD(p, 0);
411 /* system_serial_low */
412 WRITE_WORD(p, 0);
413 /* system_serial_high */
414 WRITE_WORD(p, 0);
415 /* mem_fclk_21285 */
416 WRITE_WORD(p, 0);
417 /* zero unused fields */
418 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
419 WRITE_WORD(p, 0);
421 s = info->kernel_cmdline;
422 if (s) {
423 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
424 } else {
425 WRITE_WORD(p, 0);
429 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base,
430 uint32_t scells, hwaddr mem_len,
431 int numa_node_id)
433 char *nodename;
434 int ret;
436 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
437 qemu_fdt_add_subnode(fdt, nodename);
438 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
439 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base,
440 scells, mem_len);
441 if (ret < 0) {
442 goto out;
445 /* only set the NUMA ID if it is specified */
446 if (numa_node_id >= 0) {
447 ret = qemu_fdt_setprop_cell(fdt, nodename,
448 "numa-node-id", numa_node_id);
450 out:
451 g_free(nodename);
452 return ret;
455 static void fdt_add_psci_node(void *fdt)
457 uint32_t cpu_suspend_fn;
458 uint32_t cpu_off_fn;
459 uint32_t cpu_on_fn;
460 uint32_t migrate_fn;
461 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
462 const char *psci_method;
463 int64_t psci_conduit;
464 int rc;
466 psci_conduit = object_property_get_int(OBJECT(armcpu),
467 "psci-conduit",
468 &error_abort);
469 switch (psci_conduit) {
470 case QEMU_PSCI_CONDUIT_DISABLED:
471 return;
472 case QEMU_PSCI_CONDUIT_HVC:
473 psci_method = "hvc";
474 break;
475 case QEMU_PSCI_CONDUIT_SMC:
476 psci_method = "smc";
477 break;
478 default:
479 g_assert_not_reached();
483 * If /psci node is present in provided DTB, assume that no fixup
484 * is necessary and all PSCI configuration should be taken as-is
486 rc = fdt_path_offset(fdt, "/psci");
487 if (rc >= 0) {
488 return;
491 qemu_fdt_add_subnode(fdt, "/psci");
492 if (armcpu->psci_version == 2) {
493 const char comp[] = "arm,psci-0.2\0arm,psci";
494 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
496 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
497 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
498 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
499 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
500 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
501 } else {
502 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
503 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
504 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
506 } else {
507 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
509 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
510 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
511 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
512 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
515 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
516 * to the instruction that should be used to invoke PSCI functions.
517 * However, the device tree binding uses 'method' instead, so that is
518 * what we should use here.
520 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
524 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
525 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
528 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
529 hwaddr addr_limit, AddressSpace *as, MachineState *ms)
531 void *fdt = NULL;
532 int size, rc, n = 0;
533 uint32_t acells, scells;
534 unsigned int i;
535 hwaddr mem_base, mem_len;
536 char **node_path;
537 Error *err = NULL;
539 if (binfo->dtb_filename) {
540 char *filename;
541 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
542 if (!filename) {
543 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
544 goto fail;
547 fdt = load_device_tree(filename, &size);
548 if (!fdt) {
549 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
550 g_free(filename);
551 goto fail;
553 g_free(filename);
554 } else {
555 fdt = binfo->get_dtb(binfo, &size);
556 if (!fdt) {
557 fprintf(stderr, "Board was unable to create a dtb blob\n");
558 goto fail;
562 if (addr_limit > addr && size > (addr_limit - addr)) {
563 /* Installing the device tree blob at addr would exceed addr_limit.
564 * Whether this constitutes failure is up to the caller to decide,
565 * so just return 0 as size, i.e., no error.
567 g_free(fdt);
568 return 0;
571 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
572 NULL, &error_fatal);
573 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
574 NULL, &error_fatal);
575 if (acells == 0 || scells == 0) {
576 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
577 goto fail;
580 if (scells < 2 && binfo->ram_size >= 4 * GiB) {
581 /* This is user error so deserves a friendlier error message
582 * than the failure of setprop_sized_cells would provide
584 fprintf(stderr, "qemu: dtb file not compatible with "
585 "RAM size > 4GB\n");
586 goto fail;
589 /* nop all root nodes matching /memory or /memory@unit-address */
590 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
591 if (err) {
592 error_report_err(err);
593 goto fail;
595 while (node_path[n]) {
596 if (g_str_has_prefix(node_path[n], "/memory")) {
597 qemu_fdt_nop_node(fdt, node_path[n]);
599 n++;
601 g_strfreev(node_path);
603 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
604 mem_base = binfo->loader_start;
605 for (i = 0; i < ms->numa_state->num_nodes; i++) {
606 mem_len = ms->numa_state->nodes[i].node_mem;
607 rc = fdt_add_memory_node(fdt, acells, mem_base,
608 scells, mem_len, i);
609 if (rc < 0) {
610 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
611 mem_base);
612 goto fail;
615 mem_base += mem_len;
617 } else {
618 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start,
619 scells, binfo->ram_size, -1);
620 if (rc < 0) {
621 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
622 binfo->loader_start);
623 goto fail;
627 rc = fdt_path_offset(fdt, "/chosen");
628 if (rc < 0) {
629 qemu_fdt_add_subnode(fdt, "/chosen");
632 if (ms->kernel_cmdline && *ms->kernel_cmdline) {
633 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
634 ms->kernel_cmdline);
635 if (rc < 0) {
636 fprintf(stderr, "couldn't set /chosen/bootargs\n");
637 goto fail;
641 if (binfo->initrd_size) {
642 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
643 binfo->initrd_start);
644 if (rc < 0) {
645 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
646 goto fail;
649 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
650 binfo->initrd_start + binfo->initrd_size);
651 if (rc < 0) {
652 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
653 goto fail;
657 fdt_add_psci_node(fdt);
659 if (binfo->modify_dtb) {
660 binfo->modify_dtb(binfo, fdt);
663 qemu_fdt_dumpdtb(fdt, size);
665 /* Put the DTB into the memory map as a ROM image: this will ensure
666 * the DTB is copied again upon reset, even if addr points into RAM.
668 rom_add_blob_fixed_as("dtb", fdt, size, addr, as);
670 g_free(fdt);
672 return size;
674 fail:
675 g_free(fdt);
676 return -1;
679 static void do_cpu_reset(void *opaque)
681 ARMCPU *cpu = opaque;
682 CPUState *cs = CPU(cpu);
683 CPUARMState *env = &cpu->env;
684 const struct arm_boot_info *info = env->boot_info;
686 cpu_reset(cs);
687 if (info) {
688 if (!info->is_linux) {
689 int i;
690 /* Jump to the entry point. */
691 uint64_t entry = info->entry;
693 switch (info->endianness) {
694 case ARM_ENDIANNESS_LE:
695 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
696 for (i = 1; i < 4; ++i) {
697 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
699 env->uncached_cpsr &= ~CPSR_E;
700 break;
701 case ARM_ENDIANNESS_BE8:
702 env->cp15.sctlr_el[1] |= SCTLR_E0E;
703 for (i = 1; i < 4; ++i) {
704 env->cp15.sctlr_el[i] |= SCTLR_EE;
706 env->uncached_cpsr |= CPSR_E;
707 break;
708 case ARM_ENDIANNESS_BE32:
709 env->cp15.sctlr_el[1] |= SCTLR_B;
710 break;
711 case ARM_ENDIANNESS_UNKNOWN:
712 break; /* Board's decision */
713 default:
714 g_assert_not_reached();
717 cpu_set_pc(cs, entry);
718 } else {
719 /* If we are booting Linux then we need to check whether we are
720 * booting into secure or non-secure state and adjust the state
721 * accordingly. Out of reset, ARM is defined to be in secure state
722 * (SCR.NS = 0), we change that here if non-secure boot has been
723 * requested.
725 if (arm_feature(env, ARM_FEATURE_EL3)) {
726 /* AArch64 is defined to come out of reset into EL3 if enabled.
727 * If we are booting Linux then we need to adjust our EL as
728 * Linux expects us to be in EL2 or EL1. AArch32 resets into
729 * SVC, which Linux expects, so no privilege/exception level to
730 * adjust.
732 if (env->aarch64) {
733 env->cp15.scr_el3 |= SCR_RW;
734 if (arm_feature(env, ARM_FEATURE_EL2)) {
735 env->cp15.hcr_el2 |= HCR_RW;
736 env->pstate = PSTATE_MODE_EL2h;
737 } else {
738 env->pstate = PSTATE_MODE_EL1h;
740 if (cpu_isar_feature(aa64_pauth, cpu)) {
741 env->cp15.scr_el3 |= SCR_API | SCR_APK;
743 if (cpu_isar_feature(aa64_mte, cpu)) {
744 env->cp15.scr_el3 |= SCR_ATA;
746 if (cpu_isar_feature(aa64_sve, cpu)) {
747 env->cp15.cptr_el[3] |= CPTR_EZ;
749 /* AArch64 kernels never boot in secure mode */
750 assert(!info->secure_boot);
751 /* This hook is only supported for AArch32 currently:
752 * bootloader_aarch64[] will not call the hook, and
753 * the code above has already dropped us into EL2 or EL1.
755 assert(!info->secure_board_setup);
758 if (arm_feature(env, ARM_FEATURE_EL2)) {
759 /* If we have EL2 then Linux expects the HVC insn to work */
760 env->cp15.scr_el3 |= SCR_HCE;
763 /* Set to non-secure if not a secure boot */
764 if (!info->secure_boot &&
765 (cs != first_cpu || !info->secure_board_setup)) {
766 /* Linux expects non-secure state */
767 env->cp15.scr_el3 |= SCR_NS;
768 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
769 env->cp15.nsacr |= 3 << 10;
773 if (!env->aarch64 && !info->secure_boot &&
774 arm_feature(env, ARM_FEATURE_EL2)) {
776 * This is an AArch32 boot not to Secure state, and
777 * we have Hyp mode available, so boot the kernel into
778 * Hyp mode. This is not how the CPU comes out of reset,
779 * so we need to manually put it there.
781 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
784 if (cs == first_cpu) {
785 AddressSpace *as = arm_boot_address_space(cpu, info);
787 cpu_set_pc(cs, info->loader_start);
789 if (!have_dtb(info)) {
790 if (old_param) {
791 set_kernel_args_old(info, as);
792 } else {
793 set_kernel_args(info, as);
796 } else {
797 info->secondary_cpu_reset_hook(cpu, info);
800 arm_rebuild_hflags(env);
805 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
806 * by key.
807 * @fw_cfg: The firmware config instance to store the data in.
808 * @size_key: The firmware config key to store the size of the loaded
809 * data under, with fw_cfg_add_i32().
810 * @data_key: The firmware config key to store the loaded data under,
811 * with fw_cfg_add_bytes().
812 * @image_name: The name of the image file to load. If it is NULL, the
813 * function returns without doing anything.
814 * @try_decompress: Whether the image should be decompressed (gunzipped) before
815 * adding it to fw_cfg. If decompression fails, the image is
816 * loaded as-is.
818 * In case of failure, the function prints an error message to stderr and the
819 * process exits with status 1.
821 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
822 uint16_t data_key, const char *image_name,
823 bool try_decompress)
825 size_t size = -1;
826 uint8_t *data;
828 if (image_name == NULL) {
829 return;
832 if (try_decompress) {
833 size = load_image_gzipped_buffer(image_name,
834 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
837 if (size == (size_t)-1) {
838 gchar *contents;
839 gsize length;
841 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
842 error_report("failed to load \"%s\"", image_name);
843 exit(1);
845 size = length;
846 data = (uint8_t *)contents;
849 fw_cfg_add_i32(fw_cfg, size_key, size);
850 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
853 static int do_arm_linux_init(Object *obj, void *opaque)
855 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
856 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
857 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
858 struct arm_boot_info *info = opaque;
860 if (albifc->arm_linux_init) {
861 albifc->arm_linux_init(albif, info->secure_boot);
864 return 0;
867 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
868 uint64_t *lowaddr, uint64_t *highaddr,
869 int elf_machine, AddressSpace *as)
871 bool elf_is64;
872 union {
873 Elf32_Ehdr h32;
874 Elf64_Ehdr h64;
875 } elf_header;
876 int data_swab = 0;
877 bool big_endian;
878 int64_t ret = -1;
879 Error *err = NULL;
882 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
883 if (err) {
884 error_free(err);
885 return ret;
888 if (elf_is64) {
889 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
890 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
891 : ARM_ENDIANNESS_LE;
892 } else {
893 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
894 if (big_endian) {
895 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
896 info->endianness = ARM_ENDIANNESS_BE8;
897 } else {
898 info->endianness = ARM_ENDIANNESS_BE32;
899 /* In BE32, the CPU has a different view of the per-byte
900 * address map than the rest of the system. BE32 ELF files
901 * are organised such that they can be programmed through
902 * the CPU's per-word byte-reversed view of the world. QEMU
903 * however loads ELF files independently of the CPU. So
904 * tell the ELF loader to byte reverse the data for us.
906 data_swab = 2;
908 } else {
909 info->endianness = ARM_ENDIANNESS_LE;
913 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL,
914 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine,
915 1, data_swab, as);
916 if (ret <= 0) {
917 /* The header loaded but the image didn't */
918 exit(1);
921 return ret;
924 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
925 hwaddr *entry, AddressSpace *as)
927 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
928 uint64_t kernel_size = 0;
929 uint8_t *buffer;
930 int size;
932 /* On aarch64, it's the bootloader's job to uncompress the kernel. */
933 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
934 &buffer);
936 if (size < 0) {
937 gsize len;
939 /* Load as raw file otherwise */
940 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
941 return -1;
943 size = len;
946 /* check the arm64 magic header value -- very old kernels may not have it */
947 if (size > ARM64_MAGIC_OFFSET + 4 &&
948 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
949 uint64_t hdrvals[2];
951 /* The arm64 Image header has text_offset and image_size fields at 8 and
952 * 16 bytes into the Image header, respectively. The text_offset field
953 * is only valid if the image_size is non-zero.
955 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
957 kernel_size = le64_to_cpu(hdrvals[1]);
959 if (kernel_size != 0) {
960 kernel_load_offset = le64_to_cpu(hdrvals[0]);
963 * We write our startup "bootloader" at the very bottom of RAM,
964 * so that bit can't be used for the image. Luckily the Image
965 * format specification is that the image requests only an offset
966 * from a 2MB boundary, not an absolute load address. So if the
967 * image requests an offset that might mean it overlaps with the
968 * bootloader, we can just load it starting at 2MB+offset rather
969 * than 0MB + offset.
971 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
972 kernel_load_offset += 2 * MiB;
978 * Kernels before v3.17 don't populate the image_size field, and
979 * raw images have no header. For those our best guess at the size
980 * is the size of the Image file itself.
982 if (kernel_size == 0) {
983 kernel_size = size;
986 *entry = mem_base + kernel_load_offset;
987 rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
989 g_free(buffer);
991 return kernel_size;
994 static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
995 struct arm_boot_info *info)
997 /* Set up for a direct boot of a kernel image file. */
998 CPUState *cs;
999 AddressSpace *as = arm_boot_address_space(cpu, info);
1000 int kernel_size;
1001 int initrd_size;
1002 int is_linux = 0;
1003 uint64_t elf_entry;
1004 /* Addresses of first byte used and first byte not used by the image */
1005 uint64_t image_low_addr = 0, image_high_addr = 0;
1006 int elf_machine;
1007 hwaddr entry;
1008 static const ARMInsnFixup *primary_loader;
1009 uint64_t ram_end = info->loader_start + info->ram_size;
1011 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1012 primary_loader = bootloader_aarch64;
1013 elf_machine = EM_AARCH64;
1014 } else {
1015 primary_loader = bootloader;
1016 if (!info->write_board_setup) {
1017 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
1019 elf_machine = EM_ARM;
1022 if (!info->secondary_cpu_reset_hook) {
1023 info->secondary_cpu_reset_hook = default_reset_secondary;
1025 if (!info->write_secondary_boot) {
1026 info->write_secondary_boot = default_write_secondary;
1029 if (info->nb_cpus == 0)
1030 info->nb_cpus = 1;
1032 /* Assume that raw images are linux kernels, and ELF images are not. */
1033 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr,
1034 &image_high_addr, elf_machine, as);
1035 if (kernel_size > 0 && have_dtb(info)) {
1037 * If there is still some room left at the base of RAM, try and put
1038 * the DTB there like we do for images loaded with -bios or -pflash.
1040 if (image_low_addr > info->loader_start
1041 || image_high_addr < info->loader_start) {
1043 * Set image_low_addr as address limit for arm_load_dtb if it may be
1044 * pointing into RAM, otherwise pass '0' (no limit)
1046 if (image_low_addr < info->loader_start) {
1047 image_low_addr = 0;
1049 info->dtb_start = info->loader_start;
1050 info->dtb_limit = image_low_addr;
1053 entry = elf_entry;
1054 if (kernel_size < 0) {
1055 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR;
1056 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr,
1057 &is_linux, NULL, NULL, as);
1058 if (kernel_size >= 0) {
1059 image_low_addr = loadaddr;
1060 image_high_addr = image_low_addr + kernel_size;
1063 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
1064 kernel_size = load_aarch64_image(info->kernel_filename,
1065 info->loader_start, &entry, as);
1066 is_linux = 1;
1067 if (kernel_size >= 0) {
1068 image_low_addr = entry;
1069 image_high_addr = image_low_addr + kernel_size;
1071 } else if (kernel_size < 0) {
1072 /* 32-bit ARM */
1073 entry = info->loader_start + KERNEL_LOAD_ADDR;
1074 kernel_size = load_image_targphys_as(info->kernel_filename, entry,
1075 ram_end - KERNEL_LOAD_ADDR, as);
1076 is_linux = 1;
1077 if (kernel_size >= 0) {
1078 image_low_addr = entry;
1079 image_high_addr = image_low_addr + kernel_size;
1082 if (kernel_size < 0) {
1083 error_report("could not load kernel '%s'", info->kernel_filename);
1084 exit(1);
1087 if (kernel_size > info->ram_size) {
1088 error_report("kernel '%s' is too large to fit in RAM "
1089 "(kernel size %d, RAM size %" PRId64 ")",
1090 info->kernel_filename, kernel_size, info->ram_size);
1091 exit(1);
1094 info->entry = entry;
1097 * We want to put the initrd far enough into RAM that when the
1098 * kernel is uncompressed it will not clobber the initrd. However
1099 * on boards without much RAM we must ensure that we still leave
1100 * enough room for a decent sized initrd, and on boards with large
1101 * amounts of RAM we must avoid the initrd being so far up in RAM
1102 * that it is outside lowmem and inaccessible to the kernel.
1103 * So for boards with less than 256MB of RAM we put the initrd
1104 * halfway into RAM, and for boards with 256MB of RAM or more we put
1105 * the initrd at 128MB.
1106 * We also refuse to put the initrd somewhere that will definitely
1107 * overlay the kernel we just loaded, though for kernel formats which
1108 * don't tell us their exact size (eg self-decompressing 32-bit kernels)
1109 * we might still make a bad choice here.
1111 info->initrd_start = info->loader_start +
1112 MIN(info->ram_size / 2, 128 * MiB);
1113 if (image_high_addr) {
1114 info->initrd_start = MAX(info->initrd_start, image_high_addr);
1116 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
1118 if (is_linux) {
1119 uint32_t fixupcontext[FIXUP_MAX];
1121 if (info->initrd_filename) {
1123 if (info->initrd_start >= ram_end) {
1124 error_report("not enough space after kernel to load initrd");
1125 exit(1);
1128 initrd_size = load_ramdisk_as(info->initrd_filename,
1129 info->initrd_start,
1130 ram_end - info->initrd_start, as);
1131 if (initrd_size < 0) {
1132 initrd_size = load_image_targphys_as(info->initrd_filename,
1133 info->initrd_start,
1134 ram_end -
1135 info->initrd_start,
1136 as);
1138 if (initrd_size < 0) {
1139 error_report("could not load initrd '%s'",
1140 info->initrd_filename);
1141 exit(1);
1143 if (info->initrd_start + initrd_size > ram_end) {
1144 error_report("could not load initrd '%s': "
1145 "too big to fit into RAM after the kernel",
1146 info->initrd_filename);
1147 exit(1);
1149 } else {
1150 initrd_size = 0;
1152 info->initrd_size = initrd_size;
1154 fixupcontext[FIXUP_BOARDID] = info->board_id;
1155 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
1158 * for device tree boot, we pass the DTB directly in r2. Otherwise
1159 * we point to the kernel args.
1161 if (have_dtb(info)) {
1162 hwaddr align;
1164 if (elf_machine == EM_AARCH64) {
1166 * Some AArch64 kernels on early bootup map the fdt region as
1168 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]
1170 * Let's play safe and prealign it to 2MB to give us some space.
1172 align = 2 * MiB;
1173 } else {
1175 * Some 32bit kernels will trash anything in the 4K page the
1176 * initrd ends in, so make sure the DTB isn't caught up in that.
1178 align = 4 * KiB;
1181 /* Place the DTB after the initrd in memory with alignment. */
1182 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
1183 align);
1184 if (info->dtb_start >= ram_end) {
1185 error_report("Not enough space for DTB after kernel/initrd");
1186 exit(1);
1188 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
1189 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
1190 } else {
1191 fixupcontext[FIXUP_ARGPTR_LO] =
1192 info->loader_start + KERNEL_ARGS_ADDR;
1193 fixupcontext[FIXUP_ARGPTR_HI] =
1194 (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
1195 if (info->ram_size >= 4 * GiB) {
1196 error_report("RAM size must be less than 4GB to boot"
1197 " Linux kernel using ATAGS (try passing a device tree"
1198 " using -dtb)");
1199 exit(1);
1202 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
1203 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
1205 write_bootloader("bootloader", info->loader_start,
1206 primary_loader, fixupcontext, as);
1208 if (info->nb_cpus > 1) {
1209 info->write_secondary_boot(cpu, info);
1211 if (info->write_board_setup) {
1212 info->write_board_setup(cpu, info);
1216 * Notify devices which need to fake up firmware initialization
1217 * that we're doing a direct kernel boot.
1219 object_child_foreach_recursive(object_get_root(),
1220 do_arm_linux_init, info);
1222 info->is_linux = is_linux;
1224 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1225 ARM_CPU(cs)->env.boot_info = info;
1229 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info)
1231 /* Set up for booting firmware (which might load a kernel via fw_cfg) */
1233 if (have_dtb(info)) {
1235 * If we have a device tree blob, but no kernel to supply it to (or
1236 * the kernel is supposed to be loaded by the bootloader), copy the
1237 * DTB to the base of RAM for the bootloader to pick up.
1239 info->dtb_start = info->loader_start;
1242 if (info->kernel_filename) {
1243 FWCfgState *fw_cfg;
1244 bool try_decompressing_kernel;
1246 fw_cfg = fw_cfg_find();
1247 try_decompressing_kernel = arm_feature(&cpu->env,
1248 ARM_FEATURE_AARCH64);
1251 * Expose the kernel, the command line, and the initrd in fw_cfg.
1252 * We don't process them here at all, it's all left to the
1253 * firmware.
1255 load_image_to_fw_cfg(fw_cfg,
1256 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
1257 info->kernel_filename,
1258 try_decompressing_kernel);
1259 load_image_to_fw_cfg(fw_cfg,
1260 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
1261 info->initrd_filename, false);
1263 if (info->kernel_cmdline) {
1264 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1265 strlen(info->kernel_cmdline) + 1);
1266 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
1267 info->kernel_cmdline);
1272 * We will start from address 0 (typically a boot ROM image) in the
1273 * same way as hardware. Leave env->boot_info NULL, so that
1274 * do_cpu_reset() knows it does not need to alter the PC on reset.
1278 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
1280 CPUState *cs;
1281 AddressSpace *as = arm_boot_address_space(cpu, info);
1284 * CPU objects (unlike devices) are not automatically reset on system
1285 * reset, so we must always register a handler to do so. If we're
1286 * actually loading a kernel, the handler is also responsible for
1287 * arranging that we start it correctly.
1289 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1290 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1294 * The board code is not supposed to set secure_board_setup unless
1295 * running its code in secure mode is actually possible, and KVM
1296 * doesn't support secure.
1298 assert(!(info->secure_board_setup && kvm_enabled()));
1299 info->kernel_filename = ms->kernel_filename;
1300 info->kernel_cmdline = ms->kernel_cmdline;
1301 info->initrd_filename = ms->initrd_filename;
1302 info->dtb_filename = ms->dtb;
1303 info->dtb_limit = 0;
1305 /* Load the kernel. */
1306 if (!info->kernel_filename || info->firmware_loaded) {
1307 arm_setup_firmware_boot(cpu, info);
1308 } else {
1309 arm_setup_direct_kernel_boot(cpu, info);
1312 if (!info->skip_dtb_autoload && have_dtb(info)) {
1313 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1314 exit(1);
1319 static const TypeInfo arm_linux_boot_if_info = {
1320 .name = TYPE_ARM_LINUX_BOOT_IF,
1321 .parent = TYPE_INTERFACE,
1322 .class_size = sizeof(ARMLinuxBootIfClass),
1325 static void arm_linux_boot_register_types(void)
1327 type_register_static(&arm_linux_boot_if_info);
1330 type_init(arm_linux_boot_register_types)