target-s390x/ioinst.c

   1 /*
   2  * I/O instructions for S/390
   3  *
   4  * Copyright 2012 IBM Corp.
   5  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8  * your option) any later version. See the COPYING file in the top-level
   9  * directory.
  10  */
  11
  12 #include <sys/types.h>
  13
  14 #include "cpu.h"
  15 #include "ioinst.h"
  16 #include "trace.h"
  17
  18 int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
  19                                  int *schid)
  20 {
  21     if (!IOINST_SCHID_ONE(value)) {
  22         return -EINVAL;
  23     }
  24     if (!IOINST_SCHID_M(value)) {
  25         if (IOINST_SCHID_CSSID(value)) {
  26             return -EINVAL;
  27         }
  28         *cssid = 0;
  29         *m = 0;
  30     } else {
  31         *cssid = IOINST_SCHID_CSSID(value);
  32         *m = 1;
  33     }
  34     *ssid = IOINST_SCHID_SSID(value);
  35     *schid = IOINST_SCHID_NR(value);
  36     return 0;
  37 }
  38
  39 int ioinst_handle_xsch(CPUS390XState *env, uint64_t reg1)
  40 {
  41     int cssid, ssid, schid, m;
  42     SubchDev *sch;
  43     int ret = -ENODEV;
  44     int cc;
  45
  46     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  47         program_interrupt(env, PGM_OPERAND, 2);
  48         return -EIO;
  49     }
  50     trace_ioinst_sch_id("xsch", cssid, ssid, schid);
  51     sch = css_find_subch(m, cssid, ssid, schid);
  52     if (sch && css_subch_visible(sch)) {
  53         ret = css_do_xsch(sch);
  54     }
  55     switch (ret) {
  56     case -ENODEV:
  57         cc = 3;
  58         break;
  59     case -EBUSY:
  60         cc = 2;
  61         break;
  62     case 0:
  63         cc = 0;
  64         break;
  65     default:
  66         cc = 1;
  67         break;
  68     }
  69
  70     return cc;
  71 }
  72
  73 int ioinst_handle_csch(CPUS390XState *env, uint64_t reg1)
  74 {
  75     int cssid, ssid, schid, m;
  76     SubchDev *sch;
  77     int ret = -ENODEV;
  78     int cc;
  79
  80     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  81         program_interrupt(env, PGM_OPERAND, 2);
  82         return -EIO;
  83     }
  84     trace_ioinst_sch_id("csch", cssid, ssid, schid);
  85     sch = css_find_subch(m, cssid, ssid, schid);
  86     if (sch && css_subch_visible(sch)) {
  87         ret = css_do_csch(sch);
  88     }
  89     if (ret == -ENODEV) {
  90         cc = 3;
  91     } else {
  92         cc = 0;
  93     }
  94     return cc;
  95 }
  96
  97 int ioinst_handle_hsch(CPUS390XState *env, uint64_t reg1)
  98 {
  99     int cssid, ssid, schid, m;
 100     SubchDev *sch;
 101     int ret = -ENODEV;
 102     int cc;
 103
 104     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 105         program_interrupt(env, PGM_OPERAND, 2);
 106         return -EIO;
 107     }
 108     trace_ioinst_sch_id("hsch", cssid, ssid, schid);
 109     sch = css_find_subch(m, cssid, ssid, schid);
 110     if (sch && css_subch_visible(sch)) {
 111         ret = css_do_hsch(sch);
 112     }
 113     switch (ret) {
 114     case -ENODEV:
 115         cc = 3;
 116         break;
 117     case -EBUSY:
 118         cc = 2;
 119         break;
 120     case 0:
 121         cc = 0;
 122         break;
 123     default:
 124         cc = 1;
 125         break;
 126     }
 127
 128     return cc;
 129 }
 130
 131 static int ioinst_schib_valid(SCHIB *schib)
 132 {
 133     if ((schib->pmcw.flags & PMCW_FLAGS_MASK_INVALID) ||
 134         (schib->pmcw.chars & PMCW_CHARS_MASK_INVALID)) {
 135         return 0;
 136     }
 137     /* Disallow extended measurements for now. */
 138     if (schib->pmcw.chars & PMCW_CHARS_MASK_XMWME) {
 139         return 0;
 140     }
 141     return 1;
 142 }
 143
 144 int ioinst_handle_msch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
 145 {
 146     int cssid, ssid, schid, m;
 147     SubchDev *sch;
 148     SCHIB *schib;
 149     uint64_t addr;
 150     int ret = -ENODEV;
 151     int cc;
 152     hwaddr len = sizeof(*schib);
 153
 154     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 155         program_interrupt(env, PGM_OPERAND, 2);
 156         return -EIO;
 157     }
 158     trace_ioinst_sch_id("msch", cssid, ssid, schid);
 159     addr = decode_basedisp_s(env, ipb);
 160     if (addr & 3) {
 161         program_interrupt(env, PGM_SPECIFICATION, 2);
 162         return -EIO;
 163     }
 164     schib = s390_cpu_physical_memory_map(env, addr, &len, 0);
 165     if (!schib || len != sizeof(*schib)) {
 166         program_interrupt(env, PGM_SPECIFICATION, 2);
 167         cc = -EIO;
 168         goto out;
 169     }
 170     if (!ioinst_schib_valid(schib)) {
 171         program_interrupt(env, PGM_OPERAND, 2);
 172         cc = -EIO;
 173         goto out;
 174     }
 175     sch = css_find_subch(m, cssid, ssid, schid);
 176     if (sch && css_subch_visible(sch)) {
 177         ret = css_do_msch(sch, schib);
 178     }
 179     switch (ret) {
 180     case -ENODEV:
 181         cc = 3;
 182         break;
 183     case -EBUSY:
 184         cc = 2;
 185         break;
 186     case 0:
 187         cc = 0;
 188         break;
 189     default:
 190         cc = 1;
 191         break;
 192     }
 193 out:
 194     s390_cpu_physical_memory_unmap(env, schib, len, 0);
 195     return cc;
 196 }
 197
 198 static void copy_orb_from_guest(ORB *dest, const ORB *src)
 199 {
 200     dest->intparm = be32_to_cpu(src->intparm);
 201     dest->ctrl0 = be16_to_cpu(src->ctrl0);
 202     dest->lpm = src->lpm;
 203     dest->ctrl1 = src->ctrl1;
 204     dest->cpa = be32_to_cpu(src->cpa);
 205 }
 206
 207 static int ioinst_orb_valid(ORB *orb)
 208 {
 209     if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
 210         (orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
 211         return 0;
 212     }
 213     if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
 214         return 0;
 215     }
 216     return 1;
 217 }
 218
 219 int ioinst_handle_ssch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
 220 {
 221     int cssid, ssid, schid, m;
 222     SubchDev *sch;
 223     ORB *orig_orb, orb;
 224     uint64_t addr;
 225     int ret = -ENODEV;
 226     int cc;
 227     hwaddr len = sizeof(*orig_orb);
 228
 229     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 230         program_interrupt(env, PGM_OPERAND, 2);
 231         return -EIO;
 232     }
 233     trace_ioinst_sch_id("ssch", cssid, ssid, schid);
 234     addr = decode_basedisp_s(env, ipb);
 235     if (addr & 3) {
 236         program_interrupt(env, PGM_SPECIFICATION, 2);
 237         return -EIO;
 238     }
 239     orig_orb = s390_cpu_physical_memory_map(env, addr, &len, 0);
 240     if (!orig_orb || len != sizeof(*orig_orb)) {
 241         program_interrupt(env, PGM_SPECIFICATION, 2);
 242         cc = -EIO;
 243         goto out;
 244     }
 245     copy_orb_from_guest(&orb, orig_orb);
 246     if (!ioinst_orb_valid(&orb)) {
 247         program_interrupt(env, PGM_OPERAND, 2);
 248         cc = -EIO;
 249         goto out;
 250     }
 251     sch = css_find_subch(m, cssid, ssid, schid);
 252     if (sch && css_subch_visible(sch)) {
 253         ret = css_do_ssch(sch, &orb);
 254     }
 255     switch (ret) {
 256     case -ENODEV:
 257         cc = 3;
 258         break;
 259     case -EBUSY:
 260         cc = 2;
 261         break;
 262     case 0:
 263         cc = 0;
 264         break;
 265     default:
 266         cc = 1;
 267         break;
 268     }
 269
 270 out:
 271     s390_cpu_physical_memory_unmap(env, orig_orb, len, 0);
 272     return cc;
 273 }
 274
 275 int ioinst_handle_stcrw(CPUS390XState *env, uint32_t ipb)
 276 {
 277     CRW *crw;
 278     uint64_t addr;
 279     int cc;
 280     hwaddr len = sizeof(*crw);
 281
 282     addr = decode_basedisp_s(env, ipb);
 283     if (addr & 3) {
 284         program_interrupt(env, PGM_SPECIFICATION, 2);
 285         return -EIO;
 286     }
 287     crw = s390_cpu_physical_memory_map(env, addr, &len, 1);
 288     if (!crw || len != sizeof(*crw)) {
 289         program_interrupt(env, PGM_SPECIFICATION, 2);
 290         cc = -EIO;
 291         goto out;
 292     }
 293     cc = css_do_stcrw(crw);
 294     /* 0 - crw stored, 1 - zeroes stored */
 295 out:
 296     s390_cpu_physical_memory_unmap(env, crw, len, 1);
 297     return cc;
 298 }
 299
 300 int ioinst_handle_stsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
 301 {
 302     int cssid, ssid, schid, m;
 303     SubchDev *sch;
 304     uint64_t addr;
 305     int cc;
 306     SCHIB *schib;
 307     hwaddr len = sizeof(*schib);
 308
 309     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 310         program_interrupt(env, PGM_OPERAND, 2);
 311         return -EIO;
 312     }
 313     trace_ioinst_sch_id("stsch", cssid, ssid, schid);
 314     addr = decode_basedisp_s(env, ipb);
 315     if (addr & 3) {
 316         program_interrupt(env, PGM_SPECIFICATION, 2);
 317         return -EIO;
 318     }
 319     schib = s390_cpu_physical_memory_map(env, addr, &len, 1);
 320     if (!schib || len != sizeof(*schib)) {
 321         program_interrupt(env, PGM_SPECIFICATION, 2);
 322         cc = -EIO;
 323         goto out;
 324     }
 325     sch = css_find_subch(m, cssid, ssid, schid);
 326     if (sch) {
 327         if (css_subch_visible(sch)) {
 328             css_do_stsch(sch, schib);
 329             cc = 0;
 330         } else {
 331             /* Indicate no more subchannels in this css/ss */
 332             cc = 3;
 333         }
 334     } else {
 335         if (css_schid_final(m, cssid, ssid, schid)) {
 336             cc = 3; /* No more subchannels in this css/ss */
 337         } else {
 338             /* Store an empty schib. */
 339             memset(schib, 0, sizeof(*schib));
 340             cc = 0;
 341         }
 342     }
 343 out:
 344     s390_cpu_physical_memory_unmap(env, schib, len, 1);
 345     return cc;
 346 }
 347
 348 int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
 349 {
 350     int cssid, ssid, schid, m;
 351     SubchDev *sch;
 352     IRB *irb;
 353     uint64_t addr;
 354     int ret = -ENODEV;
 355     int cc;
 356     hwaddr len = sizeof(*irb);
 357
 358     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 359         program_interrupt(env, PGM_OPERAND, 2);
 360         return -EIO;
 361     }
 362     trace_ioinst_sch_id("tsch", cssid, ssid, schid);
 363     addr = decode_basedisp_s(env, ipb);
 364     if (addr & 3) {
 365         program_interrupt(env, PGM_SPECIFICATION, 2);
 366         return -EIO;
 367     }
 368     irb = s390_cpu_physical_memory_map(env, addr, &len, 1);
 369     if (!irb || len != sizeof(*irb)) {
 370         program_interrupt(env, PGM_SPECIFICATION, 2);
 371         cc = -EIO;
 372         goto out;
 373     }
 374     sch = css_find_subch(m, cssid, ssid, schid);
 375     if (sch && css_subch_visible(sch)) {
 376         ret = css_do_tsch(sch, irb);
 377         /* 0 - status pending, 1 - not status pending */
 378         cc = ret;
 379     } else {
 380         cc = 3;
 381     }
 382 out:
 383     s390_cpu_physical_memory_unmap(env, irb, sizeof(*irb), 1);
 384     return cc;
 385 }
 386
 387 typedef struct ChscReq {
 388     uint16_t len;
 389     uint16_t command;
 390     uint32_t param0;
 391     uint32_t param1;
 392     uint32_t param2;
 393 } QEMU_PACKED ChscReq;
 394
 395 typedef struct ChscResp {
 396     uint16_t len;
 397     uint16_t code;
 398     uint32_t param;
 399     char data[0];
 400 } QEMU_PACKED ChscResp;
 401
 402 #define CHSC_MIN_RESP_LEN 0x0008
 403
 404 #define CHSC_SCPD 0x0002
 405 #define CHSC_SCSC 0x0010
 406 #define CHSC_SDA  0x0031
 407
 408 #define CHSC_SCPD_0_M 0x20000000
 409 #define CHSC_SCPD_0_C 0x10000000
 410 #define CHSC_SCPD_0_FMT 0x0f000000
 411 #define CHSC_SCPD_0_CSSID 0x00ff0000
 412 #define CHSC_SCPD_0_RFMT 0x00000f00
 413 #define CHSC_SCPD_0_RES 0xc000f000
 414 #define CHSC_SCPD_1_RES 0xffffff00
 415 #define CHSC_SCPD_01_CHPID 0x000000ff
 416 static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
 417 {
 418     uint16_t len = be16_to_cpu(req->len);
 419     uint32_t param0 = be32_to_cpu(req->param0);
 420     uint32_t param1 = be32_to_cpu(req->param1);
 421     uint16_t resp_code;
 422     int rfmt;
 423     uint16_t cssid;
 424     uint8_t f_chpid, l_chpid;
 425     int desc_size;
 426     int m;
 427
 428     rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
 429     if ((rfmt == 0) ||  (rfmt == 1)) {
 430         rfmt = !!(param0 & CHSC_SCPD_0_C);
 431     }
 432     if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
 433         (param1 & CHSC_SCPD_1_RES) || req->param2) {
 434         resp_code = 0x0003;
 435         goto out_err;
 436     }
 437     if (param0 & CHSC_SCPD_0_FMT) {
 438         resp_code = 0x0007;
 439         goto out_err;
 440     }
 441     cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
 442     m = param0 & CHSC_SCPD_0_M;
 443     if (cssid != 0) {
 444         if (!m || !css_present(cssid)) {
 445             resp_code = 0x0008;
 446             goto out_err;
 447         }
 448     }
 449     f_chpid = param0 & CHSC_SCPD_01_CHPID;
 450     l_chpid = param1 & CHSC_SCPD_01_CHPID;
 451     if (l_chpid < f_chpid) {
 452         resp_code = 0x0003;
 453         goto out_err;
 454     }
 455     /* css_collect_chp_desc() is endian-aware */
 456     desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
 457                                      &res->data);
 458     res->code = cpu_to_be16(0x0001);
 459     res->len = cpu_to_be16(8 + desc_size);
 460     res->param = cpu_to_be32(rfmt);
 461     return;
 462
 463   out_err:
 464     res->code = cpu_to_be16(resp_code);
 465     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 466     res->param = cpu_to_be32(rfmt);
 467 }
 468
 469 #define CHSC_SCSC_0_M 0x20000000
 470 #define CHSC_SCSC_0_FMT 0x000f0000
 471 #define CHSC_SCSC_0_CSSID 0x0000ff00
 472 #define CHSC_SCSC_0_RES 0xdff000ff
 473 static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
 474 {
 475     uint16_t len = be16_to_cpu(req->len);
 476     uint32_t param0 = be32_to_cpu(req->param0);
 477     uint8_t cssid;
 478     uint16_t resp_code;
 479     uint32_t general_chars[510];
 480     uint32_t chsc_chars[508];
 481
 482     if (len != 0x0010) {
 483         resp_code = 0x0003;
 484         goto out_err;
 485     }
 486
 487     if (param0 & CHSC_SCSC_0_FMT) {
 488         resp_code = 0x0007;
 489         goto out_err;
 490     }
 491     cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
 492     if (cssid != 0) {
 493         if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
 494             resp_code = 0x0008;
 495             goto out_err;
 496         }
 497     }
 498     if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
 499         resp_code = 0x0003;
 500         goto out_err;
 501     }
 502     res->code = cpu_to_be16(0x0001);
 503     res->len = cpu_to_be16(4080);
 504     res->param = 0;
 505
 506     memset(general_chars, 0, sizeof(general_chars));
 507     memset(chsc_chars, 0, sizeof(chsc_chars));
 508
 509     general_chars[0] = cpu_to_be32(0x03000000);
 510     general_chars[1] = cpu_to_be32(0x00059000);
 511
 512     chsc_chars[0] = cpu_to_be32(0x40000000);
 513     chsc_chars[3] = cpu_to_be32(0x00040000);
 514
 515     memcpy(res->data, general_chars, sizeof(general_chars));
 516     memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
 517     return;
 518
 519   out_err:
 520     res->code = cpu_to_be16(resp_code);
 521     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 522     res->param = 0;
 523 }
 524
 525 #define CHSC_SDA_0_FMT 0x0f000000
 526 #define CHSC_SDA_0_OC 0x0000ffff
 527 #define CHSC_SDA_0_RES 0xf0ff0000
 528 #define CHSC_SDA_OC_MCSSE 0x0
 529 #define CHSC_SDA_OC_MSS 0x2
 530 static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
 531 {
 532     uint16_t resp_code = 0x0001;
 533     uint16_t len = be16_to_cpu(req->len);
 534     uint32_t param0 = be32_to_cpu(req->param0);
 535     uint16_t oc;
 536     int ret;
 537
 538     if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
 539         resp_code = 0x0003;
 540         goto out;
 541     }
 542
 543     if (param0 & CHSC_SDA_0_FMT) {
 544         resp_code = 0x0007;
 545         goto out;
 546     }
 547
 548     oc = param0 & CHSC_SDA_0_OC;
 549     switch (oc) {
 550     case CHSC_SDA_OC_MCSSE:
 551         ret = css_enable_mcsse();
 552         if (ret == -EINVAL) {
 553             resp_code = 0x0101;
 554             goto out;
 555         }
 556         break;
 557     case CHSC_SDA_OC_MSS:
 558         ret = css_enable_mss();
 559         if (ret == -EINVAL) {
 560             resp_code = 0x0101;
 561             goto out;
 562         }
 563         break;
 564     default:
 565         resp_code = 0x0003;
 566         goto out;
 567     }
 568
 569 out:
 570     res->code = cpu_to_be16(resp_code);
 571     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 572     res->param = 0;
 573 }
 574
 575 static void ioinst_handle_chsc_unimplemented(ChscResp *res)
 576 {
 577     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 578     res->code = cpu_to_be16(0x0004);
 579     res->param = 0;
 580 }
 581
 582 int ioinst_handle_chsc(CPUS390XState *env, uint32_t ipb)
 583 {
 584     ChscReq *req;
 585     ChscResp *res;
 586     uint64_t addr;
 587     int reg;
 588     uint16_t len;
 589     uint16_t command;
 590     hwaddr map_size = TARGET_PAGE_SIZE;
 591     int ret = 0;
 592
 593     trace_ioinst("chsc");
 594     reg = (ipb >> 20) & 0x00f;
 595     addr = env->regs[reg];
 596     /* Page boundary? */
 597     if (addr & 0xfff) {
 598         program_interrupt(env, PGM_SPECIFICATION, 2);
 599         return -EIO;
 600     }
 601     req = s390_cpu_physical_memory_map(env, addr, &map_size, 1);
 602     if (!req || map_size != TARGET_PAGE_SIZE) {
 603         program_interrupt(env, PGM_SPECIFICATION, 2);
 604         ret = -EIO;
 605         goto out;
 606     }
 607     len = be16_to_cpu(req->len);
 608     /* Length field valid? */
 609     if ((len < 16) || (len > 4088) || (len & 7)) {
 610         program_interrupt(env, PGM_OPERAND, 2);
 611         ret = -EIO;
 612         goto out;
 613     }
 614     memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
 615     res = (void *)((char *)req + len);
 616     command = be16_to_cpu(req->command);
 617     trace_ioinst_chsc_cmd(command, len);
 618     switch (command) {
 619     case CHSC_SCSC:
 620         ioinst_handle_chsc_scsc(req, res);
 621         break;
 622     case CHSC_SCPD:
 623         ioinst_handle_chsc_scpd(req, res);
 624         break;
 625     case CHSC_SDA:
 626         ioinst_handle_chsc_sda(req, res);
 627         break;
 628     default:
 629         ioinst_handle_chsc_unimplemented(res);
 630         break;
 631     }
 632
 633 out:
 634     s390_cpu_physical_memory_unmap(env, req, map_size, 1);
 635     return ret;
 636 }
 637
 638 int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb)
 639 {
 640     uint64_t addr;
 641     int lowcore;
 642     IOIntCode *int_code;
 643     hwaddr len, orig_len;
 644     int ret;
 645
 646     trace_ioinst("tpi");
 647     addr = decode_basedisp_s(env, ipb);
 648     if (addr & 3) {
 649         program_interrupt(env, PGM_SPECIFICATION, 2);
 650         return -EIO;
 651     }
 652
 653     lowcore = addr ? 0 : 1;
 654     len = lowcore ? 8 /* two words */ : 12 /* three words */;
 655     orig_len = len;
 656     int_code = s390_cpu_physical_memory_map(env, addr, &len, 1);
 657     if (!int_code || (len != orig_len)) {
 658         program_interrupt(env, PGM_SPECIFICATION, 2);
 659         ret = -EIO;
 660         goto out;
 661     }
 662     ret = css_do_tpi(int_code, lowcore);
 663 out:
 664     s390_cpu_physical_memory_unmap(env, int_code, len, 1);
 665     return ret;
 666 }
 667
 668 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
 669 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
 670 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
 671 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
 672
 673 int ioinst_handle_schm(CPUS390XState *env, uint64_t reg1, uint64_t reg2,
 674                        uint32_t ipb)
 675 {
 676     uint8_t mbk;
 677     int update;
 678     int dct;
 679
 680     trace_ioinst("schm");
 681
 682     if (SCHM_REG1_RES(reg1)) {
 683         program_interrupt(env, PGM_OPERAND, 2);
 684         return -EIO;
 685     }
 686
 687     mbk = SCHM_REG1_MBK(reg1);
 688     update = SCHM_REG1_UPD(reg1);
 689     dct = SCHM_REG1_DCT(reg1);
 690
 691     if (update && (reg2 & 0x0000000000000fff)) {
 692         program_interrupt(env, PGM_OPERAND, 2);
 693         return -EIO;
 694     }
 695
 696     css_do_schm(mbk, update, dct, update ? reg2 : 0);
 697
 698     return 0;
 699 }
 700
 701 int ioinst_handle_rsch(CPUS390XState *env, uint64_t reg1)
 702 {
 703     int cssid, ssid, schid, m;
 704     SubchDev *sch;
 705     int ret = -ENODEV;
 706     int cc;
 707
 708     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 709         program_interrupt(env, PGM_OPERAND, 2);
 710         return -EIO;
 711     }
 712     trace_ioinst_sch_id("rsch", cssid, ssid, schid);
 713     sch = css_find_subch(m, cssid, ssid, schid);
 714     if (sch && css_subch_visible(sch)) {
 715         ret = css_do_rsch(sch);
 716     }
 717     switch (ret) {
 718     case -ENODEV:
 719         cc = 3;
 720         break;
 721     case -EINVAL:
 722         cc = 2;
 723         break;
 724     case 0:
 725         cc = 0;
 726         break;
 727     default:
 728         cc = 1;
 729         break;
 730     }
 731
 732     return cc;
 733
 734 }
 735
 736 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
 737 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
 738 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
 739 int ioinst_handle_rchp(CPUS390XState *env, uint64_t reg1)
 740 {
 741     int cc;
 742     uint8_t cssid;
 743     uint8_t chpid;
 744     int ret;
 745
 746     if (RCHP_REG1_RES(reg1)) {
 747         program_interrupt(env, PGM_OPERAND, 2);
 748         return -EIO;
 749     }
 750
 751     cssid = RCHP_REG1_CSSID(reg1);
 752     chpid = RCHP_REG1_CHPID(reg1);
 753
 754     trace_ioinst_chp_id("rchp", cssid, chpid);
 755
 756     ret = css_do_rchp(cssid, chpid);
 757
 758     switch (ret) {
 759     case -ENODEV:
 760         cc = 3;
 761         break;
 762     case -EBUSY:
 763         cc = 2;
 764         break;
 765     case 0:
 766         cc = 0;
 767         break;
 768     default:
 769         /* Invalid channel subsystem. */
 770         program_interrupt(env, PGM_OPERAND, 2);
 771         return -EIO;
 772     }
 773
 774     return cc;
 775 }
 776
 777 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
 778 int ioinst_handle_sal(CPUS390XState *env, uint64_t reg1)
 779 {
 780     /* We do not provide address limit checking, so let's suppress it. */
 781     if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
 782         program_interrupt(env, PGM_OPERAND, 2);
 783         return -EIO;
 784     }
 785     return 0;
 786 }