hw/mips/cps.c

   1 /*
   2  * Coherent Processing System emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/mips/cps.h"
  23 #include "hw/mips/mips.h"
  24 #include "hw/mips/cpudevs.h"
  25 #include "sysemu/kvm.h"
  26
  27 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
  28 {
  29     assert(pin_number < s->num_irq);
  30     return s->gic.irq_state[pin_number].irq;
  31 }
  32
  33 static void mips_cps_init(Object *obj)
  34 {
  35     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  36     MIPSCPSState *s = MIPS_CPS(obj);
  37
  38     /* Cover entire address space as there do not seem to be any
  39      * constraints for the base address of CPC and GIC. */
  40     memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
  41     sysbus_init_mmio(sbd, &s->container);
  42 }
  43
  44 static void main_cpu_reset(void *opaque)
  45 {
  46     MIPSCPU *cpu = opaque;
  47     CPUState *cs = CPU(cpu);
  48
  49     cpu_reset(cs);
  50
  51     /* All VPs are halted on reset. Leave powering up to CPC. */
  52     cs->halted = 1;
  53 }
  54
  55 static bool cpu_mips_itu_supported(CPUMIPSState *env)
  56 {
  57     bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
  58                  (env->CP0_Config3 & (1 << CP0C3_MT));
  59
  60     return is_mt && !kvm_enabled();
  61 }
  62
  63 static void mips_cps_realize(DeviceState *dev, Error **errp)
  64 {
  65     MIPSCPSState *s = MIPS_CPS(dev);
  66     CPUMIPSState *env;
  67     MIPSCPU *cpu;
  68     int i;
  69     Error *err = NULL;
  70     target_ulong gcr_base;
  71     bool itu_present = false;
  72
  73     for (i = 0; i < s->num_vp; i++) {
  74         cpu = cpu_mips_init(s->cpu_model);
  75         if (cpu == NULL) {
  76             error_setg(errp, "%s: CPU initialization failed",  __func__);
  77             return;
  78         }
  79
  80         /* Init internal devices */
  81         cpu_mips_irq_init_cpu(cpu);
  82         cpu_mips_clock_init(cpu);
  83
  84         env = &cpu->env;
  85         if (cpu_mips_itu_supported(env)) {
  86             itu_present = true;
  87             /* Attach ITC Tag to the VP */
  88             env->itc_tag = mips_itu_get_tag_region(&s->itu);
  89         }
  90         qemu_register_reset(main_cpu_reset, cpu);
  91     }
  92
  93     cpu = MIPS_CPU(first_cpu);
  94     env = &cpu->env;
  95
  96     /* Inter-Thread Communication Unit */
  97     if (itu_present) {
  98         object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
  99         qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
 100
 101         object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
 102         object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
 103         object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
 104         if (err != NULL) {
 105             error_propagate(errp, err);
 106             return;
 107         }
 108
 109         memory_region_add_subregion(&s->container, 0,
 110                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
 111     }
 112
 113     /* Cluster Power Controller */
 114     object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
 115     qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
 116
 117     object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
 118     object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
 119     object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
 120     if (err != NULL) {
 121         error_propagate(errp, err);
 122         return;
 123     }
 124
 125     memory_region_add_subregion(&s->container, 0,
 126                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
 127
 128     /* Global Interrupt Controller */
 129     object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
 130     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 131
 132     object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
 133     object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
 134     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 135     if (err != NULL) {
 136         error_propagate(errp, err);
 137         return;
 138     }
 139
 140     memory_region_add_subregion(&s->container, 0,
 141                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
 142
 143     /* Global Configuration Registers */
 144     gcr_base = env->CP0_CMGCRBase << 4;
 145
 146     object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
 147     qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
 148
 149     object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
 150     object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
 151     object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
 152     object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
 153     object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
 154     object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
 155     if (err != NULL) {
 156         error_propagate(errp, err);
 157         return;
 158     }
 159
 160     memory_region_add_subregion(&s->container, gcr_base,
 161                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
 162 }
 163
 164 static Property mips_cps_properties[] = {
 165     DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
 166     DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
 167     DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
 168     DEFINE_PROP_END_OF_LIST()
 169 };
 170
 171 static void mips_cps_class_init(ObjectClass *klass, void *data)
 172 {
 173     DeviceClass *dc = DEVICE_CLASS(klass);
 174
 175     dc->realize = mips_cps_realize;
 176     dc->props = mips_cps_properties;
 177 }
 178
 179 static const TypeInfo mips_cps_info = {
 180     .name = TYPE_MIPS_CPS,
 181     .parent = TYPE_SYS_BUS_DEVICE,
 182     .instance_size = sizeof(MIPSCPSState),
 183     .instance_init = mips_cps_init,
 184     .class_init = mips_cps_class_init,
 185 };
 186
 187 static void mips_cps_register_types(void)
 188 {
 189     type_register_static(&mips_cps_info);
 190 }
 191
 192 type_init(mips_cps_register_types)