hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw/hw.h"
  22 #include "hw/pc.h"
  23 #include "hw/apm.h"
  24 #include "hw/pm_smbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/acpi.h"
  27 #include "sysemu/sysemu.h"
  28 #include "qemu/range.h"
  29 #include "exec/ioport.h"
  30 #include "hw/fw_cfg.h"
  31 #include "exec/address-spaces.h"
  32
  33 //#define DEBUG
  34
  35 #ifdef DEBUG
  36 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  37 #else
  38 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  39 #endif
  40
  41 #define GPE_BASE 0xafe0
  42 #define GPE_LEN 4
  43
  44 #define PCI_HOTPLUG_ADDR 0xae00
  45 #define PCI_HOTPLUG_SIZE 0x000f
  46 #define PCI_UP_BASE 0xae00
  47 #define PCI_DOWN_BASE 0xae04
  48 #define PCI_EJ_BASE 0xae08
  49 #define PCI_RMV_BASE 0xae0c
  50
  51 #define PIIX4_PCI_HOTPLUG_STATUS 2
  52
  53 struct pci_status {
  54     uint32_t up; /* deprecated, maintained for migration compatibility */
  55     uint32_t down;
  56 };
  57
  58 typedef struct PIIX4PMState {
  59     PCIDevice dev;
  60
  61     MemoryRegion io;
  62     MemoryRegion io_gpe;
  63     MemoryRegion io_pci;
  64     ACPIREGS ar;
  65
  66     APMState apm;
  67
  68     PMSMBus smb;
  69     uint32_t smb_io_base;
  70
  71     qemu_irq irq;
  72     qemu_irq smi_irq;
  73     int kvm_enabled;
  74     Notifier machine_ready;
  75     Notifier powerdown_notifier;
  76
  77     /* for pci hotplug */
  78     struct pci_status pci0_status;
  79     uint32_t pci0_hotplug_enable;
  80     uint32_t pci0_slot_device_present;
  81
  82     uint8_t disable_s3;
  83     uint8_t disable_s4;
  84     uint8_t s4_val;
  85 } PIIX4PMState;
  86
  87 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  88                                            PCIBus *bus, PIIX4PMState *s);
  89
  90 #define ACPI_ENABLE 0xf1
  91 #define ACPI_DISABLE 0xf0
  92
  93 static void pm_update_sci(PIIX4PMState *s)
  94 {
  95     int sci_level, pmsts;
  96
  97     pmsts = acpi_pm1_evt_get_sts(&s->ar);
  98     sci_level = (((pmsts & s->ar.pm1.evt.en) &
  99                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 100                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 101                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 102                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
 103         (((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
 104           & PIIX4_PCI_HOTPLUG_STATUS) != 0);
 105
 106     qemu_set_irq(s->irq, sci_level);
 107     /* schedule a timer interruption if needed */
 108     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 109                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 110 }
 111
 112 static void pm_tmr_timer(ACPIREGS *ar)
 113 {
 114     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 115     pm_update_sci(s);
 116 }
 117
 118 static void apm_ctrl_changed(uint32_t val, void *arg)
 119 {
 120     PIIX4PMState *s = arg;
 121
 122     /* ACPI specs 3.0, 4.7.2.5 */
 123     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 124
 125     if (s->dev.config[0x5b] & (1 << 1)) {
 126         if (s->smi_irq) {
 127             qemu_irq_raise(s->smi_irq);
 128         }
 129     }
 130 }
 131
 132 static void pm_io_space_update(PIIX4PMState *s)
 133 {
 134     uint32_t pm_io_base;
 135
 136     pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 137     pm_io_base &= 0xffc0;
 138
 139     memory_region_transaction_begin();
 140     memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
 141     memory_region_set_address(&s->io, pm_io_base);
 142     memory_region_transaction_commit();
 143 }
 144
 145 static void smbus_io_space_update(PIIX4PMState *s)
 146 {
 147     s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90));
 148     s->smb_io_base &= 0xffc0;
 149
 150     memory_region_transaction_begin();
 151     memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1);
 152     memory_region_set_address(&s->smb.io, s->smb_io_base);
 153     memory_region_transaction_commit();
 154 }
 155
 156 static void pm_write_config(PCIDevice *d,
 157                             uint32_t address, uint32_t val, int len)
 158 {
 159     pci_default_write_config(d, address, val, len);
 160     if (range_covers_byte(address, len, 0x80) ||
 161         ranges_overlap(address, len, 0x40, 4)) {
 162         pm_io_space_update((PIIX4PMState *)d);
 163     }
 164     if (range_covers_byte(address, len, 0xd2) ||
 165         ranges_overlap(address, len, 0x90, 4)) {
 166         smbus_io_space_update((PIIX4PMState *)d);
 167     }
 168 }
 169
 170 static void vmstate_pci_status_pre_save(void *opaque)
 171 {
 172     struct pci_status *pci0_status = opaque;
 173     PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
 174
 175     /* We no longer track up, so build a safe value for migrating
 176      * to a version that still does... of course these might get lost
 177      * by an old buggy implementation, but we try. */
 178     pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 179 }
 180
 181 static int vmstate_acpi_post_load(void *opaque, int version_id)
 182 {
 183     PIIX4PMState *s = opaque;
 184
 185     pm_io_space_update(s);
 186     return 0;
 187 }
 188
 189 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 190  {                                                                   \
 191      .name       = (stringify(_field)),                              \
 192      .version_id = 0,                                                \
 193      .info       = &vmstate_info_uint16,                             \
 194      .size       = sizeof(uint16_t),                                 \
 195      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 196      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 197  }
 198
 199 static const VMStateDescription vmstate_gpe = {
 200     .name = "gpe",
 201     .version_id = 1,
 202     .minimum_version_id = 1,
 203     .minimum_version_id_old = 1,
 204     .fields      = (VMStateField []) {
 205         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 206         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 207         VMSTATE_END_OF_LIST()
 208     }
 209 };
 210
 211 static const VMStateDescription vmstate_pci_status = {
 212     .name = "pci_status",
 213     .version_id = 1,
 214     .minimum_version_id = 1,
 215     .minimum_version_id_old = 1,
 216     .pre_save = vmstate_pci_status_pre_save,
 217     .fields      = (VMStateField []) {
 218         VMSTATE_UINT32(up, struct pci_status),
 219         VMSTATE_UINT32(down, struct pci_status),
 220         VMSTATE_END_OF_LIST()
 221     }
 222 };
 223
 224 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 225 {
 226     PIIX4PMState *s = opaque;
 227     int ret, i;
 228     uint16_t temp;
 229
 230     ret = pci_device_load(&s->dev, f);
 231     if (ret < 0) {
 232         return ret;
 233     }
 234     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 235     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 236     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 237
 238     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 239     if (ret) {
 240         return ret;
 241     }
 242
 243     qemu_get_timer(f, s->ar.tmr.timer);
 244     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 245
 246     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 247     for (i = 0; i < 3; i++) {
 248         qemu_get_be16s(f, &temp);
 249     }
 250
 251     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 252     for (i = 0; i < 3; i++) {
 253         qemu_get_be16s(f, &temp);
 254     }
 255
 256     ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1);
 257     return ret;
 258 }
 259
 260 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 261  * To support incoming qemu-kvm 1.2 migration, change version_id
 262  * and minimum_version_id to 2 below (which breaks migration from
 263  * qemu 1.2).
 264  *
 265  */
 266 static const VMStateDescription vmstate_acpi = {
 267     .name = "piix4_pm",
 268     .version_id = 3,
 269     .minimum_version_id = 3,
 270     .minimum_version_id_old = 1,
 271     .load_state_old = acpi_load_old,
 272     .post_load = vmstate_acpi_post_load,
 273     .fields      = (VMStateField []) {
 274         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 275         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 276         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 277         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 278         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 279         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 280         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 281         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 282         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 283                        struct pci_status),
 284         VMSTATE_END_OF_LIST()
 285     }
 286 };
 287
 288 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
 289 {
 290     BusChild *kid, *next;
 291     BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
 292     int slot = ffs(slots) - 1;
 293     bool slot_free = true;
 294
 295     /* Mark request as complete */
 296     s->pci0_status.down &= ~(1U << slot);
 297
 298     QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 299         DeviceState *qdev = kid->child;
 300         PCIDevice *dev = PCI_DEVICE(qdev);
 301         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 302         if (PCI_SLOT(dev->devfn) == slot) {
 303             if (pc->no_hotplug) {
 304                 slot_free = false;
 305             } else {
 306                 qdev_free(qdev);
 307             }
 308         }
 309     }
 310     if (slot_free) {
 311         s->pci0_slot_device_present &= ~(1U << slot);
 312     }
 313 }
 314
 315 static void piix4_update_hotplug(PIIX4PMState *s)
 316 {
 317     PCIDevice *dev = &s->dev;
 318     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 319     BusChild *kid, *next;
 320
 321     /* Execute any pending removes during reset */
 322     while (s->pci0_status.down) {
 323         acpi_piix_eject_slot(s, s->pci0_status.down);
 324     }
 325
 326     s->pci0_hotplug_enable = ~0;
 327     s->pci0_slot_device_present = 0;
 328
 329     QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 330         DeviceState *qdev = kid->child;
 331         PCIDevice *pdev = PCI_DEVICE(qdev);
 332         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
 333         int slot = PCI_SLOT(pdev->devfn);
 334
 335         if (pc->no_hotplug) {
 336             s->pci0_hotplug_enable &= ~(1U << slot);
 337         }
 338
 339         s->pci0_slot_device_present |= (1U << slot);
 340     }
 341 }
 342
 343 static void piix4_reset(void *opaque)
 344 {
 345     PIIX4PMState *s = opaque;
 346     uint8_t *pci_conf = s->dev.config;
 347
 348     pci_conf[0x58] = 0;
 349     pci_conf[0x59] = 0;
 350     pci_conf[0x5a] = 0;
 351     pci_conf[0x5b] = 0;
 352
 353     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 354     pci_conf[0x80] = 0;
 355
 356     if (s->kvm_enabled) {
 357         /* Mark SMM as already inited (until KVM supports SMM). */
 358         pci_conf[0x5B] = 0x02;
 359     }
 360     piix4_update_hotplug(s);
 361 }
 362
 363 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 364 {
 365     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 366
 367     assert(s != NULL);
 368     acpi_pm1_evt_power_down(&s->ar);
 369 }
 370
 371 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 372 {
 373     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 374     uint8_t *pci_conf;
 375
 376     pci_conf = s->dev.config;
 377     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 378     pci_conf[0x63] = 0x60;
 379     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 380         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 381
 382 }
 383
 384 static int piix4_pm_initfn(PCIDevice *dev)
 385 {
 386     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 387     uint8_t *pci_conf;
 388
 389     pci_conf = s->dev.config;
 390     pci_conf[0x06] = 0x80;
 391     pci_conf[0x07] = 0x02;
 392     pci_conf[0x09] = 0x00;
 393     pci_conf[0x3d] = 0x01; // interrupt pin 1
 394
 395     /* APM */
 396     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 397
 398     if (s->kvm_enabled) {
 399         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 400          * support SMM mode. */
 401         pci_conf[0x5B] = 0x02;
 402     }
 403
 404     /* XXX: which specification is used ? The i82731AB has different
 405        mappings */
 406     pci_conf[0x90] = s->smb_io_base | 1;
 407     pci_conf[0x91] = s->smb_io_base >> 8;
 408     pci_conf[0xd2] = 0x09;
 409     pm_smbus_init(&s->dev.qdev, &s->smb);
 410     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 411     memory_region_add_subregion(pci_address_space_io(dev),
 412                                 s->smb_io_base, &s->smb.io);
 413
 414     memory_region_init(&s->io, "piix4-pm", 64);
 415     memory_region_set_enabled(&s->io, false);
 416     memory_region_add_subregion(pci_address_space_io(dev),
 417                                 0, &s->io);
 418
 419     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 420     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 421     acpi_pm1_cnt_init(&s->ar, &s->io);
 422     acpi_gpe_init(&s->ar, GPE_LEN);
 423
 424     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 425     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 426
 427     s->machine_ready.notify = piix4_pm_machine_ready;
 428     qemu_add_machine_init_done_notifier(&s->machine_ready);
 429     qemu_register_reset(piix4_reset, s);
 430
 431     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 432
 433     return 0;
 434 }
 435
 436 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 437                        qemu_irq sci_irq, qemu_irq smi_irq,
 438                        int kvm_enabled, void *fw_cfg)
 439 {
 440     PCIDevice *dev;
 441     PIIX4PMState *s;
 442
 443     dev = pci_create(bus, devfn, "PIIX4_PM");
 444     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 445
 446     s = DO_UPCAST(PIIX4PMState, dev, dev);
 447     s->irq = sci_irq;
 448     s->smi_irq = smi_irq;
 449     s->kvm_enabled = kvm_enabled;
 450
 451     qdev_init_nofail(&dev->qdev);
 452
 453     if (fw_cfg) {
 454         uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 455         suspend[3] = 1 | ((!s->disable_s3) << 7);
 456         suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 457
 458         fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 459     }
 460
 461     return s->smb.smbus;
 462 }
 463
 464 static Property piix4_pm_properties[] = {
 465     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 466     DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
 467     DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
 468     DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
 469     DEFINE_PROP_END_OF_LIST(),
 470 };
 471
 472 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 473 {
 474     DeviceClass *dc = DEVICE_CLASS(klass);
 475     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 476
 477     k->no_hotplug = 1;
 478     k->init = piix4_pm_initfn;
 479     k->config_write = pm_write_config;
 480     k->vendor_id = PCI_VENDOR_ID_INTEL;
 481     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 482     k->revision = 0x03;
 483     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 484     dc->desc = "PM";
 485     dc->no_user = 1;
 486     dc->vmsd = &vmstate_acpi;
 487     dc->props = piix4_pm_properties;
 488 }
 489
 490 static const TypeInfo piix4_pm_info = {
 491     .name          = "PIIX4_PM",
 492     .parent        = TYPE_PCI_DEVICE,
 493     .instance_size = sizeof(PIIX4PMState),
 494     .class_init    = piix4_pm_class_init,
 495 };
 496
 497 static void piix4_pm_register_types(void)
 498 {
 499     type_register_static(&piix4_pm_info);
 500 }
 501
 502 type_init(piix4_pm_register_types)
 503
 504 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 505 {
 506     PIIX4PMState *s = opaque;
 507     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 508
 509     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 510     return val;
 511 }
 512
 513 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 514                        unsigned width)
 515 {
 516     PIIX4PMState *s = opaque;
 517
 518     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 519     pm_update_sci(s);
 520
 521     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 522 }
 523
 524 static const MemoryRegionOps piix4_gpe_ops = {
 525     .read = gpe_readb,
 526     .write = gpe_writeb,
 527     .valid.min_access_size = 1,
 528     .valid.max_access_size = 4,
 529     .impl.min_access_size = 1,
 530     .impl.max_access_size = 1,
 531     .endianness = DEVICE_LITTLE_ENDIAN,
 532 };
 533
 534 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
 535 {
 536     PIIX4PMState *s = opaque;
 537     uint32_t val = 0;
 538
 539     switch (addr) {
 540     case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
 541         /* Manufacture an "up" value to cause a device check on any hotplug
 542          * slot with a device.  Extra device checks are harmless. */
 543         val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 544         PIIX4_DPRINTF("pci_up_read %x\n", val);
 545         break;
 546     case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
 547         val = s->pci0_status.down;
 548         PIIX4_DPRINTF("pci_down_read %x\n", val);
 549         break;
 550     case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
 551         /* No feature defined yet */
 552         PIIX4_DPRINTF("pci_features_read %x\n", val);
 553         break;
 554     case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
 555         val = s->pci0_hotplug_enable;
 556         break;
 557     default:
 558         break;
 559     }
 560
 561     return val;
 562 }
 563
 564 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
 565                       unsigned int size)
 566 {
 567     switch (addr) {
 568     case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
 569         acpi_piix_eject_slot(opaque, (uint32_t)data);
 570         PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n",
 571                       addr, data);
 572         break;
 573     default:
 574         break;
 575     }
 576 }
 577
 578 static const MemoryRegionOps piix4_pci_ops = {
 579     .read = pci_read,
 580     .write = pci_write,
 581     .endianness = DEVICE_LITTLE_ENDIAN,
 582     .valid = {
 583         .min_access_size = 4,
 584         .max_access_size = 4,
 585     },
 586 };
 587
 588 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 589                                 PCIHotplugState state);
 590
 591 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 592                                            PCIBus *bus, PIIX4PMState *s)
 593 {
 594     memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0",
 595                           GPE_LEN);
 596     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 597
 598     memory_region_init_io(&s->io_pci, &piix4_pci_ops, s, "apci-pci-hotplug",
 599                           PCI_HOTPLUG_SIZE);
 600     memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
 601                                 &s->io_pci);
 602     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 603 }
 604
 605 static void enable_device(PIIX4PMState *s, int slot)
 606 {
 607     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 608     s->pci0_slot_device_present |= (1U << slot);
 609 }
 610
 611 static void disable_device(PIIX4PMState *s, int slot)
 612 {
 613     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 614     s->pci0_status.down |= (1U << slot);
 615 }
 616
 617 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 618                                 PCIHotplugState state)
 619 {
 620     int slot = PCI_SLOT(dev->devfn);
 621     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 622                                 PCI_DEVICE(qdev));
 623
 624     /* Don't send event when device is enabled during qemu machine creation:
 625      * it is present on boot, no hotplug event is necessary. We do send an
 626      * event when the device is disabled later. */
 627     if (state == PCI_COLDPLUG_ENABLED) {
 628         s->pci0_slot_device_present |= (1U << slot);
 629         return 0;
 630     }
 631
 632     if (state == PCI_HOTPLUG_ENABLED) {
 633         enable_device(s, slot);
 634     } else {
 635         disable_device(s, slot);
 636     }
 637
 638     pm_update_sci(s);
 639
 640     return 0;
 641 }