memory: avoid unnecessary object_ref/unref
[qemu/ar7.git] / target-i386 / cpu.h
blob595891e78d86b74bf0ff2a7bde567842bc534a42
1 /*
2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef CPU_I386_H
20 #define CPU_I386_H
22 #include "config.h"
23 #include "qemu-common.h"
24 #include "standard-headers/asm-x86/hyperv.h"
26 #ifdef TARGET_X86_64
27 #define TARGET_LONG_BITS 64
28 #else
29 #define TARGET_LONG_BITS 32
30 #endif
32 /* Maximum instruction code size */
33 #define TARGET_MAX_INSN_SIZE 16
35 /* support for self modifying code even if the modified instruction is
36 close to the modifying instruction */
37 #define TARGET_HAS_PRECISE_SMC
39 #ifdef TARGET_X86_64
40 #define I386_ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
42 #else
43 #define I386_ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
45 #endif
47 #define CPUArchState struct CPUX86State
49 #include "exec/cpu-defs.h"
51 #include "fpu/softfloat.h"
53 #define R_EAX 0
54 #define R_ECX 1
55 #define R_EDX 2
56 #define R_EBX 3
57 #define R_ESP 4
58 #define R_EBP 5
59 #define R_ESI 6
60 #define R_EDI 7
62 #define R_AL 0
63 #define R_CL 1
64 #define R_DL 2
65 #define R_BL 3
66 #define R_AH 4
67 #define R_CH 5
68 #define R_DH 6
69 #define R_BH 7
71 #define R_ES 0
72 #define R_CS 1
73 #define R_SS 2
74 #define R_DS 3
75 #define R_FS 4
76 #define R_GS 5
78 /* segment descriptor fields */
79 #define DESC_G_MASK (1 << 23)
80 #define DESC_B_SHIFT 22
81 #define DESC_B_MASK (1 << DESC_B_SHIFT)
82 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
83 #define DESC_L_MASK (1 << DESC_L_SHIFT)
84 #define DESC_AVL_MASK (1 << 20)
85 #define DESC_P_MASK (1 << 15)
86 #define DESC_DPL_SHIFT 13
87 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
88 #define DESC_S_MASK (1 << 12)
89 #define DESC_TYPE_SHIFT 8
90 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
91 #define DESC_A_MASK (1 << 8)
93 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
94 #define DESC_C_MASK (1 << 10) /* code: conforming */
95 #define DESC_R_MASK (1 << 9) /* code: readable */
97 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
98 #define DESC_W_MASK (1 << 9) /* data: writable */
100 #define DESC_TSS_BUSY_MASK (1 << 9)
102 /* eflags masks */
103 #define CC_C 0x0001
104 #define CC_P 0x0004
105 #define CC_A 0x0010
106 #define CC_Z 0x0040
107 #define CC_S 0x0080
108 #define CC_O 0x0800
110 #define TF_SHIFT 8
111 #define IOPL_SHIFT 12
112 #define VM_SHIFT 17
114 #define TF_MASK 0x00000100
115 #define IF_MASK 0x00000200
116 #define DF_MASK 0x00000400
117 #define IOPL_MASK 0x00003000
118 #define NT_MASK 0x00004000
119 #define RF_MASK 0x00010000
120 #define VM_MASK 0x00020000
121 #define AC_MASK 0x00040000
122 #define VIF_MASK 0x00080000
123 #define VIP_MASK 0x00100000
124 #define ID_MASK 0x00200000
126 /* hidden flags - used internally by qemu to represent additional cpu
127 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
128 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
129 positions to ease oring with eflags. */
130 /* current cpl */
131 #define HF_CPL_SHIFT 0
132 /* true if soft mmu is being used */
133 #define HF_SOFTMMU_SHIFT 2
134 /* true if hardware interrupts must be disabled for next instruction */
135 #define HF_INHIBIT_IRQ_SHIFT 3
136 /* 16 or 32 segments */
137 #define HF_CS32_SHIFT 4
138 #define HF_SS32_SHIFT 5
139 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
140 #define HF_ADDSEG_SHIFT 6
141 /* copy of CR0.PE (protected mode) */
142 #define HF_PE_SHIFT 7
143 #define HF_TF_SHIFT 8 /* must be same as eflags */
144 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
145 #define HF_EM_SHIFT 10
146 #define HF_TS_SHIFT 11
147 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
148 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
149 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
150 #define HF_RF_SHIFT 16 /* must be same as eflags */
151 #define HF_VM_SHIFT 17 /* must be same as eflags */
152 #define HF_AC_SHIFT 18 /* must be same as eflags */
153 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
154 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
155 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
156 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
157 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
158 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
160 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
161 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
162 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
163 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
164 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
165 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
166 #define HF_PE_MASK (1 << HF_PE_SHIFT)
167 #define HF_TF_MASK (1 << HF_TF_SHIFT)
168 #define HF_MP_MASK (1 << HF_MP_SHIFT)
169 #define HF_EM_MASK (1 << HF_EM_SHIFT)
170 #define HF_TS_MASK (1 << HF_TS_SHIFT)
171 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
172 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
173 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
174 #define HF_RF_MASK (1 << HF_RF_SHIFT)
175 #define HF_VM_MASK (1 << HF_VM_SHIFT)
176 #define HF_AC_MASK (1 << HF_AC_SHIFT)
177 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
178 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
179 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
180 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
181 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
182 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
184 /* hflags2 */
186 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
187 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
188 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
189 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
190 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
192 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
193 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
194 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
195 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
196 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
198 #define CR0_PE_SHIFT 0
199 #define CR0_MP_SHIFT 1
201 #define CR0_PE_MASK (1U << 0)
202 #define CR0_MP_MASK (1U << 1)
203 #define CR0_EM_MASK (1U << 2)
204 #define CR0_TS_MASK (1U << 3)
205 #define CR0_ET_MASK (1U << 4)
206 #define CR0_NE_MASK (1U << 5)
207 #define CR0_WP_MASK (1U << 16)
208 #define CR0_AM_MASK (1U << 18)
209 #define CR0_PG_MASK (1U << 31)
211 #define CR4_VME_MASK (1U << 0)
212 #define CR4_PVI_MASK (1U << 1)
213 #define CR4_TSD_MASK (1U << 2)
214 #define CR4_DE_MASK (1U << 3)
215 #define CR4_PSE_MASK (1U << 4)
216 #define CR4_PAE_MASK (1U << 5)
217 #define CR4_MCE_MASK (1U << 6)
218 #define CR4_PGE_MASK (1U << 7)
219 #define CR4_PCE_MASK (1U << 8)
220 #define CR4_OSFXSR_SHIFT 9
221 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
222 #define CR4_OSXMMEXCPT_MASK (1U << 10)
223 #define CR4_VMXE_MASK (1U << 13)
224 #define CR4_SMXE_MASK (1U << 14)
225 #define CR4_FSGSBASE_MASK (1U << 16)
226 #define CR4_PCIDE_MASK (1U << 17)
227 #define CR4_OSXSAVE_MASK (1U << 18)
228 #define CR4_SMEP_MASK (1U << 20)
229 #define CR4_SMAP_MASK (1U << 21)
231 #define DR6_BD (1 << 13)
232 #define DR6_BS (1 << 14)
233 #define DR6_BT (1 << 15)
234 #define DR6_FIXED_1 0xffff0ff0
236 #define DR7_GD (1 << 13)
237 #define DR7_TYPE_SHIFT 16
238 #define DR7_LEN_SHIFT 18
239 #define DR7_FIXED_1 0x00000400
240 #define DR7_GLOBAL_BP_MASK 0xaa
241 #define DR7_LOCAL_BP_MASK 0x55
242 #define DR7_MAX_BP 4
243 #define DR7_TYPE_BP_INST 0x0
244 #define DR7_TYPE_DATA_WR 0x1
245 #define DR7_TYPE_IO_RW 0x2
246 #define DR7_TYPE_DATA_RW 0x3
248 #define PG_PRESENT_BIT 0
249 #define PG_RW_BIT 1
250 #define PG_USER_BIT 2
251 #define PG_PWT_BIT 3
252 #define PG_PCD_BIT 4
253 #define PG_ACCESSED_BIT 5
254 #define PG_DIRTY_BIT 6
255 #define PG_PSE_BIT 7
256 #define PG_GLOBAL_BIT 8
257 #define PG_PSE_PAT_BIT 12
258 #define PG_NX_BIT 63
260 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
261 #define PG_RW_MASK (1 << PG_RW_BIT)
262 #define PG_USER_MASK (1 << PG_USER_BIT)
263 #define PG_PWT_MASK (1 << PG_PWT_BIT)
264 #define PG_PCD_MASK (1 << PG_PCD_BIT)
265 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
266 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
267 #define PG_PSE_MASK (1 << PG_PSE_BIT)
268 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
269 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
270 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
271 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
272 #define PG_HI_USER_MASK 0x7ff0000000000000LL
273 #define PG_NX_MASK (1LL << PG_NX_BIT)
275 #define PG_ERROR_W_BIT 1
277 #define PG_ERROR_P_MASK 0x01
278 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
279 #define PG_ERROR_U_MASK 0x04
280 #define PG_ERROR_RSVD_MASK 0x08
281 #define PG_ERROR_I_D_MASK 0x10
283 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
284 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
286 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
287 #define MCE_BANKS_DEF 10
289 #define MCG_CAP_BANKS_MASK 0xff
291 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
292 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
293 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
295 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
296 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
297 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
298 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
299 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
300 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
301 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
302 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
303 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
305 /* MISC register defines */
306 #define MCM_ADDR_SEGOFF 0 /* segment offset */
307 #define MCM_ADDR_LINEAR 1 /* linear address */
308 #define MCM_ADDR_PHYS 2 /* physical address */
309 #define MCM_ADDR_MEM 3 /* memory address */
310 #define MCM_ADDR_GENERIC 7 /* generic */
312 #define MSR_IA32_TSC 0x10
313 #define MSR_IA32_APICBASE 0x1b
314 #define MSR_IA32_APICBASE_BSP (1<<8)
315 #define MSR_IA32_APICBASE_ENABLE (1<<11)
316 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
317 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
318 #define MSR_TSC_ADJUST 0x0000003b
319 #define MSR_IA32_TSCDEADLINE 0x6e0
321 #define MSR_P6_PERFCTR0 0xc1
323 #define MSR_IA32_SMBASE 0x9e
324 #define MSR_MTRRcap 0xfe
325 #define MSR_MTRRcap_VCNT 8
326 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
327 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
329 #define MSR_IA32_SYSENTER_CS 0x174
330 #define MSR_IA32_SYSENTER_ESP 0x175
331 #define MSR_IA32_SYSENTER_EIP 0x176
333 #define MSR_MCG_CAP 0x179
334 #define MSR_MCG_STATUS 0x17a
335 #define MSR_MCG_CTL 0x17b
337 #define MSR_P6_EVNTSEL0 0x186
339 #define MSR_IA32_PERF_STATUS 0x198
341 #define MSR_IA32_MISC_ENABLE 0x1a0
342 /* Indicates good rep/movs microcode on some processors: */
343 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
345 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
346 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
348 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
350 #define MSR_MTRRfix64K_00000 0x250
351 #define MSR_MTRRfix16K_80000 0x258
352 #define MSR_MTRRfix16K_A0000 0x259
353 #define MSR_MTRRfix4K_C0000 0x268
354 #define MSR_MTRRfix4K_C8000 0x269
355 #define MSR_MTRRfix4K_D0000 0x26a
356 #define MSR_MTRRfix4K_D8000 0x26b
357 #define MSR_MTRRfix4K_E0000 0x26c
358 #define MSR_MTRRfix4K_E8000 0x26d
359 #define MSR_MTRRfix4K_F0000 0x26e
360 #define MSR_MTRRfix4K_F8000 0x26f
362 #define MSR_PAT 0x277
364 #define MSR_MTRRdefType 0x2ff
366 #define MSR_CORE_PERF_FIXED_CTR0 0x309
367 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
368 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
369 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
370 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
371 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
372 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
374 #define MSR_MC0_CTL 0x400
375 #define MSR_MC0_STATUS 0x401
376 #define MSR_MC0_ADDR 0x402
377 #define MSR_MC0_MISC 0x403
379 #define MSR_EFER 0xc0000080
381 #define MSR_EFER_SCE (1 << 0)
382 #define MSR_EFER_LME (1 << 8)
383 #define MSR_EFER_LMA (1 << 10)
384 #define MSR_EFER_NXE (1 << 11)
385 #define MSR_EFER_SVME (1 << 12)
386 #define MSR_EFER_FFXSR (1 << 14)
388 #define MSR_STAR 0xc0000081
389 #define MSR_LSTAR 0xc0000082
390 #define MSR_CSTAR 0xc0000083
391 #define MSR_FMASK 0xc0000084
392 #define MSR_FSBASE 0xc0000100
393 #define MSR_GSBASE 0xc0000101
394 #define MSR_KERNELGSBASE 0xc0000102
395 #define MSR_TSC_AUX 0xc0000103
397 #define MSR_VM_HSAVE_PA 0xc0010117
399 #define MSR_IA32_BNDCFGS 0x00000d90
400 #define MSR_IA32_XSS 0x00000da0
402 #define XSTATE_FP (1ULL << 0)
403 #define XSTATE_SSE (1ULL << 1)
404 #define XSTATE_YMM (1ULL << 2)
405 #define XSTATE_BNDREGS (1ULL << 3)
406 #define XSTATE_BNDCSR (1ULL << 4)
407 #define XSTATE_OPMASK (1ULL << 5)
408 #define XSTATE_ZMM_Hi256 (1ULL << 6)
409 #define XSTATE_Hi16_ZMM (1ULL << 7)
412 /* CPUID feature words */
413 typedef enum FeatureWord {
414 FEAT_1_EDX, /* CPUID[1].EDX */
415 FEAT_1_ECX, /* CPUID[1].ECX */
416 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
417 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
418 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
419 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
420 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
421 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
422 FEAT_SVM, /* CPUID[8000_000A].EDX */
423 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
424 FEAT_6_EAX, /* CPUID[6].EAX */
425 FEATURE_WORDS,
426 } FeatureWord;
428 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
430 /* cpuid_features bits */
431 #define CPUID_FP87 (1U << 0)
432 #define CPUID_VME (1U << 1)
433 #define CPUID_DE (1U << 2)
434 #define CPUID_PSE (1U << 3)
435 #define CPUID_TSC (1U << 4)
436 #define CPUID_MSR (1U << 5)
437 #define CPUID_PAE (1U << 6)
438 #define CPUID_MCE (1U << 7)
439 #define CPUID_CX8 (1U << 8)
440 #define CPUID_APIC (1U << 9)
441 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
442 #define CPUID_MTRR (1U << 12)
443 #define CPUID_PGE (1U << 13)
444 #define CPUID_MCA (1U << 14)
445 #define CPUID_CMOV (1U << 15)
446 #define CPUID_PAT (1U << 16)
447 #define CPUID_PSE36 (1U << 17)
448 #define CPUID_PN (1U << 18)
449 #define CPUID_CLFLUSH (1U << 19)
450 #define CPUID_DTS (1U << 21)
451 #define CPUID_ACPI (1U << 22)
452 #define CPUID_MMX (1U << 23)
453 #define CPUID_FXSR (1U << 24)
454 #define CPUID_SSE (1U << 25)
455 #define CPUID_SSE2 (1U << 26)
456 #define CPUID_SS (1U << 27)
457 #define CPUID_HT (1U << 28)
458 #define CPUID_TM (1U << 29)
459 #define CPUID_IA64 (1U << 30)
460 #define CPUID_PBE (1U << 31)
462 #define CPUID_EXT_SSE3 (1U << 0)
463 #define CPUID_EXT_PCLMULQDQ (1U << 1)
464 #define CPUID_EXT_DTES64 (1U << 2)
465 #define CPUID_EXT_MONITOR (1U << 3)
466 #define CPUID_EXT_DSCPL (1U << 4)
467 #define CPUID_EXT_VMX (1U << 5)
468 #define CPUID_EXT_SMX (1U << 6)
469 #define CPUID_EXT_EST (1U << 7)
470 #define CPUID_EXT_TM2 (1U << 8)
471 #define CPUID_EXT_SSSE3 (1U << 9)
472 #define CPUID_EXT_CID (1U << 10)
473 #define CPUID_EXT_FMA (1U << 12)
474 #define CPUID_EXT_CX16 (1U << 13)
475 #define CPUID_EXT_XTPR (1U << 14)
476 #define CPUID_EXT_PDCM (1U << 15)
477 #define CPUID_EXT_PCID (1U << 17)
478 #define CPUID_EXT_DCA (1U << 18)
479 #define CPUID_EXT_SSE41 (1U << 19)
480 #define CPUID_EXT_SSE42 (1U << 20)
481 #define CPUID_EXT_X2APIC (1U << 21)
482 #define CPUID_EXT_MOVBE (1U << 22)
483 #define CPUID_EXT_POPCNT (1U << 23)
484 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
485 #define CPUID_EXT_AES (1U << 25)
486 #define CPUID_EXT_XSAVE (1U << 26)
487 #define CPUID_EXT_OSXSAVE (1U << 27)
488 #define CPUID_EXT_AVX (1U << 28)
489 #define CPUID_EXT_F16C (1U << 29)
490 #define CPUID_EXT_RDRAND (1U << 30)
491 #define CPUID_EXT_HYPERVISOR (1U << 31)
493 #define CPUID_EXT2_FPU (1U << 0)
494 #define CPUID_EXT2_VME (1U << 1)
495 #define CPUID_EXT2_DE (1U << 2)
496 #define CPUID_EXT2_PSE (1U << 3)
497 #define CPUID_EXT2_TSC (1U << 4)
498 #define CPUID_EXT2_MSR (1U << 5)
499 #define CPUID_EXT2_PAE (1U << 6)
500 #define CPUID_EXT2_MCE (1U << 7)
501 #define CPUID_EXT2_CX8 (1U << 8)
502 #define CPUID_EXT2_APIC (1U << 9)
503 #define CPUID_EXT2_SYSCALL (1U << 11)
504 #define CPUID_EXT2_MTRR (1U << 12)
505 #define CPUID_EXT2_PGE (1U << 13)
506 #define CPUID_EXT2_MCA (1U << 14)
507 #define CPUID_EXT2_CMOV (1U << 15)
508 #define CPUID_EXT2_PAT (1U << 16)
509 #define CPUID_EXT2_PSE36 (1U << 17)
510 #define CPUID_EXT2_MP (1U << 19)
511 #define CPUID_EXT2_NX (1U << 20)
512 #define CPUID_EXT2_MMXEXT (1U << 22)
513 #define CPUID_EXT2_MMX (1U << 23)
514 #define CPUID_EXT2_FXSR (1U << 24)
515 #define CPUID_EXT2_FFXSR (1U << 25)
516 #define CPUID_EXT2_PDPE1GB (1U << 26)
517 #define CPUID_EXT2_RDTSCP (1U << 27)
518 #define CPUID_EXT2_LM (1U << 29)
519 #define CPUID_EXT2_3DNOWEXT (1U << 30)
520 #define CPUID_EXT2_3DNOW (1U << 31)
522 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
523 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
524 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
525 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
526 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
527 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
528 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
529 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
530 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
531 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
533 #define CPUID_EXT3_LAHF_LM (1U << 0)
534 #define CPUID_EXT3_CMP_LEG (1U << 1)
535 #define CPUID_EXT3_SVM (1U << 2)
536 #define CPUID_EXT3_EXTAPIC (1U << 3)
537 #define CPUID_EXT3_CR8LEG (1U << 4)
538 #define CPUID_EXT3_ABM (1U << 5)
539 #define CPUID_EXT3_SSE4A (1U << 6)
540 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
541 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
542 #define CPUID_EXT3_OSVW (1U << 9)
543 #define CPUID_EXT3_IBS (1U << 10)
544 #define CPUID_EXT3_XOP (1U << 11)
545 #define CPUID_EXT3_SKINIT (1U << 12)
546 #define CPUID_EXT3_WDT (1U << 13)
547 #define CPUID_EXT3_LWP (1U << 15)
548 #define CPUID_EXT3_FMA4 (1U << 16)
549 #define CPUID_EXT3_TCE (1U << 17)
550 #define CPUID_EXT3_NODEID (1U << 19)
551 #define CPUID_EXT3_TBM (1U << 21)
552 #define CPUID_EXT3_TOPOEXT (1U << 22)
553 #define CPUID_EXT3_PERFCORE (1U << 23)
554 #define CPUID_EXT3_PERFNB (1U << 24)
556 #define CPUID_SVM_NPT (1U << 0)
557 #define CPUID_SVM_LBRV (1U << 1)
558 #define CPUID_SVM_SVMLOCK (1U << 2)
559 #define CPUID_SVM_NRIPSAVE (1U << 3)
560 #define CPUID_SVM_TSCSCALE (1U << 4)
561 #define CPUID_SVM_VMCBCLEAN (1U << 5)
562 #define CPUID_SVM_FLUSHASID (1U << 6)
563 #define CPUID_SVM_DECODEASSIST (1U << 7)
564 #define CPUID_SVM_PAUSEFILTER (1U << 10)
565 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
567 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
568 #define CPUID_7_0_EBX_BMI1 (1U << 3)
569 #define CPUID_7_0_EBX_HLE (1U << 4)
570 #define CPUID_7_0_EBX_AVX2 (1U << 5)
571 #define CPUID_7_0_EBX_SMEP (1U << 7)
572 #define CPUID_7_0_EBX_BMI2 (1U << 8)
573 #define CPUID_7_0_EBX_ERMS (1U << 9)
574 #define CPUID_7_0_EBX_INVPCID (1U << 10)
575 #define CPUID_7_0_EBX_RTM (1U << 11)
576 #define CPUID_7_0_EBX_MPX (1U << 14)
577 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
578 #define CPUID_7_0_EBX_RDSEED (1U << 18)
579 #define CPUID_7_0_EBX_ADX (1U << 19)
580 #define CPUID_7_0_EBX_SMAP (1U << 20)
581 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
582 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
583 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
584 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
585 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
586 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
588 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
589 #define CPUID_XSAVE_XSAVEC (1U << 1)
590 #define CPUID_XSAVE_XGETBV1 (1U << 2)
591 #define CPUID_XSAVE_XSAVES (1U << 3)
593 #define CPUID_6_EAX_ARAT (1U << 2)
595 /* CPUID[0x80000007].EDX flags: */
596 #define CPUID_APM_INVTSC (1U << 8)
598 #define CPUID_VENDOR_SZ 12
600 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
601 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
602 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
603 #define CPUID_VENDOR_INTEL "GenuineIntel"
605 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
606 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
607 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
608 #define CPUID_VENDOR_AMD "AuthenticAMD"
610 #define CPUID_VENDOR_VIA "CentaurHauls"
612 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
613 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
615 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
616 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
617 #endif
619 #define EXCP00_DIVZ 0
620 #define EXCP01_DB 1
621 #define EXCP02_NMI 2
622 #define EXCP03_INT3 3
623 #define EXCP04_INTO 4
624 #define EXCP05_BOUND 5
625 #define EXCP06_ILLOP 6
626 #define EXCP07_PREX 7
627 #define EXCP08_DBLE 8
628 #define EXCP09_XERR 9
629 #define EXCP0A_TSS 10
630 #define EXCP0B_NOSEG 11
631 #define EXCP0C_STACK 12
632 #define EXCP0D_GPF 13
633 #define EXCP0E_PAGE 14
634 #define EXCP10_COPR 16
635 #define EXCP11_ALGN 17
636 #define EXCP12_MCHK 18
638 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
639 for syscall instruction */
641 /* i386-specific interrupt pending bits. */
642 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
643 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
644 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
645 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
646 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
647 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
648 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
650 /* Use a clearer name for this. */
651 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
653 typedef enum {
654 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
655 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
657 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
658 CC_OP_MULW,
659 CC_OP_MULL,
660 CC_OP_MULQ,
662 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
663 CC_OP_ADDW,
664 CC_OP_ADDL,
665 CC_OP_ADDQ,
667 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
668 CC_OP_ADCW,
669 CC_OP_ADCL,
670 CC_OP_ADCQ,
672 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
673 CC_OP_SUBW,
674 CC_OP_SUBL,
675 CC_OP_SUBQ,
677 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
678 CC_OP_SBBW,
679 CC_OP_SBBL,
680 CC_OP_SBBQ,
682 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
683 CC_OP_LOGICW,
684 CC_OP_LOGICL,
685 CC_OP_LOGICQ,
687 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
688 CC_OP_INCW,
689 CC_OP_INCL,
690 CC_OP_INCQ,
692 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
693 CC_OP_DECW,
694 CC_OP_DECL,
695 CC_OP_DECQ,
697 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
698 CC_OP_SHLW,
699 CC_OP_SHLL,
700 CC_OP_SHLQ,
702 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
703 CC_OP_SARW,
704 CC_OP_SARL,
705 CC_OP_SARQ,
707 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
708 CC_OP_BMILGW,
709 CC_OP_BMILGL,
710 CC_OP_BMILGQ,
712 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
713 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
714 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
716 CC_OP_CLR, /* Z set, all other flags clear. */
718 CC_OP_NB,
719 } CCOp;
721 typedef struct SegmentCache {
722 uint32_t selector;
723 target_ulong base;
724 uint32_t limit;
725 uint32_t flags;
726 } SegmentCache;
728 typedef union {
729 uint8_t _b[64];
730 uint16_t _w[32];
731 uint32_t _l[16];
732 uint64_t _q[8];
733 float32 _s[16];
734 float64 _d[8];
735 } XMMReg; /* really zmm */
737 typedef union {
738 uint8_t _b[8];
739 uint16_t _w[4];
740 uint32_t _l[2];
741 float32 _s[2];
742 uint64_t q;
743 } MMXReg;
745 typedef struct BNDReg {
746 uint64_t lb;
747 uint64_t ub;
748 } BNDReg;
750 typedef struct BNDCSReg {
751 uint64_t cfgu;
752 uint64_t sts;
753 } BNDCSReg;
755 #ifdef HOST_WORDS_BIGENDIAN
756 #define XMM_B(n) _b[63 - (n)]
757 #define XMM_W(n) _w[31 - (n)]
758 #define XMM_L(n) _l[15 - (n)]
759 #define XMM_S(n) _s[15 - (n)]
760 #define XMM_Q(n) _q[7 - (n)]
761 #define XMM_D(n) _d[7 - (n)]
763 #define MMX_B(n) _b[7 - (n)]
764 #define MMX_W(n) _w[3 - (n)]
765 #define MMX_L(n) _l[1 - (n)]
766 #define MMX_S(n) _s[1 - (n)]
767 #else
768 #define XMM_B(n) _b[n]
769 #define XMM_W(n) _w[n]
770 #define XMM_L(n) _l[n]
771 #define XMM_S(n) _s[n]
772 #define XMM_Q(n) _q[n]
773 #define XMM_D(n) _d[n]
775 #define MMX_B(n) _b[n]
776 #define MMX_W(n) _w[n]
777 #define MMX_L(n) _l[n]
778 #define MMX_S(n) _s[n]
779 #endif
780 #define MMX_Q(n) q
782 typedef union {
783 floatx80 d __attribute__((aligned(16)));
784 MMXReg mmx;
785 } FPReg;
787 typedef struct {
788 uint64_t base;
789 uint64_t mask;
790 } MTRRVar;
792 #define CPU_NB_REGS64 16
793 #define CPU_NB_REGS32 8
795 #ifdef TARGET_X86_64
796 #define CPU_NB_REGS CPU_NB_REGS64
797 #else
798 #define CPU_NB_REGS CPU_NB_REGS32
799 #endif
801 #define MAX_FIXED_COUNTERS 3
802 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
804 #define NB_MMU_MODES 3
805 #define TARGET_INSN_START_EXTRA_WORDS 1
807 #define NB_OPMASK_REGS 8
809 typedef enum TPRAccess {
810 TPR_ACCESS_READ,
811 TPR_ACCESS_WRITE,
812 } TPRAccess;
814 typedef struct CPUX86State {
815 /* standard registers */
816 target_ulong regs[CPU_NB_REGS];
817 target_ulong eip;
818 target_ulong eflags; /* eflags register. During CPU emulation, CC
819 flags and DF are set to zero because they are
820 stored elsewhere */
822 /* emulator internal eflags handling */
823 target_ulong cc_dst;
824 target_ulong cc_src;
825 target_ulong cc_src2;
826 uint32_t cc_op;
827 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
828 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
829 are known at translation time. */
830 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
832 /* segments */
833 SegmentCache segs[6]; /* selector values */
834 SegmentCache ldt;
835 SegmentCache tr;
836 SegmentCache gdt; /* only base and limit are used */
837 SegmentCache idt; /* only base and limit are used */
839 target_ulong cr[5]; /* NOTE: cr1 is unused */
840 int32_t a20_mask;
842 BNDReg bnd_regs[4];
843 BNDCSReg bndcs_regs;
844 uint64_t msr_bndcfgs;
845 uint64_t efer;
847 /* Beginning of state preserved by INIT (dummy marker). */
848 struct {} start_init_save;
850 /* FPU state */
851 unsigned int fpstt; /* top of stack index */
852 uint16_t fpus;
853 uint16_t fpuc;
854 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
855 FPReg fpregs[8];
856 /* KVM-only so far */
857 uint16_t fpop;
858 uint64_t fpip;
859 uint64_t fpdp;
861 /* emulator internal variables */
862 float_status fp_status;
863 floatx80 ft0;
865 float_status mmx_status; /* for 3DNow! float ops */
866 float_status sse_status;
867 uint32_t mxcsr;
868 XMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
869 XMMReg xmm_t0;
870 MMXReg mmx_t0;
872 uint64_t opmask_regs[NB_OPMASK_REGS];
874 /* sysenter registers */
875 uint32_t sysenter_cs;
876 target_ulong sysenter_esp;
877 target_ulong sysenter_eip;
878 uint64_t star;
880 uint64_t vm_hsave;
882 #ifdef TARGET_X86_64
883 target_ulong lstar;
884 target_ulong cstar;
885 target_ulong fmask;
886 target_ulong kernelgsbase;
887 #endif
889 uint64_t tsc;
890 uint64_t tsc_adjust;
891 uint64_t tsc_deadline;
893 uint64_t mcg_status;
894 uint64_t msr_ia32_misc_enable;
895 uint64_t msr_ia32_feature_control;
897 uint64_t msr_fixed_ctr_ctrl;
898 uint64_t msr_global_ctrl;
899 uint64_t msr_global_status;
900 uint64_t msr_global_ovf_ctrl;
901 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
902 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
903 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
905 uint64_t pat;
906 uint32_t smbase;
908 /* End of state preserved by INIT (dummy marker). */
909 struct {} end_init_save;
911 uint64_t system_time_msr;
912 uint64_t wall_clock_msr;
913 uint64_t steal_time_msr;
914 uint64_t async_pf_en_msr;
915 uint64_t pv_eoi_en_msr;
917 uint64_t msr_hv_hypercall;
918 uint64_t msr_hv_guest_os_id;
919 uint64_t msr_hv_vapic;
920 uint64_t msr_hv_tsc;
921 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS];
922 uint64_t msr_hv_runtime;
923 uint64_t msr_hv_synic_control;
924 uint64_t msr_hv_synic_version;
925 uint64_t msr_hv_synic_evt_page;
926 uint64_t msr_hv_synic_msg_page;
927 uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT];
928 uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT];
929 uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT];
931 /* exception/interrupt handling */
932 int error_code;
933 int exception_is_int;
934 target_ulong exception_next_eip;
935 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
936 union {
937 struct CPUBreakpoint *cpu_breakpoint[4];
938 struct CPUWatchpoint *cpu_watchpoint[4];
939 }; /* break/watchpoints for dr[0..3] */
940 int old_exception; /* exception in flight */
942 uint64_t vm_vmcb;
943 uint64_t tsc_offset;
944 uint64_t intercept;
945 uint16_t intercept_cr_read;
946 uint16_t intercept_cr_write;
947 uint16_t intercept_dr_read;
948 uint16_t intercept_dr_write;
949 uint32_t intercept_exceptions;
950 uint8_t v_tpr;
952 /* KVM states, automatically cleared on reset */
953 uint8_t nmi_injected;
954 uint8_t nmi_pending;
956 CPU_COMMON
958 /* Fields from here on are preserved across CPU reset. */
960 /* processor features (e.g. for CPUID insn) */
961 uint32_t cpuid_level;
962 uint32_t cpuid_xlevel;
963 uint32_t cpuid_xlevel2;
964 uint32_t cpuid_vendor1;
965 uint32_t cpuid_vendor2;
966 uint32_t cpuid_vendor3;
967 uint32_t cpuid_version;
968 FeatureWordArray features;
969 uint32_t cpuid_model[12];
971 /* MTRRs */
972 uint64_t mtrr_fixed[11];
973 uint64_t mtrr_deftype;
974 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
976 /* For KVM */
977 uint32_t mp_state;
978 int32_t exception_injected;
979 int32_t interrupt_injected;
980 uint8_t soft_interrupt;
981 uint8_t has_error_code;
982 uint32_t sipi_vector;
983 bool tsc_valid;
984 int64_t tsc_khz;
985 void *kvm_xsave_buf;
987 uint64_t mcg_cap;
988 uint64_t mcg_ctl;
989 uint64_t mce_banks[MCE_BANKS_DEF*4];
991 uint64_t tsc_aux;
993 /* vmstate */
994 uint16_t fpus_vmstate;
995 uint16_t fptag_vmstate;
996 uint16_t fpregs_format_vmstate;
997 uint64_t xstate_bv;
999 uint64_t xcr0;
1000 uint64_t xss;
1002 TPRAccess tpr_access_type;
1003 } CPUX86State;
1005 #include "cpu-qom.h"
1007 X86CPU *cpu_x86_init(const char *cpu_model);
1008 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
1009 int cpu_x86_exec(CPUState *cpu);
1010 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1011 void x86_cpudef_setup(void);
1012 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1014 int cpu_get_pic_interrupt(CPUX86State *s);
1015 /* MSDOS compatibility mode FPU exception support */
1016 void cpu_set_ferr(CPUX86State *s);
1018 /* this function must always be used to load data in the segment
1019 cache: it synchronizes the hflags with the segment cache values */
1020 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1021 int seg_reg, unsigned int selector,
1022 target_ulong base,
1023 unsigned int limit,
1024 unsigned int flags)
1026 SegmentCache *sc;
1027 unsigned int new_hflags;
1029 sc = &env->segs[seg_reg];
1030 sc->selector = selector;
1031 sc->base = base;
1032 sc->limit = limit;
1033 sc->flags = flags;
1035 /* update the hidden flags */
1037 if (seg_reg == R_CS) {
1038 #ifdef TARGET_X86_64
1039 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1040 /* long mode */
1041 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1042 env->hflags &= ~(HF_ADDSEG_MASK);
1043 } else
1044 #endif
1046 /* legacy / compatibility case */
1047 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1048 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1049 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1050 new_hflags;
1053 if (seg_reg == R_SS) {
1054 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1055 #if HF_CPL_MASK != 3
1056 #error HF_CPL_MASK is hardcoded
1057 #endif
1058 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1060 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1061 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1062 if (env->hflags & HF_CS64_MASK) {
1063 /* zero base assumed for DS, ES and SS in long mode */
1064 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1065 (env->eflags & VM_MASK) ||
1066 !(env->hflags & HF_CS32_MASK)) {
1067 /* XXX: try to avoid this test. The problem comes from the
1068 fact that is real mode or vm86 mode we only modify the
1069 'base' and 'selector' fields of the segment cache to go
1070 faster. A solution may be to force addseg to one in
1071 translate-i386.c. */
1072 new_hflags |= HF_ADDSEG_MASK;
1073 } else {
1074 new_hflags |= ((env->segs[R_DS].base |
1075 env->segs[R_ES].base |
1076 env->segs[R_SS].base) != 0) <<
1077 HF_ADDSEG_SHIFT;
1079 env->hflags = (env->hflags &
1080 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1084 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1085 uint8_t sipi_vector)
1087 CPUState *cs = CPU(cpu);
1088 CPUX86State *env = &cpu->env;
1090 env->eip = 0;
1091 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1092 sipi_vector << 12,
1093 env->segs[R_CS].limit,
1094 env->segs[R_CS].flags);
1095 cs->halted = 0;
1098 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1099 target_ulong *base, unsigned int *limit,
1100 unsigned int *flags);
1102 /* op_helper.c */
1103 /* used for debug or cpu save/restore */
1104 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1105 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1107 /* cpu-exec.c */
1108 /* the following helpers are only usable in user mode simulation as
1109 they can trigger unexpected exceptions */
1110 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1111 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1112 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1114 /* you can call this signal handler from your SIGBUS and SIGSEGV
1115 signal handlers to inform the virtual CPU of exceptions. non zero
1116 is returned if the signal was handled by the virtual CPU. */
1117 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1118 void *puc);
1120 /* cpuid.c */
1121 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1122 uint32_t *eax, uint32_t *ebx,
1123 uint32_t *ecx, uint32_t *edx);
1124 void cpu_clear_apic_feature(CPUX86State *env);
1125 void host_cpuid(uint32_t function, uint32_t count,
1126 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1128 /* helper.c */
1129 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1130 int is_write, int mmu_idx);
1131 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1133 #ifndef CONFIG_USER_ONLY
1134 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1135 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1136 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1137 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1138 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1139 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1140 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1141 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1142 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1143 #endif
1145 void breakpoint_handler(CPUState *cs);
1147 /* will be suppressed */
1148 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1149 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1150 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1151 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1153 /* hw/pc.c */
1154 uint64_t cpu_get_tsc(CPUX86State *env);
1156 #define TARGET_PAGE_BITS 12
1158 #ifdef TARGET_X86_64
1159 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1160 /* ??? This is really 48 bits, sign-extended, but the only thing
1161 accessible to userland with bit 48 set is the VSYSCALL, and that
1162 is handled via other mechanisms. */
1163 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1164 #else
1165 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1166 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1167 #endif
1169 /* XXX: This value should match the one returned by CPUID
1170 * and in exec.c */
1171 # if defined(TARGET_X86_64)
1172 # define PHYS_ADDR_MASK 0xffffffffffLL
1173 # else
1174 # define PHYS_ADDR_MASK 0xfffffffffLL
1175 # endif
1177 #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
1179 #define cpu_exec cpu_x86_exec
1180 #define cpu_signal_handler cpu_x86_signal_handler
1181 #define cpu_list x86_cpu_list
1182 #define cpudef_setup x86_cpudef_setup
1184 /* MMU modes definitions */
1185 #define MMU_MODE0_SUFFIX _ksmap
1186 #define MMU_MODE1_SUFFIX _user
1187 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1188 #define MMU_KSMAP_IDX 0
1189 #define MMU_USER_IDX 1
1190 #define MMU_KNOSMAP_IDX 2
1191 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1193 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1194 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1195 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1198 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1200 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1201 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1202 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1205 #define CC_DST (env->cc_dst)
1206 #define CC_SRC (env->cc_src)
1207 #define CC_SRC2 (env->cc_src2)
1208 #define CC_OP (env->cc_op)
1210 /* n must be a constant to be efficient */
1211 static inline target_long lshift(target_long x, int n)
1213 if (n >= 0) {
1214 return x << n;
1215 } else {
1216 return x >> (-n);
1220 /* float macros */
1221 #define FT0 (env->ft0)
1222 #define ST0 (env->fpregs[env->fpstt].d)
1223 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1224 #define ST1 ST(1)
1226 /* translate.c */
1227 void optimize_flags_init(void);
1229 #include "exec/cpu-all.h"
1230 #include "svm.h"
1232 #if !defined(CONFIG_USER_ONLY)
1233 #include "hw/i386/apic.h"
1234 #endif
1236 #include "exec/exec-all.h"
1238 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1239 target_ulong *cs_base, int *flags)
1241 *cs_base = env->segs[R_CS].base;
1242 *pc = *cs_base + env->eip;
1243 *flags = env->hflags |
1244 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1247 void do_cpu_init(X86CPU *cpu);
1248 void do_cpu_sipi(X86CPU *cpu);
1250 #define MCE_INJECT_BROADCAST 1
1251 #define MCE_INJECT_UNCOND_AO 2
1253 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1254 uint64_t status, uint64_t mcg_status, uint64_t addr,
1255 uint64_t misc, int flags);
1257 /* excp_helper.c */
1258 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1259 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1260 uintptr_t retaddr);
1261 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1262 int error_code);
1263 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1264 int error_code, uintptr_t retaddr);
1265 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1266 int error_code, int next_eip_addend);
1268 /* cc_helper.c */
1269 extern const uint8_t parity_table[256];
1270 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1271 void update_fp_status(CPUX86State *env);
1273 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1275 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1278 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1279 * after generating a call to a helper that uses this.
1281 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1282 int update_mask)
1284 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1285 CC_OP = CC_OP_EFLAGS;
1286 env->df = 1 - (2 * ((eflags >> 10) & 1));
1287 env->eflags = (env->eflags & ~update_mask) |
1288 (eflags & update_mask) | 0x2;
1291 /* load efer and update the corresponding hflags. XXX: do consistency
1292 checks with cpuid bits? */
1293 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1295 env->efer = val;
1296 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1297 if (env->efer & MSR_EFER_LMA) {
1298 env->hflags |= HF_LMA_MASK;
1300 if (env->efer & MSR_EFER_SVME) {
1301 env->hflags |= HF_SVME_MASK;
1305 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1307 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1310 /* fpu_helper.c */
1311 void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
1312 void cpu_set_fpuc(CPUX86State *env, uint16_t val);
1314 /* mem_helper.c */
1315 void helper_lock_init(void);
1317 /* svm_helper.c */
1318 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1319 uint64_t param);
1320 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1322 /* seg_helper.c */
1323 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1325 /* smm_helper.c */
1326 void do_smm_enter(X86CPU *cpu);
1327 void cpu_smm_update(X86CPU *cpu);
1329 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1331 /* Change the value of a KVM-specific default
1333 * If value is NULL, no default will be set and the original
1334 * value from the CPU model table will be kept.
1336 * It is valid to call this funciton only for properties that
1337 * are already present in the kvm_default_props table.
1339 void x86_cpu_change_kvm_default(const char *prop, const char *value);
1342 /* Return name of 32-bit register, from a R_* constant */
1343 const char *get_register_name_32(unsigned int reg);
1345 void enable_compat_apic_id_mode(void);
1347 #define APIC_DEFAULT_ADDRESS 0xfee00000
1348 #define APIC_SPACE_SIZE 0x100000
1350 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1351 fprintf_function cpu_fprintf, int flags);
1353 #endif /* CPU_I386_H */