tests/i440fx-test.c

   1 /*
   2  * qtest I440FX test case
   3  *
   4  * Copyright IBM, Corp. 2012-2013
   5  * Copyright Red Hat, Inc. 2013
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *  Laszlo Ersek      <lersek@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include <glib.h>
  16 #include <string.h>
  17 #include <stdio.h>
  18 #include <unistd.h>
  19 #include <errno.h>
  20 #include <sys/mman.h>
  21 #include <stdlib.h>
  22
  23 #include "libqtest.h"
  24 #include "libqos/pci.h"
  25 #include "libqos/pci-pc.h"
  26 #include "hw/pci/pci_regs.h"
  27
  28 #define BROKEN 1
  29
  30 #define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
  31
  32 typedef struct TestData
  33 {
  34     int num_cpus;
  35 } TestData;
  36
  37 typedef struct FirmwareTestFixture {
  38     /* decides whether we're testing -bios or -pflash */
  39     bool is_bios;
  40 } FirmwareTestFixture;
  41
  42 static QPCIBus *test_start_get_bus(const TestData *s)
  43 {
  44     char *cmdline;
  45
  46     cmdline = g_strdup_printf("-smp %d", s->num_cpus);
  47     qtest_start(cmdline);
  48     g_free(cmdline);
  49     return qpci_init_pc();
  50 }
  51
  52 static void test_i440fx_defaults(gconstpointer opaque)
  53 {
  54     const TestData *s = opaque;
  55     QPCIBus *bus;
  56     QPCIDevice *dev;
  57     uint32_t value;
  58
  59     bus = test_start_get_bus(s);
  60     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
  61     g_assert(dev != NULL);
  62
  63     /* 3.2.2 */
  64     g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
  65     /* 3.2.3 */
  66     g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
  67 #ifndef BROKEN
  68     /* 3.2.4 */
  69     g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
  70     /* 3.2.5 */
  71     g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
  72 #endif
  73     /* 3.2.7 */
  74     g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
  75     g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
  76     /* 3.2.8 */
  77     g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
  78     /* 3.2.9 */
  79     g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
  80     /* 3.2.10 */
  81     g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
  82
  83     /* 3.2.11 */
  84     value = qpci_config_readw(dev, 0x50); /* PMCCFG */
  85     if (s->num_cpus == 1) { /* WPE */
  86         g_assert(!(value & (1 << 15)));
  87     } else {
  88         g_assert((value & (1 << 15)));
  89     }
  90
  91     g_assert(!(value & (1 << 6))); /* EPTE */
  92
  93     /* 3.2.12 */
  94     g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
  95     /* 3.2.13 */
  96 #ifndef BROKEN
  97     g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
  98 #endif
  99     /* 3.2.14 */
 100     g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
 101     /* 3.2.15 */
 102     g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
 103 #ifndef BROKEN
 104     /* 3.2.16 */
 105     g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
 106     /* 3.2.17 */
 107     g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
 108 #endif
 109     /* 3.2.18 */
 110     g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
 111     g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
 112     g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
 113     g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
 114     g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
 115     g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
 116     g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
 117 #ifndef BROKEN
 118     /* 3.2.19 */
 119     g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
 120     g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
 121     g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
 122     g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
 123     g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
 124     g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
 125     g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
 126     g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
 127 #endif
 128     /* 3.2.20 */
 129     g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
 130     /* 3.2.21 */
 131     g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
 132 #ifndef BROKEN
 133     /* 3.2.22 */
 134     g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
 135 #endif
 136     /* 3.2.23 */
 137     g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
 138     /* 3.2.24 */
 139     g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
 140     /* 3.2.25 */
 141     g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
 142     /* 3.2.26 */
 143     g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 144
 145     qtest_end();
 146 }
 147
 148 #define PAM_RE 1
 149 #define PAM_WE 2
 150
 151 static void pam_set(QPCIDevice *dev, int index, int flags)
 152 {
 153     int regno = 0x59 + (index / 2);
 154     uint8_t reg;
 155
 156     reg = qpci_config_readb(dev, regno);
 157     if (index & 1) {
 158         reg = (reg & 0x0F) | (flags << 4);
 159     } else {
 160         reg = (reg & 0xF0) | flags;
 161     }
 162     qpci_config_writeb(dev, regno, reg);
 163 }
 164
 165 static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
 166 {
 167     uint32_t size = end - start + 1;
 168     gboolean ret = TRUE;
 169     uint8_t *data;
 170     int i;
 171
 172     data = g_malloc0(size);
 173     memread(start, data, size);
 174
 175     g_test_message("verify_area: data[0] = 0x%x", data[0]);
 176
 177     for (i = 0; i < size; i++) {
 178         if (data[i] != value) {
 179             ret = FALSE;
 180             break;
 181         }
 182     }
 183
 184     g_free(data);
 185
 186     return ret;
 187 }
 188
 189 static void write_area(uint32_t start, uint32_t end, uint8_t value)
 190 {
 191     uint32_t size = end - start + 1;
 192     uint8_t *data;
 193
 194     data = g_malloc0(size);
 195     memset(data, value, size);
 196     memwrite(start, data, size);
 197
 198     g_free(data);
 199 }
 200
 201 static void test_i440fx_pam(gconstpointer opaque)
 202 {
 203     const TestData *s = opaque;
 204     QPCIBus *bus;
 205     QPCIDevice *dev;
 206     int i;
 207     static struct {
 208         uint32_t start;
 209         uint32_t end;
 210     } pam_area[] = {
 211         { 0, 0 },             /* Reserved */
 212         { 0xF0000, 0xFFFFF }, /* BIOS Area */
 213         { 0xC0000, 0xC3FFF }, /* Option ROM */
 214         { 0xC4000, 0xC7FFF }, /* Option ROM */
 215         { 0xC8000, 0xCBFFF }, /* Option ROM */
 216         { 0xCC000, 0xCFFFF }, /* Option ROM */
 217         { 0xD0000, 0xD3FFF }, /* Option ROM */
 218         { 0xD4000, 0xD7FFF }, /* Option ROM */
 219         { 0xD8000, 0xDBFFF }, /* Option ROM */
 220         { 0xDC000, 0xDFFFF }, /* Option ROM */
 221         { 0xE0000, 0xE3FFF }, /* BIOS Extension */
 222         { 0xE4000, 0xE7FFF }, /* BIOS Extension */
 223         { 0xE8000, 0xEBFFF }, /* BIOS Extension */
 224         { 0xEC000, 0xEFFFF }, /* BIOS Extension */
 225     };
 226
 227     bus = test_start_get_bus(s);
 228     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
 229     g_assert(dev != NULL);
 230
 231     for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
 232         if (pam_area[i].start == pam_area[i].end) {
 233             continue;
 234         }
 235
 236         g_test_message("Checking area 0x%05x..0x%05x",
 237                        pam_area[i].start, pam_area[i].end);
 238         /* Switch to RE for the area */
 239         pam_set(dev, i, PAM_RE);
 240         /* Verify the RAM is all zeros */
 241         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
 242
 243         /* Switch to WE for the area */
 244         pam_set(dev, i, PAM_RE | PAM_WE);
 245         /* Write out a non-zero mask to the full area */
 246         write_area(pam_area[i].start, pam_area[i].end, 0x42);
 247
 248 #ifndef BROKEN
 249         /* QEMU only supports a limited form of PAM */
 250
 251         /* Switch to !RE for the area */
 252         pam_set(dev, i, PAM_WE);
 253         /* Verify the area is not our mask */
 254         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 255 #endif
 256
 257         /* Verify the area is our new mask */
 258         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 259
 260         /* Write out a new mask */
 261         write_area(pam_area[i].start, pam_area[i].end, 0x82);
 262
 263 #ifndef BROKEN
 264         /* QEMU only supports a limited form of PAM */
 265
 266         /* Verify the area is not our mask */
 267         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 268
 269         /* Switch to RE for the area */
 270         pam_set(dev, i, PAM_RE | PAM_WE);
 271 #endif
 272         /* Verify the area is our new mask */
 273         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 274
 275         /* Reset area */
 276         pam_set(dev, i, 0);
 277
 278         /* Verify the area is not our new mask */
 279         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 280     }
 281     qtest_end();
 282 }
 283
 284 #define BLOB_SIZE ((size_t)65536)
 285 #define ISA_BIOS_MAXSZ ((size_t)(128 * 1024))
 286
 287 /* Create a blob file, and return its absolute pathname as a dynamically
 288  * allocated string.
 289  * The file is closed before the function returns.
 290  * In case of error, NULL is returned. The function prints the error message.
 291  */
 292 static char *create_blob_file(void)
 293 {
 294     int ret, fd;
 295     char *pathname;
 296     GError *error = NULL;
 297
 298     ret = -1;
 299     fd = g_file_open_tmp("blob_XXXXXX", &pathname, &error);
 300     if (fd == -1) {
 301         fprintf(stderr, "unable to create blob file: %s\n", error->message);
 302         g_error_free(error);
 303     } else {
 304         if (ftruncate(fd, BLOB_SIZE) == -1) {
 305             fprintf(stderr, "ftruncate(\"%s\", %zu): %s\n", pathname,
 306                     BLOB_SIZE, strerror(errno));
 307         } else {
 308             void *buf;
 309
 310             buf = mmap(NULL, BLOB_SIZE, PROT_WRITE, MAP_SHARED, fd, 0);
 311             if (buf == MAP_FAILED) {
 312                 fprintf(stderr, "mmap(\"%s\", %zu): %s\n", pathname, BLOB_SIZE,
 313                         strerror(errno));
 314             } else {
 315                 size_t i;
 316
 317                 for (i = 0; i < BLOB_SIZE; ++i) {
 318                     ((uint8_t *)buf)[i] = i;
 319                 }
 320                 munmap(buf, BLOB_SIZE);
 321                 ret = 0;
 322             }
 323         }
 324         close(fd);
 325         if (ret == -1) {
 326             unlink(pathname);
 327             g_free(pathname);
 328         }
 329     }
 330
 331     return ret == -1 ? NULL : pathname;
 332 }
 333
 334 static void test_i440fx_firmware(FirmwareTestFixture *fixture,
 335                                  gconstpointer user_data)
 336 {
 337     char *fw_pathname, *cmdline;
 338     uint8_t *buf;
 339     size_t i, isa_bios_size;
 340
 341     fw_pathname = create_blob_file();
 342     g_assert(fw_pathname != NULL);
 343
 344     /* Better hope the user didn't put metacharacters in TMPDIR and co. */
 345     cmdline = g_strdup_printf("-S %s%s", fixture->is_bios
 346                                          ? "-bios "
 347                                          : "-drive if=pflash,format=raw,file=",
 348                               fw_pathname);
 349     g_test_message("qemu cmdline: %s", cmdline);
 350     qtest_start(cmdline);
 351     g_free(cmdline);
 352
 353     /* QEMU has loaded the firmware (because qtest_start() only returns after
 354      * the QMP handshake completes). We must unlink the firmware blob right
 355      * here, because any assertion firing below would leak it in the
 356      * filesystem. This is also the reason why we recreate the blob every time
 357      * this function is invoked.
 358      */
 359     unlink(fw_pathname);
 360     g_free(fw_pathname);
 361
 362     /* check below 4G */
 363     buf = g_malloc0(BLOB_SIZE);
 364     memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);
 365     for (i = 0; i < BLOB_SIZE; ++i) {
 366         g_assert_cmphex(buf[i], ==, (uint8_t)i);
 367     }
 368
 369     /* check in ISA space too */
 370     memset(buf, 0, BLOB_SIZE);
 371     isa_bios_size = ISA_BIOS_MAXSZ < BLOB_SIZE ? ISA_BIOS_MAXSZ : BLOB_SIZE;
 372     memread(0x100000 - isa_bios_size, buf, isa_bios_size);
 373     for (i = 0; i < isa_bios_size; ++i) {
 374         g_assert_cmphex(buf[i], ==,
 375                         (uint8_t)((BLOB_SIZE - isa_bios_size) + i));
 376     }
 377
 378     g_free(buf);
 379     qtest_end();
 380 }
 381
 382 static void add_firmware_test(const char *testpath,
 383                               void (*setup_fixture)(FirmwareTestFixture *f,
 384                                                     gconstpointer test_data))
 385 {
 386     g_test_add(testpath, FirmwareTestFixture, NULL, setup_fixture,
 387                test_i440fx_firmware, NULL);
 388 }
 389
 390 static void request_bios(FirmwareTestFixture *fixture,
 391                          gconstpointer user_data)
 392 {
 393     fixture->is_bios = true;
 394 }
 395
 396 static void request_pflash(FirmwareTestFixture *fixture,
 397                            gconstpointer user_data)
 398 {
 399     fixture->is_bios = false;
 400 }
 401
 402 int main(int argc, char **argv)
 403 {
 404     TestData data;
 405     int ret;
 406
 407     g_test_init(&argc, &argv, NULL);
 408
 409     data.num_cpus = 1;
 410
 411     g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
 412     g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
 413     add_firmware_test("/i440fx/firmware/bios", request_bios);
 414     add_firmware_test("/i440fx/firmware/pflash", request_pflash);
 415
 416     ret = g_test_run();
 417     return ret;
 418 }