2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/char/serial.h"
29 #include "migration/vmstate.h"
30 #include "chardev/char-serial.h"
31 #include "qapi/error.h"
32 #include "qemu/timer.h"
33 #include "sysemu/reset.h"
34 #include "sysemu/runstate.h"
35 #include "qemu/error-report.h"
38 //#define DEBUG_SERIAL
40 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
42 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
43 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
44 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
45 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
47 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
48 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
50 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
51 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
52 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
53 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
54 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
56 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
57 #define UART_IIR_FE 0xC0 /* Fifo enabled */
60 * These are the definitions for the Modem Control Register
62 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
63 #define UART_MCR_OUT2 0x08 /* Out2 complement */
64 #define UART_MCR_OUT1 0x04 /* Out1 complement */
65 #define UART_MCR_RTS 0x02 /* RTS complement */
66 #define UART_MCR_DTR 0x01 /* DTR complement */
69 * These are the definitions for the Modem Status Register
71 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
72 #define UART_MSR_RI 0x40 /* Ring Indicator */
73 #define UART_MSR_DSR 0x20 /* Data Set Ready */
74 #define UART_MSR_CTS 0x10 /* Clear to Send */
75 #define UART_MSR_DDCD 0x08 /* Delta DCD */
76 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
77 #define UART_MSR_DDSR 0x02 /* Delta DSR */
78 #define UART_MSR_DCTS 0x01 /* Delta CTS */
79 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
81 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
82 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
83 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
84 #define UART_LSR_FE 0x08 /* Frame error indicator */
85 #define UART_LSR_PE 0x04 /* Parity error indicator */
86 #define UART_LSR_OE 0x02 /* Overrun error indicator */
87 #define UART_LSR_DR 0x01 /* Receiver data ready */
88 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
90 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
92 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
93 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
94 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
95 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
97 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
98 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
99 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
100 #define UART_FCR_FE 0x01 /* FIFO Enable */
102 #define MAX_XMIT_RETRY 4
105 #define DPRINTF(fmt, ...) \
106 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
108 #define DPRINTF(fmt, ...) \
112 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
);
113 static void serial_xmit(SerialState
*s
);
115 static inline void recv_fifo_put(SerialState
*s
, uint8_t chr
)
117 /* Receive overruns do not overwrite FIFO contents. */
118 if (!fifo8_is_full(&s
->recv_fifo
)) {
119 fifo8_push(&s
->recv_fifo
, chr
);
121 s
->lsr
|= UART_LSR_OE
;
125 static void serial_update_irq(SerialState
*s
)
127 uint8_t tmp_iir
= UART_IIR_NO_INT
;
129 if ((s
->ier
& UART_IER_RLSI
) && (s
->lsr
& UART_LSR_INT_ANY
)) {
130 tmp_iir
= UART_IIR_RLSI
;
131 } else if ((s
->ier
& UART_IER_RDI
) && s
->timeout_ipending
) {
132 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
133 * this is not in the specification but is observed on existing
135 tmp_iir
= UART_IIR_CTI
;
136 } else if ((s
->ier
& UART_IER_RDI
) && (s
->lsr
& UART_LSR_DR
) &&
137 (!(s
->fcr
& UART_FCR_FE
) ||
138 s
->recv_fifo
.num
>= s
->recv_fifo_itl
)) {
139 tmp_iir
= UART_IIR_RDI
;
140 } else if ((s
->ier
& UART_IER_THRI
) && s
->thr_ipending
) {
141 tmp_iir
= UART_IIR_THRI
;
142 } else if ((s
->ier
& UART_IER_MSI
) && (s
->msr
& UART_MSR_ANY_DELTA
)) {
143 tmp_iir
= UART_IIR_MSI
;
146 s
->iir
= tmp_iir
| (s
->iir
& 0xF0);
148 if (tmp_iir
!= UART_IIR_NO_INT
) {
149 qemu_irq_raise(s
->irq
);
151 qemu_irq_lower(s
->irq
);
155 static void serial_update_parameters(SerialState
*s
)
158 int parity
, data_bits
, stop_bits
, frame_size
;
159 QEMUSerialSetParams ssp
;
179 data_bits
= (s
->lcr
& 0x03) + 5;
180 frame_size
+= data_bits
+ stop_bits
;
181 /* Zero divisor should give about 3500 baud */
182 speed
= (s
->divider
== 0) ? 3500 : (float) s
->baudbase
/ s
->divider
;
185 ssp
.data_bits
= data_bits
;
186 ssp
.stop_bits
= stop_bits
;
187 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
188 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
190 DPRINTF("speed=%.2f parity=%c data=%d stop=%d\n",
191 speed
, parity
, data_bits
, stop_bits
);
194 static void serial_update_msl(SerialState
*s
)
199 timer_del(s
->modem_status_poll
);
201 if (qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
,
202 &flags
) == -ENOTSUP
) {
209 s
->msr
= (flags
& CHR_TIOCM_CTS
) ? s
->msr
| UART_MSR_CTS
: s
->msr
& ~UART_MSR_CTS
;
210 s
->msr
= (flags
& CHR_TIOCM_DSR
) ? s
->msr
| UART_MSR_DSR
: s
->msr
& ~UART_MSR_DSR
;
211 s
->msr
= (flags
& CHR_TIOCM_CAR
) ? s
->msr
| UART_MSR_DCD
: s
->msr
& ~UART_MSR_DCD
;
212 s
->msr
= (flags
& CHR_TIOCM_RI
) ? s
->msr
| UART_MSR_RI
: s
->msr
& ~UART_MSR_RI
;
214 if (s
->msr
!= omsr
) {
216 s
->msr
= s
->msr
| ((s
->msr
>> 4) ^ (omsr
>> 4));
217 /* UART_MSR_TERI only if change was from 1 -> 0 */
218 if ((s
->msr
& UART_MSR_TERI
) && !(omsr
& UART_MSR_RI
))
219 s
->msr
&= ~UART_MSR_TERI
;
220 serial_update_irq(s
);
223 /* The real 16550A apparently has a 250ns response latency to line status changes.
224 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
227 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
228 NANOSECONDS_PER_SECOND
/ 100);
232 static gboolean
serial_watch_cb(GIOChannel
*chan
, GIOCondition cond
,
235 SerialState
*s
= opaque
;
241 static void serial_xmit(SerialState
*s
)
244 assert(!(s
->lsr
& UART_LSR_TEMT
));
245 if (s
->tsr_retry
== 0) {
246 assert(!(s
->lsr
& UART_LSR_THRE
));
248 if (s
->fcr
& UART_FCR_FE
) {
249 assert(!fifo8_is_empty(&s
->xmit_fifo
));
250 s
->tsr
= fifo8_pop(&s
->xmit_fifo
);
251 if (!s
->xmit_fifo
.num
) {
252 s
->lsr
|= UART_LSR_THRE
;
256 s
->lsr
|= UART_LSR_THRE
;
258 if ((s
->lsr
& UART_LSR_THRE
) && !s
->thr_ipending
) {
260 serial_update_irq(s
);
264 if (s
->mcr
& UART_MCR_LOOP
) {
265 /* in loopback mode, say that we just received a char */
266 serial_receive1(s
, &s
->tsr
, 1);
268 int rc
= qemu_chr_fe_write(&s
->chr
, &s
->tsr
, 1);
271 (rc
== -1 && errno
== EAGAIN
)) &&
272 s
->tsr_retry
< MAX_XMIT_RETRY
) {
273 assert(s
->watch_tag
== 0);
275 qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
277 if (s
->watch_tag
> 0) {
285 /* Transmit another byte if it is already available. It is only
286 possible when FIFO is enabled and not empty. */
287 } while (!(s
->lsr
& UART_LSR_THRE
));
289 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
290 s
->lsr
|= UART_LSR_TEMT
;
294 is_load flag means, that value is set while loading VM state
295 and interrupt should not be invoked */
296 static void serial_write_fcr(SerialState
*s
, uint8_t val
)
298 /* Set fcr - val only has the bits that are supposed to "stick" */
301 if (val
& UART_FCR_FE
) {
302 s
->iir
|= UART_IIR_FE
;
303 /* Set recv_fifo trigger Level */
304 switch (val
& 0xC0) {
306 s
->recv_fifo_itl
= 1;
309 s
->recv_fifo_itl
= 4;
312 s
->recv_fifo_itl
= 8;
315 s
->recv_fifo_itl
= 14;
319 s
->iir
&= ~UART_IIR_FE
;
323 static void serial_update_tiocm(SerialState
*s
)
327 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_GET_TIOCM
, &flags
);
329 flags
&= ~(CHR_TIOCM_RTS
| CHR_TIOCM_DTR
);
331 if (s
->mcr
& UART_MCR_RTS
) {
332 flags
|= CHR_TIOCM_RTS
;
334 if (s
->mcr
& UART_MCR_DTR
) {
335 flags
|= CHR_TIOCM_DTR
;
338 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_TIOCM
, &flags
);
341 static void serial_ioport_write(void *opaque
, hwaddr addr
, uint64_t val
,
344 SerialState
*s
= opaque
;
347 trace_serial_ioport_write(addr
, val
);
351 if (s
->lcr
& UART_LCR_DLAB
) {
353 s
->divider
= (s
->divider
& 0xff00) | val
;
357 serial_update_parameters(s
);
359 s
->thr
= (uint8_t) val
;
360 if(s
->fcr
& UART_FCR_FE
) {
361 /* xmit overruns overwrite data, so make space if needed */
362 if (fifo8_is_full(&s
->xmit_fifo
)) {
363 fifo8_pop(&s
->xmit_fifo
);
365 fifo8_push(&s
->xmit_fifo
, s
->thr
);
368 s
->lsr
&= ~UART_LSR_THRE
;
369 s
->lsr
&= ~UART_LSR_TEMT
;
370 serial_update_irq(s
);
371 if (s
->tsr_retry
== 0) {
377 if (s
->lcr
& UART_LCR_DLAB
) {
378 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
379 serial_update_parameters(s
);
381 uint8_t changed
= (s
->ier
^ val
) & 0x0f;
383 /* If the backend device is a real serial port, turn polling of the modem
384 * status lines on physical port on or off depending on UART_IER_MSI state.
386 if ((changed
& UART_IER_MSI
) && s
->poll_msl
>= 0) {
387 if (s
->ier
& UART_IER_MSI
) {
389 serial_update_msl(s
);
391 timer_del(s
->modem_status_poll
);
396 /* Turning on the THRE interrupt on IER can trigger the interrupt
397 * if LSR.THRE=1, even if it had been masked before by reading IIR.
398 * This is not in the datasheet, but Windows relies on it. It is
399 * unclear if THRE has to be resampled every time THRI becomes
400 * 1, or only on the rising edge. Bochs does the latter, and Windows
401 * always toggles IER to all zeroes and back to all ones, so do the
404 * If IER.THRI is zero, thr_ipending is not used. Set it to zero
405 * so that the thr_ipending subsection is not migrated.
407 if (changed
& UART_IER_THRI
) {
408 if ((s
->ier
& UART_IER_THRI
) && (s
->lsr
& UART_LSR_THRE
)) {
416 serial_update_irq(s
);
421 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
422 if ((val
^ s
->fcr
) & UART_FCR_FE
) {
423 val
|= UART_FCR_XFR
| UART_FCR_RFR
;
428 if (val
& UART_FCR_RFR
) {
429 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
430 timer_del(s
->fifo_timeout_timer
);
431 s
->timeout_ipending
= 0;
432 fifo8_reset(&s
->recv_fifo
);
435 if (val
& UART_FCR_XFR
) {
436 s
->lsr
|= UART_LSR_THRE
;
438 fifo8_reset(&s
->xmit_fifo
);
441 serial_write_fcr(s
, val
& 0xC9);
442 serial_update_irq(s
);
448 serial_update_parameters(s
);
449 break_enable
= (val
>> 6) & 1;
450 if (break_enable
!= s
->last_break_enable
) {
451 s
->last_break_enable
= break_enable
;
452 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
459 int old_mcr
= s
->mcr
;
461 if (val
& UART_MCR_LOOP
)
464 if (s
->poll_msl
>= 0 && old_mcr
!= s
->mcr
) {
465 serial_update_tiocm(s
);
466 /* Update the modem status after a one-character-send wait-time, since there may be a response
467 from the device/computer at the other end of the serial line */
468 timer_mod(s
->modem_status_poll
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
);
482 static uint64_t serial_ioport_read(void *opaque
, hwaddr addr
, unsigned size
)
484 SerialState
*s
= opaque
;
491 if (s
->lcr
& UART_LCR_DLAB
) {
492 ret
= s
->divider
& 0xff;
494 if(s
->fcr
& UART_FCR_FE
) {
495 ret
= fifo8_is_empty(&s
->recv_fifo
) ?
496 0 : fifo8_pop(&s
->recv_fifo
);
497 if (s
->recv_fifo
.num
== 0) {
498 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
500 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
502 s
->timeout_ipending
= 0;
505 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
507 serial_update_irq(s
);
508 if (!(s
->mcr
& UART_MCR_LOOP
)) {
509 /* in loopback mode, don't receive any data */
510 qemu_chr_fe_accept_input(&s
->chr
);
515 if (s
->lcr
& UART_LCR_DLAB
) {
516 ret
= (s
->divider
>> 8) & 0xff;
523 if ((ret
& UART_IIR_ID
) == UART_IIR_THRI
) {
525 serial_update_irq(s
);
536 /* Clear break and overrun interrupts */
537 if (s
->lsr
& (UART_LSR_BI
|UART_LSR_OE
)) {
538 s
->lsr
&= ~(UART_LSR_BI
|UART_LSR_OE
);
539 serial_update_irq(s
);
543 if (s
->mcr
& UART_MCR_LOOP
) {
544 /* in loopback, the modem output pins are connected to the
546 ret
= (s
->mcr
& 0x0c) << 4;
547 ret
|= (s
->mcr
& 0x02) << 3;
548 ret
|= (s
->mcr
& 0x01) << 5;
550 if (s
->poll_msl
>= 0)
551 serial_update_msl(s
);
553 /* Clear delta bits & msr int after read, if they were set */
554 if (s
->msr
& UART_MSR_ANY_DELTA
) {
556 serial_update_irq(s
);
564 trace_serial_ioport_read(addr
, ret
);
568 static int serial_can_receive(SerialState
*s
)
570 if(s
->fcr
& UART_FCR_FE
) {
571 if (s
->recv_fifo
.num
< UART_FIFO_LENGTH
) {
573 * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
574 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
575 * effect will be to almost always fill the fifo completely before
576 * the guest has a chance to respond, effectively overriding the ITL
577 * that the guest has set.
579 return (s
->recv_fifo
.num
<= s
->recv_fifo_itl
) ?
580 s
->recv_fifo_itl
- s
->recv_fifo
.num
: 1;
585 return !(s
->lsr
& UART_LSR_DR
);
589 static void serial_receive_break(SerialState
*s
)
592 /* When the LSR_DR is set a null byte is pushed into the fifo */
593 recv_fifo_put(s
, '\0');
594 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
595 serial_update_irq(s
);
598 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
599 static void fifo_timeout_int (void *opaque
) {
600 SerialState
*s
= opaque
;
601 if (s
->recv_fifo
.num
) {
602 s
->timeout_ipending
= 1;
603 serial_update_irq(s
);
607 static int serial_can_receive1(void *opaque
)
609 SerialState
*s
= opaque
;
610 return serial_can_receive(s
);
613 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
615 SerialState
*s
= opaque
;
618 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER
, NULL
);
620 if(s
->fcr
& UART_FCR_FE
) {
622 for (i
= 0; i
< size
; i
++) {
623 recv_fifo_put(s
, buf
[i
]);
625 s
->lsr
|= UART_LSR_DR
;
626 /* call the timeout receive callback in 4 char transmit time */
627 timer_mod(s
->fifo_timeout_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 4);
629 if (s
->lsr
& UART_LSR_DR
)
630 s
->lsr
|= UART_LSR_OE
;
632 s
->lsr
|= UART_LSR_DR
;
634 serial_update_irq(s
);
637 static void serial_event(void *opaque
, int event
)
639 SerialState
*s
= opaque
;
640 DPRINTF("event %x\n", event
);
641 if (event
== CHR_EVENT_BREAK
)
642 serial_receive_break(s
);
645 static int serial_pre_save(void *opaque
)
647 SerialState
*s
= opaque
;
648 s
->fcr_vmstate
= s
->fcr
;
653 static int serial_pre_load(void *opaque
)
655 SerialState
*s
= opaque
;
656 s
->thr_ipending
= -1;
661 static int serial_post_load(void *opaque
, int version_id
)
663 SerialState
*s
= opaque
;
665 if (version_id
< 3) {
668 if (s
->thr_ipending
== -1) {
669 s
->thr_ipending
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
672 if (s
->tsr_retry
> 0) {
673 /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */
674 if (s
->lsr
& UART_LSR_TEMT
) {
675 error_report("inconsistent state in serial device "
676 "(tsr empty, tsr_retry=%d", s
->tsr_retry
);
680 if (s
->tsr_retry
> MAX_XMIT_RETRY
) {
681 s
->tsr_retry
= MAX_XMIT_RETRY
;
684 assert(s
->watch_tag
== 0);
685 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
688 /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */
689 if (!(s
->lsr
& UART_LSR_TEMT
)) {
690 error_report("inconsistent state in serial device "
691 "(tsr not empty, tsr_retry=0");
696 s
->last_break_enable
= (s
->lcr
>> 6) & 1;
697 /* Initialize fcr via setter to perform essential side-effects */
698 serial_write_fcr(s
, s
->fcr_vmstate
);
699 serial_update_parameters(s
);
703 static bool serial_thr_ipending_needed(void *opaque
)
705 SerialState
*s
= opaque
;
707 if (s
->ier
& UART_IER_THRI
) {
708 bool expected_value
= ((s
->iir
& UART_IIR_ID
) == UART_IIR_THRI
);
709 return s
->thr_ipending
!= expected_value
;
711 /* LSR.THRE will be sampled again when the interrupt is
712 * enabled. thr_ipending is not used in this case, do
719 static const VMStateDescription vmstate_serial_thr_ipending
= {
720 .name
= "serial/thr_ipending",
722 .minimum_version_id
= 1,
723 .needed
= serial_thr_ipending_needed
,
724 .fields
= (VMStateField
[]) {
725 VMSTATE_INT32(thr_ipending
, SerialState
),
726 VMSTATE_END_OF_LIST()
730 static bool serial_tsr_needed(void *opaque
)
732 SerialState
*s
= (SerialState
*)opaque
;
733 return s
->tsr_retry
!= 0;
736 static const VMStateDescription vmstate_serial_tsr
= {
737 .name
= "serial/tsr",
739 .minimum_version_id
= 1,
740 .needed
= serial_tsr_needed
,
741 .fields
= (VMStateField
[]) {
742 VMSTATE_UINT32(tsr_retry
, SerialState
),
743 VMSTATE_UINT8(thr
, SerialState
),
744 VMSTATE_UINT8(tsr
, SerialState
),
745 VMSTATE_END_OF_LIST()
749 static bool serial_recv_fifo_needed(void *opaque
)
751 SerialState
*s
= (SerialState
*)opaque
;
752 return !fifo8_is_empty(&s
->recv_fifo
);
756 static const VMStateDescription vmstate_serial_recv_fifo
= {
757 .name
= "serial/recv_fifo",
759 .minimum_version_id
= 1,
760 .needed
= serial_recv_fifo_needed
,
761 .fields
= (VMStateField
[]) {
762 VMSTATE_STRUCT(recv_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
763 VMSTATE_END_OF_LIST()
767 static bool serial_xmit_fifo_needed(void *opaque
)
769 SerialState
*s
= (SerialState
*)opaque
;
770 return !fifo8_is_empty(&s
->xmit_fifo
);
773 static const VMStateDescription vmstate_serial_xmit_fifo
= {
774 .name
= "serial/xmit_fifo",
776 .minimum_version_id
= 1,
777 .needed
= serial_xmit_fifo_needed
,
778 .fields
= (VMStateField
[]) {
779 VMSTATE_STRUCT(xmit_fifo
, SerialState
, 1, vmstate_fifo8
, Fifo8
),
780 VMSTATE_END_OF_LIST()
784 static bool serial_fifo_timeout_timer_needed(void *opaque
)
786 SerialState
*s
= (SerialState
*)opaque
;
787 return timer_pending(s
->fifo_timeout_timer
);
790 static const VMStateDescription vmstate_serial_fifo_timeout_timer
= {
791 .name
= "serial/fifo_timeout_timer",
793 .minimum_version_id
= 1,
794 .needed
= serial_fifo_timeout_timer_needed
,
795 .fields
= (VMStateField
[]) {
796 VMSTATE_TIMER_PTR(fifo_timeout_timer
, SerialState
),
797 VMSTATE_END_OF_LIST()
801 static bool serial_timeout_ipending_needed(void *opaque
)
803 SerialState
*s
= (SerialState
*)opaque
;
804 return s
->timeout_ipending
!= 0;
807 static const VMStateDescription vmstate_serial_timeout_ipending
= {
808 .name
= "serial/timeout_ipending",
810 .minimum_version_id
= 1,
811 .needed
= serial_timeout_ipending_needed
,
812 .fields
= (VMStateField
[]) {
813 VMSTATE_INT32(timeout_ipending
, SerialState
),
814 VMSTATE_END_OF_LIST()
818 static bool serial_poll_needed(void *opaque
)
820 SerialState
*s
= (SerialState
*)opaque
;
821 return s
->poll_msl
>= 0;
824 static const VMStateDescription vmstate_serial_poll
= {
825 .name
= "serial/poll",
827 .needed
= serial_poll_needed
,
828 .minimum_version_id
= 1,
829 .fields
= (VMStateField
[]) {
830 VMSTATE_INT32(poll_msl
, SerialState
),
831 VMSTATE_TIMER_PTR(modem_status_poll
, SerialState
),
832 VMSTATE_END_OF_LIST()
836 const VMStateDescription vmstate_serial
= {
839 .minimum_version_id
= 2,
840 .pre_save
= serial_pre_save
,
841 .pre_load
= serial_pre_load
,
842 .post_load
= serial_post_load
,
843 .fields
= (VMStateField
[]) {
844 VMSTATE_UINT16_V(divider
, SerialState
, 2),
845 VMSTATE_UINT8(rbr
, SerialState
),
846 VMSTATE_UINT8(ier
, SerialState
),
847 VMSTATE_UINT8(iir
, SerialState
),
848 VMSTATE_UINT8(lcr
, SerialState
),
849 VMSTATE_UINT8(mcr
, SerialState
),
850 VMSTATE_UINT8(lsr
, SerialState
),
851 VMSTATE_UINT8(msr
, SerialState
),
852 VMSTATE_UINT8(scr
, SerialState
),
853 VMSTATE_UINT8_V(fcr_vmstate
, SerialState
, 3),
854 VMSTATE_END_OF_LIST()
856 .subsections
= (const VMStateDescription
*[]) {
857 &vmstate_serial_thr_ipending
,
859 &vmstate_serial_recv_fifo
,
860 &vmstate_serial_xmit_fifo
,
861 &vmstate_serial_fifo_timeout_timer
,
862 &vmstate_serial_timeout_ipending
,
863 &vmstate_serial_poll
,
868 static void serial_reset(void *opaque
)
870 SerialState
*s
= opaque
;
872 if (s
->watch_tag
> 0) {
873 g_source_remove(s
->watch_tag
);
879 s
->iir
= UART_IIR_NO_INT
;
881 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
882 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
883 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
885 s
->mcr
= UART_MCR_OUT2
;
888 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ 9600) * 10;
891 s
->timeout_ipending
= 0;
892 timer_del(s
->fifo_timeout_timer
);
893 timer_del(s
->modem_status_poll
);
895 fifo8_reset(&s
->recv_fifo
);
896 fifo8_reset(&s
->xmit_fifo
);
898 s
->last_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
901 s
->last_break_enable
= 0;
902 qemu_irq_lower(s
->irq
);
904 serial_update_msl(s
);
905 s
->msr
&= ~UART_MSR_ANY_DELTA
;
908 static int serial_be_change(void *opaque
)
910 SerialState
*s
= opaque
;
912 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
913 serial_event
, serial_be_change
, s
, NULL
, true);
915 serial_update_parameters(s
);
917 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
918 &s
->last_break_enable
);
920 s
->poll_msl
= (s
->ier
& UART_IER_MSI
) ? 1 : 0;
921 serial_update_msl(s
);
923 if (s
->poll_msl
>= 0 && !(s
->mcr
& UART_MCR_LOOP
)) {
924 serial_update_tiocm(s
);
927 if (s
->watch_tag
> 0) {
928 g_source_remove(s
->watch_tag
);
929 s
->watch_tag
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
936 void serial_realize_core(SerialState
*s
, Error
**errp
)
938 s
->modem_status_poll
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) serial_update_msl
, s
);
940 s
->fifo_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, (QEMUTimerCB
*) fifo_timeout_int
, s
);
941 qemu_register_reset(serial_reset
, s
);
943 qemu_chr_fe_set_handlers(&s
->chr
, serial_can_receive1
, serial_receive1
,
944 serial_event
, serial_be_change
, s
, NULL
, true);
945 fifo8_create(&s
->recv_fifo
, UART_FIFO_LENGTH
);
946 fifo8_create(&s
->xmit_fifo
, UART_FIFO_LENGTH
);
950 void serial_exit_core(SerialState
*s
)
952 qemu_chr_fe_deinit(&s
->chr
, false);
954 timer_del(s
->modem_status_poll
);
955 timer_free(s
->modem_status_poll
);
957 timer_del(s
->fifo_timeout_timer
);
958 timer_free(s
->fifo_timeout_timer
);
960 fifo8_destroy(&s
->recv_fifo
);
961 fifo8_destroy(&s
->xmit_fifo
);
963 qemu_unregister_reset(serial_reset
, s
);
966 /* Change the main reference oscillator frequency. */
967 void serial_set_frequency(SerialState
*s
, uint32_t frequency
)
969 s
->baudbase
= frequency
;
970 serial_update_parameters(s
);
973 const MemoryRegionOps serial_io_ops
= {
974 .read
= serial_ioport_read
,
975 .write
= serial_ioport_write
,
977 .min_access_size
= 1,
978 .max_access_size
= 1,
980 .endianness
= DEVICE_LITTLE_ENDIAN
,
983 SerialState
*serial_init(int base
, qemu_irq irq
, int baudbase
,
984 Chardev
*chr
, MemoryRegion
*system_io
)
988 s
= g_malloc0(sizeof(SerialState
));
991 s
->baudbase
= baudbase
;
992 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
993 serial_realize_core(s
, &error_fatal
);
995 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
997 memory_region_init_io(&s
->io
, NULL
, &serial_io_ops
, s
, "serial", 8);
998 memory_region_add_subregion(system_io
, base
, &s
->io
);
1003 /* Memory mapped interface */
1004 static uint64_t serial_mm_read(void *opaque
, hwaddr addr
,
1007 SerialState
*s
= opaque
;
1008 return serial_ioport_read(s
, addr
>> s
->it_shift
, 1);
1011 static void serial_mm_write(void *opaque
, hwaddr addr
,
1012 uint64_t value
, unsigned size
)
1014 SerialState
*s
= opaque
;
1016 serial_ioport_write(s
, addr
>> s
->it_shift
, value
, 1);
1019 static const MemoryRegionOps serial_mm_ops
[3] = {
1020 [DEVICE_NATIVE_ENDIAN
] = {
1021 .read
= serial_mm_read
,
1022 .write
= serial_mm_write
,
1023 .endianness
= DEVICE_NATIVE_ENDIAN
,
1024 .valid
.max_access_size
= 8,
1025 .impl
.max_access_size
= 8,
1027 [DEVICE_LITTLE_ENDIAN
] = {
1028 .read
= serial_mm_read
,
1029 .write
= serial_mm_write
,
1030 .endianness
= DEVICE_LITTLE_ENDIAN
,
1031 .valid
.max_access_size
= 8,
1032 .impl
.max_access_size
= 8,
1034 [DEVICE_BIG_ENDIAN
] = {
1035 .read
= serial_mm_read
,
1036 .write
= serial_mm_write
,
1037 .endianness
= DEVICE_BIG_ENDIAN
,
1038 .valid
.max_access_size
= 8,
1039 .impl
.max_access_size
= 8,
1043 SerialState
*serial_mm_init(MemoryRegion
*address_space
,
1044 hwaddr base
, int it_shift
,
1045 qemu_irq irq
, int baudbase
,
1046 Chardev
*chr
, enum device_endian end
)
1050 s
= g_malloc0(sizeof(SerialState
));
1052 s
->it_shift
= it_shift
;
1054 s
->baudbase
= baudbase
;
1055 qemu_chr_fe_init(&s
->chr
, chr
, &error_abort
);
1057 serial_realize_core(s
, &error_fatal
);
1058 vmstate_register(NULL
, base
, &vmstate_serial
, s
);
1060 memory_region_init_io(&s
->io
, NULL
, &serial_mm_ops
[end
], s
,
1061 "serial", 8 << it_shift
);
1062 memory_region_add_subregion(address_space
, base
, &s
->io
);