2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
30 #include "qemu/option.h"
31 #include "qemu/config-file.h"
32 #include "qapi/qmp/qerror.h"
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "sysemu/arch_init.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/cpu/icc_bus.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
53 /* Cache topology CPUID constants: */
55 /* CPUID Leaf 2 Descriptors */
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
62 /* CPUID Leaf 4 constants: */
65 #define CPUID_4_TYPE_DCACHE 1
66 #define CPUID_4_TYPE_ICACHE 2
67 #define CPUID_4_TYPE_UNIFIED 3
69 #define CPUID_4_LEVEL(l) ((l) << 5)
71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72 #define CPUID_4_FULLY_ASSOC (1 << 9)
75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
76 #define CPUID_4_INCLUSIVE (1 << 1)
77 #define CPUID_4_COMPLEX_IDX (1 << 2)
79 #define ASSOC_FULL 0xFF
81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
96 /* Definitions of the hardcoded cache entries we expose: */
99 #define L1D_LINE_SIZE 64
100 #define L1D_ASSOCIATIVITY 8
102 #define L1D_PARTITIONS 1
103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106 #define L1D_LINES_PER_TAG 1
107 #define L1D_SIZE_KB_AMD 64
108 #define L1D_ASSOCIATIVITY_AMD 2
110 /* L1 instruction cache: */
111 #define L1I_LINE_SIZE 64
112 #define L1I_ASSOCIATIVITY 8
114 #define L1I_PARTITIONS 1
115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118 #define L1I_LINES_PER_TAG 1
119 #define L1I_SIZE_KB_AMD 64
120 #define L1I_ASSOCIATIVITY_AMD 2
122 /* Level 2 unified cache: */
123 #define L2_LINE_SIZE 64
124 #define L2_ASSOCIATIVITY 16
126 #define L2_PARTITIONS 1
127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131 #define L2_LINES_PER_TAG 1
132 #define L2_SIZE_KB_AMD 512
135 #define L3_SIZE_KB 0 /* disabled */
136 #define L3_ASSOCIATIVITY 0 /* disabled */
137 #define L3_LINES_PER_TAG 0 /* disabled */
138 #define L3_LINE_SIZE 0 /* disabled */
140 /* TLB definitions: */
142 #define L1_DTLB_2M_ASSOC 1
143 #define L1_DTLB_2M_ENTRIES 255
144 #define L1_DTLB_4K_ASSOC 1
145 #define L1_DTLB_4K_ENTRIES 255
147 #define L1_ITLB_2M_ASSOC 1
148 #define L1_ITLB_2M_ENTRIES 255
149 #define L1_ITLB_4K_ASSOC 1
150 #define L1_ITLB_4K_ENTRIES 255
152 #define L2_DTLB_2M_ASSOC 0 /* disabled */
153 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
154 #define L2_DTLB_4K_ASSOC 4
155 #define L2_DTLB_4K_ENTRIES 512
157 #define L2_ITLB_2M_ASSOC 0 /* disabled */
158 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
159 #define L2_ITLB_4K_ASSOC 4
160 #define L2_ITLB_4K_ENTRIES 512
164 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
165 uint32_t vendor2
, uint32_t vendor3
)
168 for (i
= 0; i
< 4; i
++) {
169 dst
[i
] = vendor1
>> (8 * i
);
170 dst
[i
+ 4] = vendor2
>> (8 * i
);
171 dst
[i
+ 8] = vendor3
>> (8 * i
);
173 dst
[CPUID_VENDOR_SZ
] = '\0';
176 /* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
180 static const char *feature_name
[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL
, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
190 static const char *ext_feature_name
[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL
,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL
, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
200 /* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
205 static const char *ext2_feature_name
[] = {
206 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
207 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
208 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
209 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
210 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
211 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
212 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL
, "lm|i64", "3dnowext", "3dnow",
215 static const char *ext3_feature_name
[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL
, "lwp",
220 "fma4", "tce", NULL
, "nodeid_msr",
221 NULL
, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL
, NULL
, NULL
,
223 NULL
, NULL
, NULL
, NULL
,
226 static const char *ext4_feature_name
[] = {
227 NULL
, NULL
, "xstore", "xstore-en",
228 NULL
, NULL
, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL
, NULL
,
231 NULL
, NULL
, NULL
, NULL
,
232 NULL
, NULL
, NULL
, NULL
,
233 NULL
, NULL
, NULL
, NULL
,
234 NULL
, NULL
, NULL
, NULL
,
237 static const char *kvm_feature_name
[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL
, NULL
, NULL
, NULL
,
241 NULL
, NULL
, NULL
, NULL
,
242 NULL
, NULL
, NULL
, NULL
,
243 NULL
, NULL
, NULL
, NULL
,
244 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
245 NULL
, NULL
, NULL
, NULL
,
248 static const char *svm_feature_name
[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL
, NULL
, "pause_filter", NULL
,
252 "pfthreshold", NULL
, NULL
, NULL
,
253 NULL
, NULL
, NULL
, NULL
,
254 NULL
, NULL
, NULL
, NULL
,
255 NULL
, NULL
, NULL
, NULL
,
256 NULL
, NULL
, NULL
, NULL
,
259 static const char *cpuid_7_0_ebx_feature_name
[] = {
260 "fsgsbase", "tsc_adjust", NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, "mpx", NULL
,
262 "avx512f", NULL
, "rdseed", "adx", "smap", NULL
, NULL
, NULL
,
263 NULL
, NULL
, "avx512pf", "avx512er", "avx512cd", NULL
, NULL
, NULL
,
266 static const char *cpuid_apm_edx_feature_name
[] = {
267 NULL
, NULL
, NULL
, NULL
,
268 NULL
, NULL
, NULL
, NULL
,
269 "invtsc", NULL
, NULL
, NULL
,
270 NULL
, NULL
, NULL
, NULL
,
271 NULL
, NULL
, NULL
, NULL
,
272 NULL
, NULL
, NULL
, NULL
,
273 NULL
, NULL
, NULL
, NULL
,
274 NULL
, NULL
, NULL
, NULL
,
277 static const char *cpuid_xsave_feature_name
[] = {
278 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
279 NULL
, NULL
, NULL
, NULL
,
280 NULL
, NULL
, NULL
, NULL
,
281 NULL
, NULL
, NULL
, NULL
,
282 NULL
, NULL
, NULL
, NULL
,
283 NULL
, NULL
, NULL
, NULL
,
284 NULL
, NULL
, NULL
, NULL
,
285 NULL
, NULL
, NULL
, NULL
,
288 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
289 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
290 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
291 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
292 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
293 CPUID_PSE36 | CPUID_FXSR)
294 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
295 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
296 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
297 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
298 CPUID_PAE | CPUID_SEP | CPUID_APIC)
300 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
301 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
302 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
303 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
304 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
305 /* partly implemented:
306 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
308 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
309 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
310 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
311 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
312 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
314 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
315 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
316 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
317 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
318 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
322 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
324 #define TCG_EXT2_X86_64_FEATURES 0
327 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
328 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
329 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
330 TCG_EXT2_X86_64_FEATURES)
331 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
332 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
333 #define TCG_EXT4_FEATURES 0
334 #define TCG_SVM_FEATURES 0
335 #define TCG_KVM_FEATURES 0
336 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
337 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
339 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
340 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
341 CPUID_7_0_EBX_RDSEED */
342 #define TCG_APM_FEATURES 0
345 typedef struct FeatureWordInfo
{
346 const char **feat_names
;
347 uint32_t cpuid_eax
; /* Input EAX for CPUID */
348 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
349 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
350 int cpuid_reg
; /* output register (R_* constant) */
351 uint32_t tcg_features
; /* Feature flags supported by TCG */
352 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
355 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
357 .feat_names
= feature_name
,
358 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
359 .tcg_features
= TCG_FEATURES
,
362 .feat_names
= ext_feature_name
,
363 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
364 .tcg_features
= TCG_EXT_FEATURES
,
366 [FEAT_8000_0001_EDX
] = {
367 .feat_names
= ext2_feature_name
,
368 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
369 .tcg_features
= TCG_EXT2_FEATURES
,
371 [FEAT_8000_0001_ECX
] = {
372 .feat_names
= ext3_feature_name
,
373 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
374 .tcg_features
= TCG_EXT3_FEATURES
,
376 [FEAT_C000_0001_EDX
] = {
377 .feat_names
= ext4_feature_name
,
378 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
379 .tcg_features
= TCG_EXT4_FEATURES
,
382 .feat_names
= kvm_feature_name
,
383 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
384 .tcg_features
= TCG_KVM_FEATURES
,
387 .feat_names
= svm_feature_name
,
388 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
389 .tcg_features
= TCG_SVM_FEATURES
,
392 .feat_names
= cpuid_7_0_ebx_feature_name
,
394 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
396 .tcg_features
= TCG_7_0_EBX_FEATURES
,
398 [FEAT_8000_0007_EDX
] = {
399 .feat_names
= cpuid_apm_edx_feature_name
,
400 .cpuid_eax
= 0x80000007,
402 .tcg_features
= TCG_APM_FEATURES
,
403 .unmigratable_flags
= CPUID_APM_INVTSC
,
406 .feat_names
= cpuid_xsave_feature_name
,
408 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
414 typedef struct X86RegisterInfo32
{
415 /* Name of register */
417 /* QAPI enum value register */
418 X86CPURegister32 qapi_enum
;
421 #define REGISTER(reg) \
422 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
423 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
435 typedef struct ExtSaveArea
{
436 uint32_t feature
, bits
;
437 uint32_t offset
, size
;
440 static const ExtSaveArea ext_save_areas
[] = {
441 [2] = { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
442 .offset
= 0x240, .size
= 0x100 },
443 [3] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
444 .offset
= 0x3c0, .size
= 0x40 },
445 [4] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
446 .offset
= 0x400, .size
= 0x40 },
447 [5] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
448 .offset
= 0x440, .size
= 0x40 },
449 [6] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
450 .offset
= 0x480, .size
= 0x200 },
451 [7] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
452 .offset
= 0x680, .size
= 0x400 },
455 const char *get_register_name_32(unsigned int reg
)
457 if (reg
>= CPU_NB_REGS32
) {
460 return x86_reg_info_32
[reg
].name
;
463 /* KVM-specific features that are automatically added to all CPU models
464 * when KVM is enabled.
466 static uint32_t kvm_default_features
[FEATURE_WORDS
] = {
467 [FEAT_KVM
] = (1 << KVM_FEATURE_CLOCKSOURCE
) |
468 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
469 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
470 (1 << KVM_FEATURE_ASYNC_PF
) |
471 (1 << KVM_FEATURE_STEAL_TIME
) |
472 (1 << KVM_FEATURE_PV_EOI
) |
473 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
),
474 [FEAT_1_ECX
] = CPUID_EXT_X2APIC
,
477 /* Features that are not added by default to any CPU model when KVM is enabled.
479 static uint32_t kvm_default_unset_features
[FEATURE_WORDS
] = {
480 [FEAT_1_EDX
] = CPUID_ACPI
,
481 [FEAT_1_ECX
] = CPUID_EXT_MONITOR
,
482 [FEAT_8000_0001_ECX
] = CPUID_EXT3_SVM
,
485 void x86_cpu_compat_kvm_no_autoenable(FeatureWord w
, uint32_t features
)
487 kvm_default_features
[w
] &= ~features
;
490 void x86_cpu_compat_kvm_no_autodisable(FeatureWord w
, uint32_t features
)
492 kvm_default_unset_features
[w
] &= ~features
;
496 * Returns the set of feature flags that are supported and migratable by
497 * QEMU, for a given FeatureWord.
499 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
501 FeatureWordInfo
*wi
= &feature_word_info
[w
];
505 for (i
= 0; i
< 32; i
++) {
506 uint32_t f
= 1U << i
;
507 /* If the feature name is unknown, it is not supported by QEMU yet */
508 if (!wi
->feat_names
[i
]) {
511 /* Skip features known to QEMU, but explicitly marked as unmigratable */
512 if (wi
->unmigratable_flags
& f
) {
520 void host_cpuid(uint32_t function
, uint32_t count
,
521 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
527 : "=a"(vec
[0]), "=b"(vec
[1]),
528 "=c"(vec
[2]), "=d"(vec
[3])
529 : "0"(function
), "c"(count
) : "cc");
530 #elif defined(__i386__)
531 asm volatile("pusha \n\t"
533 "mov %%eax, 0(%2) \n\t"
534 "mov %%ebx, 4(%2) \n\t"
535 "mov %%ecx, 8(%2) \n\t"
536 "mov %%edx, 12(%2) \n\t"
538 : : "a"(function
), "c"(count
), "S"(vec
)
554 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
556 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
557 * a substring. ex if !NULL points to the first char after a substring,
558 * otherwise the string is assumed to sized by a terminating nul.
559 * Return lexical ordering of *s1:*s2.
561 static int sstrcmp(const char *s1
, const char *e1
,
562 const char *s2
, const char *e2
)
565 if (!*s1
|| !*s2
|| *s1
!= *s2
)
568 if (s1
== e1
&& s2
== e2
)
577 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
578 * '|' delimited (possibly empty) strings in which case search for a match
579 * within the alternatives proceeds left to right. Return 0 for success,
580 * non-zero otherwise.
582 static int altcmp(const char *s
, const char *e
, const char *altstr
)
586 for (q
= p
= altstr
; ; ) {
587 while (*p
&& *p
!= '|')
589 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
598 /* search featureset for flag *[s..e), if found set corresponding bit in
599 * *pval and return true, otherwise return false
601 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
602 const char **featureset
)
608 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
609 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
617 static void add_flagname_to_bitmaps(const char *flagname
,
618 FeatureWordArray words
,
622 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
623 FeatureWordInfo
*wi
= &feature_word_info
[w
];
624 if (wi
->feat_names
&&
625 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
629 if (w
== FEATURE_WORDS
) {
630 error_setg(errp
, "CPU feature %s not found", flagname
);
634 /* CPU class name definitions: */
636 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
637 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
639 /* Return type name for a given CPU model name
640 * Caller is responsible for freeing the returned string.
642 static char *x86_cpu_type_name(const char *model_name
)
644 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
647 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
652 if (cpu_model
== NULL
) {
656 typename
= x86_cpu_type_name(cpu_model
);
657 oc
= object_class_by_name(typename
);
662 struct X86CPUDefinition
{
667 /* vendor is zero-terminated, 12 character ASCII string */
668 char vendor
[CPUID_VENDOR_SZ
+ 1];
672 FeatureWordArray features
;
674 bool cache_info_passthrough
;
677 static X86CPUDefinition builtin_x86_defs
[] = {
681 .vendor
= CPUID_VENDOR_AMD
,
685 .features
[FEAT_1_EDX
] =
687 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
689 .features
[FEAT_1_ECX
] =
690 CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
691 .features
[FEAT_8000_0001_EDX
] =
692 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
693 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
694 .features
[FEAT_8000_0001_ECX
] =
695 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
696 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
697 .xlevel
= 0x8000000A,
702 .vendor
= CPUID_VENDOR_AMD
,
706 /* Missing: CPUID_HT */
707 .features
[FEAT_1_EDX
] =
709 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
710 CPUID_PSE36
| CPUID_VME
,
711 .features
[FEAT_1_ECX
] =
712 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
714 .features
[FEAT_8000_0001_EDX
] =
715 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
716 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
717 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
718 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
719 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
721 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
722 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
723 .features
[FEAT_8000_0001_ECX
] =
724 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
725 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
726 /* Missing: CPUID_SVM_LBRV */
727 .features
[FEAT_SVM
] =
729 .xlevel
= 0x8000001A,
730 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
735 .vendor
= CPUID_VENDOR_INTEL
,
739 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
740 .features
[FEAT_1_EDX
] =
742 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
743 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
744 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
745 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
746 .features
[FEAT_1_ECX
] =
747 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
749 .features
[FEAT_8000_0001_EDX
] =
750 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
751 .features
[FEAT_8000_0001_ECX
] =
753 .xlevel
= 0x80000008,
754 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
759 .vendor
= CPUID_VENDOR_INTEL
,
763 /* Missing: CPUID_HT */
764 .features
[FEAT_1_EDX
] =
765 PPRO_FEATURES
| CPUID_VME
|
766 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
768 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
769 .features
[FEAT_1_ECX
] =
770 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
771 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
772 .features
[FEAT_8000_0001_EDX
] =
773 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
774 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
775 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
776 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
777 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
778 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
779 .features
[FEAT_8000_0001_ECX
] =
781 .xlevel
= 0x80000008,
782 .model_id
= "Common KVM processor"
787 .vendor
= CPUID_VENDOR_INTEL
,
791 .features
[FEAT_1_EDX
] =
793 .features
[FEAT_1_ECX
] =
794 CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
795 .xlevel
= 0x80000004,
800 .vendor
= CPUID_VENDOR_INTEL
,
804 .features
[FEAT_1_EDX
] =
805 PPRO_FEATURES
| CPUID_VME
|
806 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
807 .features
[FEAT_1_ECX
] =
809 .features
[FEAT_8000_0001_EDX
] =
810 PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
811 .features
[FEAT_8000_0001_ECX
] =
813 .xlevel
= 0x80000008,
814 .model_id
= "Common 32-bit KVM processor"
819 .vendor
= CPUID_VENDOR_INTEL
,
823 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
824 .features
[FEAT_1_EDX
] =
825 PPRO_FEATURES
| CPUID_VME
|
826 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
828 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
829 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
830 .features
[FEAT_1_ECX
] =
831 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
832 .features
[FEAT_8000_0001_EDX
] =
834 .xlevel
= 0x80000008,
835 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
840 .vendor
= CPUID_VENDOR_INTEL
,
844 .features
[FEAT_1_EDX
] =
851 .vendor
= CPUID_VENDOR_INTEL
,
855 .features
[FEAT_1_EDX
] =
862 .vendor
= CPUID_VENDOR_INTEL
,
866 .features
[FEAT_1_EDX
] =
873 .vendor
= CPUID_VENDOR_INTEL
,
877 .features
[FEAT_1_EDX
] =
884 .vendor
= CPUID_VENDOR_AMD
,
888 .features
[FEAT_1_EDX
] =
889 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
891 .features
[FEAT_8000_0001_EDX
] =
892 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
893 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
894 .xlevel
= 0x80000008,
898 /* original is on level 10 */
900 .vendor
= CPUID_VENDOR_INTEL
,
904 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
905 .features
[FEAT_1_EDX
] =
907 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
908 CPUID_ACPI
| CPUID_SS
,
909 /* Some CPUs got no CPUID_SEP */
910 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
912 .features
[FEAT_1_ECX
] =
913 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
915 .features
[FEAT_8000_0001_EDX
] =
916 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
918 .features
[FEAT_8000_0001_ECX
] =
920 .xlevel
= 0x8000000A,
921 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
926 .vendor
= CPUID_VENDOR_INTEL
,
930 .features
[FEAT_1_EDX
] =
931 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
932 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
933 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
934 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
935 CPUID_DE
| CPUID_FP87
,
936 .features
[FEAT_1_ECX
] =
937 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
938 .features
[FEAT_8000_0001_EDX
] =
939 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
940 .features
[FEAT_8000_0001_ECX
] =
942 .xlevel
= 0x8000000A,
943 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
948 .vendor
= CPUID_VENDOR_INTEL
,
952 .features
[FEAT_1_EDX
] =
953 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
954 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
955 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
956 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
957 CPUID_DE
| CPUID_FP87
,
958 .features
[FEAT_1_ECX
] =
959 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
961 .features
[FEAT_8000_0001_EDX
] =
962 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
963 .features
[FEAT_8000_0001_ECX
] =
965 .xlevel
= 0x8000000A,
966 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
971 .vendor
= CPUID_VENDOR_INTEL
,
975 .features
[FEAT_1_EDX
] =
976 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
977 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
978 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
979 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
980 CPUID_DE
| CPUID_FP87
,
981 .features
[FEAT_1_ECX
] =
982 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
983 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
984 .features
[FEAT_8000_0001_EDX
] =
985 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
986 .features
[FEAT_8000_0001_ECX
] =
988 .xlevel
= 0x8000000A,
989 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
994 .vendor
= CPUID_VENDOR_INTEL
,
998 .features
[FEAT_1_EDX
] =
999 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1000 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1001 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1002 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1003 CPUID_DE
| CPUID_FP87
,
1004 .features
[FEAT_1_ECX
] =
1005 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1006 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1007 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1008 .features
[FEAT_8000_0001_EDX
] =
1009 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1010 .features
[FEAT_8000_0001_ECX
] =
1012 .xlevel
= 0x8000000A,
1013 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1016 .name
= "SandyBridge",
1018 .vendor
= CPUID_VENDOR_INTEL
,
1022 .features
[FEAT_1_EDX
] =
1023 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1024 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1025 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1026 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1027 CPUID_DE
| CPUID_FP87
,
1028 .features
[FEAT_1_ECX
] =
1029 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1030 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1031 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1032 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1034 .features
[FEAT_8000_0001_EDX
] =
1035 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1037 .features
[FEAT_8000_0001_ECX
] =
1039 .features
[FEAT_XSAVE
] =
1040 CPUID_XSAVE_XSAVEOPT
,
1041 .xlevel
= 0x8000000A,
1042 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1045 .name
= "IvyBridge",
1047 .vendor
= CPUID_VENDOR_INTEL
,
1051 .features
[FEAT_1_EDX
] =
1052 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1053 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1054 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1055 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1056 CPUID_DE
| CPUID_FP87
,
1057 .features
[FEAT_1_ECX
] =
1058 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1059 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1060 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1061 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1062 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1063 .features
[FEAT_7_0_EBX
] =
1064 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1066 .features
[FEAT_8000_0001_EDX
] =
1067 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1069 .features
[FEAT_8000_0001_ECX
] =
1071 .features
[FEAT_XSAVE
] =
1072 CPUID_XSAVE_XSAVEOPT
,
1073 .xlevel
= 0x8000000A,
1074 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1079 .vendor
= CPUID_VENDOR_INTEL
,
1083 .features
[FEAT_1_EDX
] =
1084 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1085 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1086 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1087 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1088 CPUID_DE
| CPUID_FP87
,
1089 .features
[FEAT_1_ECX
] =
1090 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1091 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1092 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1093 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1094 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1095 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1096 .features
[FEAT_8000_0001_EDX
] =
1097 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1099 .features
[FEAT_8000_0001_ECX
] =
1101 .features
[FEAT_7_0_EBX
] =
1102 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1103 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1104 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1106 .features
[FEAT_XSAVE
] =
1107 CPUID_XSAVE_XSAVEOPT
,
1108 .xlevel
= 0x8000000A,
1109 .model_id
= "Intel Core Processor (Haswell)",
1112 .name
= "Broadwell",
1114 .vendor
= CPUID_VENDOR_INTEL
,
1118 .features
[FEAT_1_EDX
] =
1119 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1120 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1121 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1122 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1123 CPUID_DE
| CPUID_FP87
,
1124 .features
[FEAT_1_ECX
] =
1125 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1126 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1127 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1128 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1129 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1130 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1131 .features
[FEAT_8000_0001_EDX
] =
1132 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1134 .features
[FEAT_8000_0001_ECX
] =
1135 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1136 .features
[FEAT_7_0_EBX
] =
1137 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1138 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1139 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1140 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1142 .features
[FEAT_XSAVE
] =
1143 CPUID_XSAVE_XSAVEOPT
,
1144 .xlevel
= 0x8000000A,
1145 .model_id
= "Intel Core Processor (Broadwell)",
1148 .name
= "Opteron_G1",
1150 .vendor
= CPUID_VENDOR_AMD
,
1154 .features
[FEAT_1_EDX
] =
1155 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1156 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1157 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1158 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1159 CPUID_DE
| CPUID_FP87
,
1160 .features
[FEAT_1_ECX
] =
1162 .features
[FEAT_8000_0001_EDX
] =
1163 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1164 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1165 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1166 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1167 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1168 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1169 .xlevel
= 0x80000008,
1170 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1173 .name
= "Opteron_G2",
1175 .vendor
= CPUID_VENDOR_AMD
,
1179 .features
[FEAT_1_EDX
] =
1180 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1181 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1182 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1183 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1184 CPUID_DE
| CPUID_FP87
,
1185 .features
[FEAT_1_ECX
] =
1186 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1187 .features
[FEAT_8000_0001_EDX
] =
1188 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1189 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1190 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1191 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1192 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1193 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1194 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1195 .features
[FEAT_8000_0001_ECX
] =
1196 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1197 .xlevel
= 0x80000008,
1198 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1201 .name
= "Opteron_G3",
1203 .vendor
= CPUID_VENDOR_AMD
,
1207 .features
[FEAT_1_EDX
] =
1208 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1209 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1210 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1211 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1212 CPUID_DE
| CPUID_FP87
,
1213 .features
[FEAT_1_ECX
] =
1214 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1216 .features
[FEAT_8000_0001_EDX
] =
1217 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1218 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1219 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1220 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1221 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1222 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1223 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1224 .features
[FEAT_8000_0001_ECX
] =
1225 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1226 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1227 .xlevel
= 0x80000008,
1228 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1231 .name
= "Opteron_G4",
1233 .vendor
= CPUID_VENDOR_AMD
,
1237 .features
[FEAT_1_EDX
] =
1238 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1239 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1240 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1241 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1242 CPUID_DE
| CPUID_FP87
,
1243 .features
[FEAT_1_ECX
] =
1244 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1245 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1246 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1248 .features
[FEAT_8000_0001_EDX
] =
1249 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1250 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1251 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1252 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1253 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1254 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1255 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1256 .features
[FEAT_8000_0001_ECX
] =
1257 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1258 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1259 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1262 .xlevel
= 0x8000001A,
1263 .model_id
= "AMD Opteron 62xx class CPU",
1266 .name
= "Opteron_G5",
1268 .vendor
= CPUID_VENDOR_AMD
,
1272 .features
[FEAT_1_EDX
] =
1273 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1274 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1275 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1276 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1277 CPUID_DE
| CPUID_FP87
,
1278 .features
[FEAT_1_ECX
] =
1279 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1280 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1281 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1282 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1283 .features
[FEAT_8000_0001_EDX
] =
1284 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1285 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1286 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1287 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1288 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1289 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1290 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1291 .features
[FEAT_8000_0001_ECX
] =
1292 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1293 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1294 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1297 .xlevel
= 0x8000001A,
1298 .model_id
= "AMD Opteron 63xx class CPU",
1303 * x86_cpu_compat_set_features:
1304 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1305 * @w: Identifies the feature word to be changed.
1306 * @feat_add: Feature bits to be added to feature word
1307 * @feat_remove: Feature bits to be removed from feature word
1309 * Change CPU model feature bits for compatibility.
1311 * This function may be used by machine-type compatibility functions
1312 * to enable or disable feature bits on specific CPU models.
1314 void x86_cpu_compat_set_features(const char *cpu_model
, FeatureWord w
,
1315 uint32_t feat_add
, uint32_t feat_remove
)
1317 X86CPUDefinition
*def
;
1319 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1320 def
= &builtin_x86_defs
[i
];
1321 if (!cpu_model
|| !strcmp(cpu_model
, def
->name
)) {
1322 def
->features
[w
] |= feat_add
;
1323 def
->features
[w
] &= ~feat_remove
;
1328 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1329 bool migratable_only
);
1333 static int cpu_x86_fill_model_id(char *str
)
1335 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1338 for (i
= 0; i
< 3; i
++) {
1339 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1340 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1341 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1342 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1343 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1348 static X86CPUDefinition host_cpudef
;
1350 static Property host_x86_cpu_properties
[] = {
1351 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1352 DEFINE_PROP_END_OF_LIST()
1355 /* class_init for the "host" CPU model
1357 * This function may be called before KVM is initialized.
1359 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1361 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1362 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1363 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1365 xcc
->kvm_required
= true;
1367 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1368 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
1370 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1371 host_cpudef
.family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1372 host_cpudef
.model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1373 host_cpudef
.stepping
= eax
& 0x0F;
1375 cpu_x86_fill_model_id(host_cpudef
.model_id
);
1377 xcc
->cpu_def
= &host_cpudef
;
1378 host_cpudef
.cache_info_passthrough
= true;
1380 /* level, xlevel, xlevel2, and the feature words are initialized on
1381 * instance_init, because they require KVM to be initialized.
1384 dc
->props
= host_x86_cpu_properties
;
1387 static void host_x86_cpu_initfn(Object
*obj
)
1389 X86CPU
*cpu
= X86_CPU(obj
);
1390 CPUX86State
*env
= &cpu
->env
;
1391 KVMState
*s
= kvm_state
;
1393 assert(kvm_enabled());
1395 /* We can't fill the features array here because we don't know yet if
1396 * "migratable" is true or false.
1398 cpu
->host_features
= true;
1400 env
->cpuid_level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1401 env
->cpuid_xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1402 env
->cpuid_xlevel2
= kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1404 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1407 static const TypeInfo host_x86_cpu_type_info
= {
1408 .name
= X86_CPU_TYPE_NAME("host"),
1409 .parent
= TYPE_X86_CPU
,
1410 .instance_init
= host_x86_cpu_initfn
,
1411 .class_init
= host_x86_cpu_class_init
,
1416 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1418 FeatureWordInfo
*f
= &feature_word_info
[w
];
1421 for (i
= 0; i
< 32; ++i
) {
1422 if (1 << i
& mask
) {
1423 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1425 fprintf(stderr
, "warning: %s doesn't support requested feature: "
1426 "CPUID.%02XH:%s%s%s [bit %d]\n",
1427 kvm_enabled() ? "host" : "TCG",
1429 f
->feat_names
[i
] ? "." : "",
1430 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1435 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
1436 const char *name
, Error
**errp
)
1438 X86CPU
*cpu
= X86_CPU(obj
);
1439 CPUX86State
*env
= &cpu
->env
;
1442 value
= (env
->cpuid_version
>> 8) & 0xf;
1444 value
+= (env
->cpuid_version
>> 20) & 0xff;
1446 visit_type_int(v
, &value
, name
, errp
);
1449 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
1450 const char *name
, Error
**errp
)
1452 X86CPU
*cpu
= X86_CPU(obj
);
1453 CPUX86State
*env
= &cpu
->env
;
1454 const int64_t min
= 0;
1455 const int64_t max
= 0xff + 0xf;
1456 Error
*local_err
= NULL
;
1459 visit_type_int(v
, &value
, name
, &local_err
);
1461 error_propagate(errp
, local_err
);
1464 if (value
< min
|| value
> max
) {
1465 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1466 name
? name
: "null", value
, min
, max
);
1470 env
->cpuid_version
&= ~0xff00f00;
1472 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1474 env
->cpuid_version
|= value
<< 8;
1478 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
1479 const char *name
, Error
**errp
)
1481 X86CPU
*cpu
= X86_CPU(obj
);
1482 CPUX86State
*env
= &cpu
->env
;
1485 value
= (env
->cpuid_version
>> 4) & 0xf;
1486 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1487 visit_type_int(v
, &value
, name
, errp
);
1490 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
1491 const char *name
, Error
**errp
)
1493 X86CPU
*cpu
= X86_CPU(obj
);
1494 CPUX86State
*env
= &cpu
->env
;
1495 const int64_t min
= 0;
1496 const int64_t max
= 0xff;
1497 Error
*local_err
= NULL
;
1500 visit_type_int(v
, &value
, name
, &local_err
);
1502 error_propagate(errp
, local_err
);
1505 if (value
< min
|| value
> max
) {
1506 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1507 name
? name
: "null", value
, min
, max
);
1511 env
->cpuid_version
&= ~0xf00f0;
1512 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1515 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1516 void *opaque
, const char *name
,
1519 X86CPU
*cpu
= X86_CPU(obj
);
1520 CPUX86State
*env
= &cpu
->env
;
1523 value
= env
->cpuid_version
& 0xf;
1524 visit_type_int(v
, &value
, name
, errp
);
1527 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1528 void *opaque
, const char *name
,
1531 X86CPU
*cpu
= X86_CPU(obj
);
1532 CPUX86State
*env
= &cpu
->env
;
1533 const int64_t min
= 0;
1534 const int64_t max
= 0xf;
1535 Error
*local_err
= NULL
;
1538 visit_type_int(v
, &value
, name
, &local_err
);
1540 error_propagate(errp
, local_err
);
1543 if (value
< min
|| value
> max
) {
1544 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1545 name
? name
: "null", value
, min
, max
);
1549 env
->cpuid_version
&= ~0xf;
1550 env
->cpuid_version
|= value
& 0xf;
1553 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
1554 const char *name
, Error
**errp
)
1556 X86CPU
*cpu
= X86_CPU(obj
);
1558 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1561 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
1562 const char *name
, Error
**errp
)
1564 X86CPU
*cpu
= X86_CPU(obj
);
1566 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1569 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1570 const char *name
, Error
**errp
)
1572 X86CPU
*cpu
= X86_CPU(obj
);
1574 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1577 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1578 const char *name
, Error
**errp
)
1580 X86CPU
*cpu
= X86_CPU(obj
);
1582 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1585 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1587 X86CPU
*cpu
= X86_CPU(obj
);
1588 CPUX86State
*env
= &cpu
->env
;
1591 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
1592 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1593 env
->cpuid_vendor3
);
1597 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1600 X86CPU
*cpu
= X86_CPU(obj
);
1601 CPUX86State
*env
= &cpu
->env
;
1604 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1605 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1610 env
->cpuid_vendor1
= 0;
1611 env
->cpuid_vendor2
= 0;
1612 env
->cpuid_vendor3
= 0;
1613 for (i
= 0; i
< 4; i
++) {
1614 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1615 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1616 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1620 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1622 X86CPU
*cpu
= X86_CPU(obj
);
1623 CPUX86State
*env
= &cpu
->env
;
1627 value
= g_malloc(48 + 1);
1628 for (i
= 0; i
< 48; i
++) {
1629 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1635 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1638 X86CPU
*cpu
= X86_CPU(obj
);
1639 CPUX86State
*env
= &cpu
->env
;
1642 if (model_id
== NULL
) {
1645 len
= strlen(model_id
);
1646 memset(env
->cpuid_model
, 0, 48);
1647 for (i
= 0; i
< 48; i
++) {
1651 c
= (uint8_t)model_id
[i
];
1653 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1657 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1658 const char *name
, Error
**errp
)
1660 X86CPU
*cpu
= X86_CPU(obj
);
1663 value
= cpu
->env
.tsc_khz
* 1000;
1664 visit_type_int(v
, &value
, name
, errp
);
1667 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1668 const char *name
, Error
**errp
)
1670 X86CPU
*cpu
= X86_CPU(obj
);
1671 const int64_t min
= 0;
1672 const int64_t max
= INT64_MAX
;
1673 Error
*local_err
= NULL
;
1676 visit_type_int(v
, &value
, name
, &local_err
);
1678 error_propagate(errp
, local_err
);
1681 if (value
< min
|| value
> max
) {
1682 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1683 name
? name
: "null", value
, min
, max
);
1687 cpu
->env
.tsc_khz
= value
/ 1000;
1690 static void x86_cpuid_get_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1691 const char *name
, Error
**errp
)
1693 X86CPU
*cpu
= X86_CPU(obj
);
1694 int64_t value
= cpu
->env
.cpuid_apic_id
;
1696 visit_type_int(v
, &value
, name
, errp
);
1699 static void x86_cpuid_set_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1700 const char *name
, Error
**errp
)
1702 X86CPU
*cpu
= X86_CPU(obj
);
1703 DeviceState
*dev
= DEVICE(obj
);
1704 const int64_t min
= 0;
1705 const int64_t max
= UINT32_MAX
;
1706 Error
*error
= NULL
;
1709 if (dev
->realized
) {
1710 error_setg(errp
, "Attempt to set property '%s' on '%s' after "
1711 "it was realized", name
, object_get_typename(obj
));
1715 visit_type_int(v
, &value
, name
, &error
);
1717 error_propagate(errp
, error
);
1720 if (value
< min
|| value
> max
) {
1721 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1722 " (minimum: %" PRId64
", maximum: %" PRId64
")" ,
1723 object_get_typename(obj
), name
, value
, min
, max
);
1727 if ((value
!= cpu
->env
.cpuid_apic_id
) && cpu_exists(value
)) {
1728 error_setg(errp
, "CPU with APIC ID %" PRIi64
" exists", value
);
1731 cpu
->env
.cpuid_apic_id
= value
;
1734 /* Generic getter for "feature-words" and "filtered-features" properties */
1735 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
, void *opaque
,
1736 const char *name
, Error
**errp
)
1738 uint32_t *array
= (uint32_t *)opaque
;
1741 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
1742 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
1743 X86CPUFeatureWordInfoList
*list
= NULL
;
1745 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1746 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1747 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
1748 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
1749 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
1750 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
1751 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
1752 qwi
->features
= array
[w
];
1754 /* List will be in reverse order, but order shouldn't matter */
1755 list_entries
[w
].next
= list
;
1756 list_entries
[w
].value
= &word_infos
[w
];
1757 list
= &list_entries
[w
];
1760 visit_type_X86CPUFeatureWordInfoList(v
, &list
, "feature-words", &err
);
1761 error_propagate(errp
, err
);
1764 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1765 const char *name
, Error
**errp
)
1767 X86CPU
*cpu
= X86_CPU(obj
);
1768 int64_t value
= cpu
->hyperv_spinlock_attempts
;
1770 visit_type_int(v
, &value
, name
, errp
);
1773 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1774 const char *name
, Error
**errp
)
1776 const int64_t min
= 0xFFF;
1777 const int64_t max
= UINT_MAX
;
1778 X86CPU
*cpu
= X86_CPU(obj
);
1782 visit_type_int(v
, &value
, name
, &err
);
1784 error_propagate(errp
, err
);
1788 if (value
< min
|| value
> max
) {
1789 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1790 " (minimum: %" PRId64
", maximum: %" PRId64
")",
1791 object_get_typename(obj
), name
? name
: "null",
1795 cpu
->hyperv_spinlock_attempts
= value
;
1798 static PropertyInfo qdev_prop_spinlocks
= {
1800 .get
= x86_get_hv_spinlocks
,
1801 .set
= x86_set_hv_spinlocks
,
1804 /* Convert all '_' in a feature string option name to '-', to make feature
1805 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1807 static inline void feat2prop(char *s
)
1809 while ((s
= strchr(s
, '_'))) {
1814 /* Parse "+feature,-feature,feature=foo" CPU feature string
1816 static void x86_cpu_parse_featurestr(CPUState
*cs
, char *features
,
1819 X86CPU
*cpu
= X86_CPU(cs
);
1820 char *featurestr
; /* Single 'key=value" string being parsed */
1822 /* Features to be added */
1823 FeatureWordArray plus_features
= { 0 };
1824 /* Features to be removed */
1825 FeatureWordArray minus_features
= { 0 };
1827 CPUX86State
*env
= &cpu
->env
;
1828 Error
*local_err
= NULL
;
1830 featurestr
= features
? strtok(features
, ",") : NULL
;
1832 while (featurestr
) {
1834 if (featurestr
[0] == '+') {
1835 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
, &local_err
);
1836 } else if (featurestr
[0] == '-') {
1837 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
, &local_err
);
1838 } else if ((val
= strchr(featurestr
, '='))) {
1840 feat2prop(featurestr
);
1841 if (!strcmp(featurestr
, "xlevel")) {
1845 numvalue
= strtoul(val
, &err
, 0);
1846 if (!*val
|| *err
) {
1847 error_setg(errp
, "bad numerical value %s", val
);
1850 if (numvalue
< 0x80000000) {
1851 error_report("xlevel value shall always be >= 0x80000000"
1852 ", fixup will be removed in future versions");
1853 numvalue
+= 0x80000000;
1855 snprintf(num
, sizeof(num
), "%" PRIu32
, numvalue
);
1856 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1857 } else if (!strcmp(featurestr
, "tsc-freq")) {
1862 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1863 STRTOSZ_DEFSUFFIX_B
, 1000);
1864 if (tsc_freq
< 0 || *err
) {
1865 error_setg(errp
, "bad numerical value %s", val
);
1868 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
1869 object_property_parse(OBJECT(cpu
), num
, "tsc-frequency",
1871 } else if (!strcmp(featurestr
, "hv-spinlocks")) {
1873 const int min
= 0xFFF;
1875 numvalue
= strtoul(val
, &err
, 0);
1876 if (!*val
|| *err
) {
1877 error_setg(errp
, "bad numerical value %s", val
);
1880 if (numvalue
< min
) {
1881 error_report("hv-spinlocks value shall always be >= 0x%x"
1882 ", fixup will be removed in future versions",
1886 snprintf(num
, sizeof(num
), "%" PRId32
, numvalue
);
1887 object_property_parse(OBJECT(cpu
), num
, featurestr
, &local_err
);
1889 object_property_parse(OBJECT(cpu
), val
, featurestr
, &local_err
);
1892 feat2prop(featurestr
);
1893 object_property_parse(OBJECT(cpu
), "on", featurestr
, &local_err
);
1896 error_propagate(errp
, local_err
);
1899 featurestr
= strtok(NULL
, ",");
1902 if (cpu
->host_features
) {
1903 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1905 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
1909 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1910 env
->features
[w
] |= plus_features
[w
];
1911 env
->features
[w
] &= ~minus_features
[w
];
1915 /* generate a composite string into buf of all cpuid names in featureset
1916 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1917 * if flags, suppress names undefined in featureset.
1919 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1920 const char **featureset
, uint32_t flags
)
1922 const char **p
= &featureset
[31];
1926 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1928 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1929 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1931 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1933 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1934 if (bufsize
<= nc
) {
1936 memcpy(b
, "...", sizeof("..."));
1945 /* generate CPU information. */
1946 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1948 X86CPUDefinition
*def
;
1952 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1953 def
= &builtin_x86_defs
[i
];
1954 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1955 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1958 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", "host",
1959 "KVM processor with all supported host features "
1960 "(only available in KVM mode)");
1963 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1964 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
1965 FeatureWordInfo
*fw
= &feature_word_info
[i
];
1967 listflags(buf
, sizeof(buf
), (uint32_t)~0, fw
->feat_names
, 1);
1968 (*cpu_fprintf
)(f
, " %s\n", buf
);
1972 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1974 CpuDefinitionInfoList
*cpu_list
= NULL
;
1975 X86CPUDefinition
*def
;
1978 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1979 CpuDefinitionInfoList
*entry
;
1980 CpuDefinitionInfo
*info
;
1982 def
= &builtin_x86_defs
[i
];
1983 info
= g_malloc0(sizeof(*info
));
1984 info
->name
= g_strdup(def
->name
);
1986 entry
= g_malloc0(sizeof(*entry
));
1987 entry
->value
= info
;
1988 entry
->next
= cpu_list
;
1995 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1996 bool migratable_only
)
1998 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2001 if (kvm_enabled()) {
2002 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2005 } else if (tcg_enabled()) {
2006 r
= wi
->tcg_features
;
2010 if (migratable_only
) {
2011 r
&= x86_cpu_get_migratable_flags(w
);
2017 * Filters CPU feature words based on host availability of each feature.
2019 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2021 static int x86_cpu_filter_features(X86CPU
*cpu
)
2023 CPUX86State
*env
= &cpu
->env
;
2027 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2028 uint32_t host_feat
=
2029 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
);
2030 uint32_t requested_features
= env
->features
[w
];
2031 env
->features
[w
] &= host_feat
;
2032 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
2033 if (cpu
->filtered_features
[w
]) {
2034 if (cpu
->check_cpuid
|| cpu
->enforce_cpuid
) {
2035 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2044 /* Load data from X86CPUDefinition
2046 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2048 CPUX86State
*env
= &cpu
->env
;
2050 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2053 object_property_set_int(OBJECT(cpu
), def
->level
, "level", errp
);
2054 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2055 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2056 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2057 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", errp
);
2058 env
->cpuid_xlevel2
= def
->xlevel2
;
2059 cpu
->cache_info_passthrough
= def
->cache_info_passthrough
;
2060 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2061 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2062 env
->features
[w
] = def
->features
[w
];
2065 /* Special cases not set in the X86CPUDefinition structs: */
2066 if (kvm_enabled()) {
2068 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2069 env
->features
[w
] |= kvm_default_features
[w
];
2070 env
->features
[w
] &= ~kvm_default_unset_features
[w
];
2074 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2076 /* sysenter isn't supported in compatibility mode on AMD,
2077 * syscall isn't supported in compatibility mode on Intel.
2078 * Normally we advertise the actual CPU vendor, but you can
2079 * override this using the 'vendor' property if you want to use
2080 * KVM's sysenter/syscall emulation in compatibility mode and
2081 * when doing cross vendor migration
2083 vendor
= def
->vendor
;
2084 if (kvm_enabled()) {
2085 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2086 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2087 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2088 vendor
= host_vendor
;
2091 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2095 X86CPU
*cpu_x86_create(const char *cpu_model
, DeviceState
*icc_bridge
,
2101 gchar
**model_pieces
;
2102 char *name
, *features
;
2103 Error
*error
= NULL
;
2105 model_pieces
= g_strsplit(cpu_model
, ",", 2);
2106 if (!model_pieces
[0]) {
2107 error_setg(&error
, "Invalid/empty CPU model name");
2110 name
= model_pieces
[0];
2111 features
= model_pieces
[1];
2113 oc
= x86_cpu_class_by_name(name
);
2115 error_setg(&error
, "Unable to find CPU definition: %s", name
);
2118 xcc
= X86_CPU_CLASS(oc
);
2120 if (xcc
->kvm_required
&& !kvm_enabled()) {
2121 error_setg(&error
, "CPU model '%s' requires KVM", name
);
2125 cpu
= X86_CPU(object_new(object_class_get_name(oc
)));
2127 #ifndef CONFIG_USER_ONLY
2128 if (icc_bridge
== NULL
) {
2129 error_setg(&error
, "Invalid icc-bridge value");
2132 qdev_set_parent_bus(DEVICE(cpu
), qdev_get_child_bus(icc_bridge
, "icc"));
2133 object_unref(OBJECT(cpu
));
2136 x86_cpu_parse_featurestr(CPU(cpu
), features
, &error
);
2142 if (error
!= NULL
) {
2143 error_propagate(errp
, error
);
2145 object_unref(OBJECT(cpu
));
2149 g_strfreev(model_pieces
);
2153 X86CPU
*cpu_x86_init(const char *cpu_model
)
2155 Error
*error
= NULL
;
2158 cpu
= cpu_x86_create(cpu_model
, NULL
, &error
);
2163 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
2167 error_report("%s", error_get_pretty(error
));
2170 object_unref(OBJECT(cpu
));
2177 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2179 X86CPUDefinition
*cpudef
= data
;
2180 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2182 xcc
->cpu_def
= cpudef
;
2185 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2187 char *typename
= x86_cpu_type_name(def
->name
);
2190 .parent
= TYPE_X86_CPU
,
2191 .class_init
= x86_cpu_cpudef_class_init
,
2199 #if !defined(CONFIG_USER_ONLY)
2201 void cpu_clear_apic_feature(CPUX86State
*env
)
2203 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2206 #endif /* !CONFIG_USER_ONLY */
2208 /* Initialize list of CPU models, filling some non-static fields if necessary
2210 void x86_cpudef_setup(void)
2213 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
2215 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
2216 X86CPUDefinition
*def
= &builtin_x86_defs
[i
];
2218 /* Look for specific "cpudef" models that */
2219 /* have the QEMU version in .model_id */
2220 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
2221 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
2222 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
2223 "QEMU Virtual CPU version ");
2224 pstrcat(def
->model_id
, sizeof(def
->model_id
),
2225 qemu_get_version());
2232 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
2233 uint32_t *ecx
, uint32_t *edx
)
2235 *ebx
= env
->cpuid_vendor1
;
2236 *edx
= env
->cpuid_vendor2
;
2237 *ecx
= env
->cpuid_vendor3
;
2240 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2241 uint32_t *eax
, uint32_t *ebx
,
2242 uint32_t *ecx
, uint32_t *edx
)
2244 X86CPU
*cpu
= x86_env_get_cpu(env
);
2245 CPUState
*cs
= CPU(cpu
);
2247 /* test if maximum index reached */
2248 if (index
& 0x80000000) {
2249 if (index
> env
->cpuid_xlevel
) {
2250 if (env
->cpuid_xlevel2
> 0) {
2251 /* Handle the Centaur's CPUID instruction. */
2252 if (index
> env
->cpuid_xlevel2
) {
2253 index
= env
->cpuid_xlevel2
;
2254 } else if (index
< 0xC0000000) {
2255 index
= env
->cpuid_xlevel
;
2258 /* Intel documentation states that invalid EAX input will
2259 * return the same information as EAX=cpuid_level
2260 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2262 index
= env
->cpuid_level
;
2266 if (index
> env
->cpuid_level
)
2267 index
= env
->cpuid_level
;
2272 *eax
= env
->cpuid_level
;
2273 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
2276 *eax
= env
->cpuid_version
;
2277 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2278 *ecx
= env
->features
[FEAT_1_ECX
];
2279 *edx
= env
->features
[FEAT_1_EDX
];
2280 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2281 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2282 *edx
|= 1 << 28; /* HTT bit */
2286 /* cache info: needed for Pentium Pro compatibility */
2287 if (cpu
->cache_info_passthrough
) {
2288 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2291 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2294 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2295 (L1I_DESCRIPTOR
<< 8) | \
2299 /* cache info: needed for Core compatibility */
2300 if (cpu
->cache_info_passthrough
) {
2301 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2302 *eax
&= ~0xFC000000;
2306 case 0: /* L1 dcache info */
2307 *eax
|= CPUID_4_TYPE_DCACHE
| \
2308 CPUID_4_LEVEL(1) | \
2309 CPUID_4_SELF_INIT_LEVEL
;
2310 *ebx
= (L1D_LINE_SIZE
- 1) | \
2311 ((L1D_PARTITIONS
- 1) << 12) | \
2312 ((L1D_ASSOCIATIVITY
- 1) << 22);
2313 *ecx
= L1D_SETS
- 1;
2314 *edx
= CPUID_4_NO_INVD_SHARING
;
2316 case 1: /* L1 icache info */
2317 *eax
|= CPUID_4_TYPE_ICACHE
| \
2318 CPUID_4_LEVEL(1) | \
2319 CPUID_4_SELF_INIT_LEVEL
;
2320 *ebx
= (L1I_LINE_SIZE
- 1) | \
2321 ((L1I_PARTITIONS
- 1) << 12) | \
2322 ((L1I_ASSOCIATIVITY
- 1) << 22);
2323 *ecx
= L1I_SETS
- 1;
2324 *edx
= CPUID_4_NO_INVD_SHARING
;
2326 case 2: /* L2 cache info */
2327 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2328 CPUID_4_LEVEL(2) | \
2329 CPUID_4_SELF_INIT_LEVEL
;
2330 if (cs
->nr_threads
> 1) {
2331 *eax
|= (cs
->nr_threads
- 1) << 14;
2333 *ebx
= (L2_LINE_SIZE
- 1) | \
2334 ((L2_PARTITIONS
- 1) << 12) | \
2335 ((L2_ASSOCIATIVITY
- 1) << 22);
2337 *edx
= CPUID_4_NO_INVD_SHARING
;
2339 default: /* end of info */
2348 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2349 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2350 *eax
|= (cs
->nr_cores
- 1) << 26;
2354 /* mwait info: needed for Core compatibility */
2355 *eax
= 0; /* Smallest monitor-line size in bytes */
2356 *ebx
= 0; /* Largest monitor-line size in bytes */
2357 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2361 /* Thermal and Power Leaf */
2368 /* Structured Extended Feature Flags Enumeration Leaf */
2370 *eax
= 0; /* Maximum ECX value for sub-leaves */
2371 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2372 *ecx
= 0; /* Reserved */
2373 *edx
= 0; /* Reserved */
2382 /* Direct Cache Access Information Leaf */
2383 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2389 /* Architectural Performance Monitoring Leaf */
2390 if (kvm_enabled() && cpu
->enable_pmu
) {
2391 KVMState
*s
= cs
->kvm_state
;
2393 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2394 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2395 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2396 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2405 KVMState
*s
= cs
->kvm_state
;
2409 /* Processor Extended State */
2414 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) || !kvm_enabled()) {
2418 kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EAX
) |
2419 ((uint64_t)kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EDX
) << 32);
2423 for (i
= 2; i
< ARRAY_SIZE(ext_save_areas
); i
++) {
2424 const ExtSaveArea
*esa
= &ext_save_areas
[i
];
2425 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2426 (kvm_mask
& (1 << i
)) != 0) {
2430 *edx
|= 1 << (i
- 32);
2432 *ecx
= MAX(*ecx
, esa
->offset
+ esa
->size
);
2435 *eax
|= kvm_mask
& (XSTATE_FP
| XSTATE_SSE
);
2437 } else if (count
== 1) {
2438 *eax
= env
->features
[FEAT_XSAVE
];
2439 } else if (count
< ARRAY_SIZE(ext_save_areas
)) {
2440 const ExtSaveArea
*esa
= &ext_save_areas
[count
];
2441 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2442 (kvm_mask
& (1 << count
)) != 0) {
2450 *eax
= env
->cpuid_xlevel
;
2451 *ebx
= env
->cpuid_vendor1
;
2452 *edx
= env
->cpuid_vendor2
;
2453 *ecx
= env
->cpuid_vendor3
;
2456 *eax
= env
->cpuid_version
;
2458 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
2459 *edx
= env
->features
[FEAT_8000_0001_EDX
];
2461 /* The Linux kernel checks for the CMPLegacy bit and
2462 * discards multiple thread information if it is set.
2463 * So dont set it here for Intel to make Linux guests happy.
2465 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2466 uint32_t tebx
, tecx
, tedx
;
2467 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
2468 if (tebx
!= CPUID_VENDOR_INTEL_1
||
2469 tedx
!= CPUID_VENDOR_INTEL_2
||
2470 tecx
!= CPUID_VENDOR_INTEL_3
) {
2471 *ecx
|= 1 << 1; /* CmpLegacy bit */
2478 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2479 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2480 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2481 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2484 /* cache info (L1 cache) */
2485 if (cpu
->cache_info_passthrough
) {
2486 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2489 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
2490 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
2491 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
2492 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
2493 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
2494 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
2495 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
2496 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
2499 /* cache info (L2 cache) */
2500 if (cpu
->cache_info_passthrough
) {
2501 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2504 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
2505 (L2_DTLB_2M_ENTRIES
<< 16) | \
2506 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
2507 (L2_ITLB_2M_ENTRIES
);
2508 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
2509 (L2_DTLB_4K_ENTRIES
<< 16) | \
2510 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
2511 (L2_ITLB_4K_ENTRIES
);
2512 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
2513 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
2514 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
2515 *edx
= ((L3_SIZE_KB
/512) << 18) | \
2516 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
2517 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
2523 *edx
= env
->features
[FEAT_8000_0007_EDX
];
2526 /* virtual & phys address size in low 2 bytes. */
2527 /* XXX: This value must match the one used in the MMU code. */
2528 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2529 /* 64 bit processor */
2530 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2531 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2533 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
2534 *eax
= 0x00000024; /* 36 bits physical */
2536 *eax
= 0x00000020; /* 32 bits physical */
2542 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2543 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2547 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2548 *eax
= 0x00000001; /* SVM Revision */
2549 *ebx
= 0x00000010; /* nr of ASIDs */
2551 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2560 *eax
= env
->cpuid_xlevel2
;
2566 /* Support for VIA CPU's CPUID instruction */
2567 *eax
= env
->cpuid_version
;
2570 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2575 /* Reserved for the future, and now filled with zero */
2582 /* reserved values: zero */
2591 /* CPUClass::reset() */
2592 static void x86_cpu_reset(CPUState
*s
)
2594 X86CPU
*cpu
= X86_CPU(s
);
2595 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2596 CPUX86State
*env
= &cpu
->env
;
2599 xcc
->parent_reset(s
);
2601 memset(env
, 0, offsetof(CPUX86State
, cpuid_level
));
2605 env
->old_exception
= -1;
2607 /* init to reset state */
2609 #ifdef CONFIG_SOFTMMU
2610 env
->hflags
|= HF_SOFTMMU_MASK
;
2612 env
->hflags2
|= HF2_GIF_MASK
;
2614 cpu_x86_update_cr0(env
, 0x60000010);
2615 env
->a20_mask
= ~0x0;
2616 env
->smbase
= 0x30000;
2618 env
->idt
.limit
= 0xffff;
2619 env
->gdt
.limit
= 0xffff;
2620 env
->ldt
.limit
= 0xffff;
2621 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2622 env
->tr
.limit
= 0xffff;
2623 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2625 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2626 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2627 DESC_R_MASK
| DESC_A_MASK
);
2628 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2629 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2631 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2632 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2634 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2635 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2637 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2638 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2640 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2641 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2645 env
->regs
[R_EDX
] = env
->cpuid_version
;
2650 for (i
= 0; i
< 8; i
++) {
2653 cpu_set_fpuc(env
, 0x37f);
2655 env
->mxcsr
= 0x1f80;
2656 env
->xstate_bv
= XSTATE_FP
| XSTATE_SSE
;
2658 env
->pat
= 0x0007040600070406ULL
;
2659 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2661 memset(env
->dr
, 0, sizeof(env
->dr
));
2662 env
->dr
[6] = DR6_FIXED_1
;
2663 env
->dr
[7] = DR7_FIXED_1
;
2664 cpu_breakpoint_remove_all(s
, BP_CPU
);
2665 cpu_watchpoint_remove_all(s
, BP_CPU
);
2670 * SDM 11.11.5 requires:
2671 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2672 * - IA32_MTRR_PHYSMASKn.V = 0
2673 * All other bits are undefined. For simplification, zero it all.
2675 env
->mtrr_deftype
= 0;
2676 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
2677 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
2679 #if !defined(CONFIG_USER_ONLY)
2680 /* We hard-wire the BSP to the first CPU. */
2681 if (s
->cpu_index
== 0) {
2682 apic_designate_bsp(cpu
->apic_state
);
2685 s
->halted
= !cpu_is_bsp(cpu
);
2687 if (kvm_enabled()) {
2688 kvm_arch_reset_vcpu(cpu
);
2693 #ifndef CONFIG_USER_ONLY
2694 bool cpu_is_bsp(X86CPU
*cpu
)
2696 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
2699 /* TODO: remove me, when reset over QOM tree is implemented */
2700 static void x86_cpu_machine_reset_cb(void *opaque
)
2702 X86CPU
*cpu
= opaque
;
2703 cpu_reset(CPU(cpu
));
2707 static void mce_init(X86CPU
*cpu
)
2709 CPUX86State
*cenv
= &cpu
->env
;
2712 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2713 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2714 (CPUID_MCE
| CPUID_MCA
)) {
2715 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2716 cenv
->mcg_ctl
= ~(uint64_t)0;
2717 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2718 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2723 #ifndef CONFIG_USER_ONLY
2724 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2726 CPUX86State
*env
= &cpu
->env
;
2727 DeviceState
*dev
= DEVICE(cpu
);
2728 APICCommonState
*apic
;
2729 const char *apic_type
= "apic";
2731 if (kvm_irqchip_in_kernel()) {
2732 apic_type
= "kvm-apic";
2733 } else if (xen_enabled()) {
2734 apic_type
= "xen-apic";
2737 cpu
->apic_state
= qdev_try_create(qdev_get_parent_bus(dev
), apic_type
);
2738 if (cpu
->apic_state
== NULL
) {
2739 error_setg(errp
, "APIC device '%s' could not be created", apic_type
);
2743 object_property_add_child(OBJECT(cpu
), "apic",
2744 OBJECT(cpu
->apic_state
), NULL
);
2745 qdev_prop_set_uint8(cpu
->apic_state
, "id", env
->cpuid_apic_id
);
2746 /* TODO: convert to link<> */
2747 apic
= APIC_COMMON(cpu
->apic_state
);
2751 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2753 if (cpu
->apic_state
== NULL
) {
2757 if (qdev_init(cpu
->apic_state
)) {
2758 error_setg(errp
, "APIC device '%s' could not be initialized",
2759 object_get_typename(OBJECT(cpu
->apic_state
)));
2764 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2770 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2771 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2772 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2773 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2774 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2775 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2776 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
2778 CPUState
*cs
= CPU(dev
);
2779 X86CPU
*cpu
= X86_CPU(dev
);
2780 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
2781 CPUX86State
*env
= &cpu
->env
;
2782 Error
*local_err
= NULL
;
2783 static bool ht_warned
;
2785 if (env
->features
[FEAT_7_0_EBX
] && env
->cpuid_level
< 7) {
2786 env
->cpuid_level
= 7;
2789 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2792 if (IS_AMD_CPU(env
)) {
2793 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
2794 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
2795 & CPUID_EXT2_AMD_ALIASES
);
2799 if (x86_cpu_filter_features(cpu
) && cpu
->enforce_cpuid
) {
2800 error_setg(&local_err
,
2802 "Host doesn't support requested features" :
2803 "TCG doesn't support requested features");
2807 #ifndef CONFIG_USER_ONLY
2808 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2810 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
2811 x86_cpu_apic_create(cpu
, &local_err
);
2812 if (local_err
!= NULL
) {
2821 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2822 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2823 * based on inputs (sockets,cores,threads), it is still better to gives
2826 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2827 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2829 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
2830 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2831 " -smp options properly.");
2835 x86_cpu_apic_realize(cpu
, &local_err
);
2836 if (local_err
!= NULL
) {
2841 xcc
->parent_realize(dev
, &local_err
);
2843 if (local_err
!= NULL
) {
2844 error_propagate(errp
, local_err
);
2849 /* Enables contiguous-apic-ID mode, for compatibility */
2850 static bool compat_apic_id_mode
;
2852 void enable_compat_apic_id_mode(void)
2854 compat_apic_id_mode
= true;
2857 /* Calculates initial APIC ID for a specific CPU index
2859 * Currently we need to be able to calculate the APIC ID from the CPU index
2860 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2861 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2862 * all CPUs up to max_cpus.
2864 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
2866 uint32_t correct_id
;
2869 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
2870 if (compat_apic_id_mode
) {
2871 if (cpu_index
!= correct_id
&& !warned
) {
2872 error_report("APIC IDs set in compatibility mode, "
2873 "CPU topology won't match the configuration");
2882 static void x86_cpu_initfn(Object
*obj
)
2884 CPUState
*cs
= CPU(obj
);
2885 X86CPU
*cpu
= X86_CPU(obj
);
2886 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
2887 CPUX86State
*env
= &cpu
->env
;
2893 object_property_add(obj
, "family", "int",
2894 x86_cpuid_version_get_family
,
2895 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
2896 object_property_add(obj
, "model", "int",
2897 x86_cpuid_version_get_model
,
2898 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
2899 object_property_add(obj
, "stepping", "int",
2900 x86_cpuid_version_get_stepping
,
2901 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
2902 object_property_add(obj
, "level", "int",
2903 x86_cpuid_get_level
,
2904 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
2905 object_property_add(obj
, "xlevel", "int",
2906 x86_cpuid_get_xlevel
,
2907 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
2908 object_property_add_str(obj
, "vendor",
2909 x86_cpuid_get_vendor
,
2910 x86_cpuid_set_vendor
, NULL
);
2911 object_property_add_str(obj
, "model-id",
2912 x86_cpuid_get_model_id
,
2913 x86_cpuid_set_model_id
, NULL
);
2914 object_property_add(obj
, "tsc-frequency", "int",
2915 x86_cpuid_get_tsc_freq
,
2916 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
2917 object_property_add(obj
, "apic-id", "int",
2918 x86_cpuid_get_apic_id
,
2919 x86_cpuid_set_apic_id
, NULL
, NULL
, NULL
);
2920 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
2921 x86_cpu_get_feature_words
,
2922 NULL
, NULL
, (void *)env
->features
, NULL
);
2923 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
2924 x86_cpu_get_feature_words
,
2925 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
2927 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
2928 env
->cpuid_apic_id
= x86_cpu_apic_id_from_index(cs
->cpu_index
);
2930 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
2932 /* init various static tables used in TCG mode */
2933 if (tcg_enabled() && !inited
) {
2935 optimize_flags_init();
2939 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
2941 X86CPU
*cpu
= X86_CPU(cs
);
2942 CPUX86State
*env
= &cpu
->env
;
2944 return env
->cpuid_apic_id
;
2947 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
2949 X86CPU
*cpu
= X86_CPU(cs
);
2951 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
2954 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
2956 X86CPU
*cpu
= X86_CPU(cs
);
2958 cpu
->env
.eip
= value
;
2961 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
2963 X86CPU
*cpu
= X86_CPU(cs
);
2965 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
2968 static bool x86_cpu_has_work(CPUState
*cs
)
2970 X86CPU
*cpu
= X86_CPU(cs
);
2971 CPUX86State
*env
= &cpu
->env
;
2973 #if !defined(CONFIG_USER_ONLY)
2974 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
2975 apic_poll_irq(cpu
->apic_state
);
2976 cpu_reset_interrupt(cs
, CPU_INTERRUPT_POLL
);
2980 return ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2981 (env
->eflags
& IF_MASK
)) ||
2982 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
2983 CPU_INTERRUPT_INIT
|
2984 CPU_INTERRUPT_SIPI
|
2985 CPU_INTERRUPT_MCE
));
2988 static Property x86_cpu_properties
[] = {
2989 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
2990 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
2991 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
2992 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
2993 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
2994 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, false),
2995 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
2996 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
2997 DEFINE_PROP_END_OF_LIST()
3000 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
3002 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3003 CPUClass
*cc
= CPU_CLASS(oc
);
3004 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3006 xcc
->parent_realize
= dc
->realize
;
3007 dc
->realize
= x86_cpu_realizefn
;
3008 dc
->bus_type
= TYPE_ICC_BUS
;
3009 dc
->props
= x86_cpu_properties
;
3011 xcc
->parent_reset
= cc
->reset
;
3012 cc
->reset
= x86_cpu_reset
;
3013 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
3015 cc
->class_by_name
= x86_cpu_class_by_name
;
3016 cc
->parse_features
= x86_cpu_parse_featurestr
;
3017 cc
->has_work
= x86_cpu_has_work
;
3018 cc
->do_interrupt
= x86_cpu_do_interrupt
;
3019 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
3020 cc
->dump_state
= x86_cpu_dump_state
;
3021 cc
->set_pc
= x86_cpu_set_pc
;
3022 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
3023 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
3024 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
3025 cc
->get_arch_id
= x86_cpu_get_arch_id
;
3026 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
3027 #ifdef CONFIG_USER_ONLY
3028 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
3030 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
3031 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
3032 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
3033 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
3034 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
3035 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
3036 cc
->vmsd
= &vmstate_x86_cpu
;
3038 cc
->gdb_num_core_regs
= CPU_NB_REGS
* 2 + 25;
3039 #ifndef CONFIG_USER_ONLY
3040 cc
->debug_excp_handler
= breakpoint_handler
;
3042 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
3043 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
3046 static const TypeInfo x86_cpu_type_info
= {
3047 .name
= TYPE_X86_CPU
,
3049 .instance_size
= sizeof(X86CPU
),
3050 .instance_init
= x86_cpu_initfn
,
3052 .class_size
= sizeof(X86CPUClass
),
3053 .class_init
= x86_cpu_common_class_init
,
3056 static void x86_cpu_register_types(void)
3060 type_register_static(&x86_cpu_type_info
);
3061 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
3062 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
3065 type_register_static(&host_x86_cpu_type_info
);
3069 type_init(x86_cpu_register_types
)