2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
30 #include "hw/qdev-properties.h"
31 #include "sysemu/dma.h"
32 #include "qemu/timer.h"
33 #include "qemu/bitops.h"
34 #include "hw/sd/sdhci.h"
35 #include "migration/vmstate.h"
36 #include "sdhci-internal.h"
38 #include "qemu/module.h"
40 #include "qom/object.h"
42 #define TYPE_SDHCI_BUS "sdhci-bus"
43 /* This is reusing the SDBus typedef from SD_BUS */
44 DECLARE_INSTANCE_CHECKER(SDBus
, SDHCI_BUS
,
47 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
49 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
51 return 1 << (9 + FIELD_EX32(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
));
54 /* return true on error */
55 static bool sdhci_check_capab_freq_range(SDHCIState
*s
, const char *desc
,
56 uint8_t freq
, Error
**errp
)
58 if (s
->sd_spec_version
>= 3) {
66 error_setg(errp
, "SD %s clock frequency can have value"
67 "in range 0-63 only", desc
);
73 static void sdhci_check_capareg(SDHCIState
*s
, Error
**errp
)
75 uint64_t msk
= s
->capareg
;
79 switch (s
->sd_spec_version
) {
81 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT_V4
);
82 trace_sdhci_capareg("64-bit system bus (v4)", val
);
83 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT_V4
, 0);
85 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, UHS_II
);
86 trace_sdhci_capareg("UHS-II", val
);
87 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, UHS_II
, 0);
89 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA3
);
90 trace_sdhci_capareg("ADMA3", val
);
91 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA3
, 0);
95 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ASYNC_INT
);
96 trace_sdhci_capareg("async interrupt", val
);
97 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ASYNC_INT
, 0);
99 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SLOT_TYPE
);
101 error_setg(errp
, "slot-type not supported");
104 trace_sdhci_capareg("slot type", val
);
105 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SLOT_TYPE
, 0);
108 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, EMBEDDED_8BIT
);
109 trace_sdhci_capareg("8-bit bus", val
);
111 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, EMBEDDED_8BIT
, 0);
113 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS_SPEED
);
114 trace_sdhci_capareg("bus speed mask", val
);
115 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS_SPEED
, 0);
117 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, DRIVER_STRENGTH
);
118 trace_sdhci_capareg("driver strength mask", val
);
119 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, DRIVER_STRENGTH
, 0);
121 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TIMER_RETUNING
);
122 trace_sdhci_capareg("timer re-tuning", val
);
123 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TIMER_RETUNING
, 0);
125 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDR50_TUNING
);
126 trace_sdhci_capareg("use SDR50 tuning", val
);
127 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDR50_TUNING
, 0);
129 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, RETUNING_MODE
);
130 trace_sdhci_capareg("re-tuning mode", val
);
131 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, RETUNING_MODE
, 0);
133 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, CLOCK_MULT
);
134 trace_sdhci_capareg("clock multiplier", val
);
135 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, CLOCK_MULT
, 0);
138 case 2: /* default version */
139 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA2
);
140 trace_sdhci_capareg("ADMA2", val
);
141 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA2
, 0);
143 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA1
);
144 trace_sdhci_capareg("ADMA1", val
);
145 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA1
, 0);
147 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT
);
148 trace_sdhci_capareg("64-bit system bus (v3)", val
);
149 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT
, 0);
153 y
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOUNIT
);
154 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOUNIT
, 0);
156 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOCLKFREQ
);
157 trace_sdhci_capareg(y
? "timeout (MHz)" : "Timeout (KHz)", val
);
158 if (sdhci_check_capab_freq_range(s
, "timeout", val
, errp
)) {
161 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOCLKFREQ
, 0);
163 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BASECLKFREQ
);
164 trace_sdhci_capareg(y
? "base (MHz)" : "Base (KHz)", val
);
165 if (sdhci_check_capab_freq_range(s
, "base", val
, errp
)) {
168 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BASECLKFREQ
, 0);
170 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
);
172 error_setg(errp
, "block size can be 512, 1024 or 2048 only");
175 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s
));
176 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, MAXBLOCKLENGTH
, 0);
178 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, HIGHSPEED
);
179 trace_sdhci_capareg("high speed", val
);
180 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, HIGHSPEED
, 0);
182 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDMA
);
183 trace_sdhci_capareg("SDMA", val
);
184 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDMA
, 0);
186 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SUSPRESUME
);
187 trace_sdhci_capareg("suspend/resume", val
);
188 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SUSPRESUME
, 0);
190 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V33
);
191 trace_sdhci_capareg("3.3v", val
);
192 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V33
, 0);
194 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V30
);
195 trace_sdhci_capareg("3.0v", val
);
196 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V30
, 0);
198 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V18
);
199 trace_sdhci_capareg("1.8v", val
);
200 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V18
, 0);
204 error_setg(errp
, "Unsupported spec version: %u", s
->sd_spec_version
);
207 qemu_log_mask(LOG_UNIMP
,
208 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64
"\n", msk
);
212 static uint8_t sdhci_slotint(SDHCIState
*s
)
214 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
215 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
216 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
219 static inline void sdhci_update_irq(SDHCIState
*s
)
221 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
224 static void sdhci_raise_insertion_irq(void *opaque
)
226 SDHCIState
*s
= (SDHCIState
*)opaque
;
228 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
229 timer_mod(s
->insert_timer
,
230 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
232 s
->prnsts
= 0x1ff0000;
233 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
234 s
->norintsts
|= SDHC_NIS_INSERT
;
240 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
242 SDHCIState
*s
= (SDHCIState
*)dev
;
244 trace_sdhci_set_inserted(level
? "insert" : "eject");
245 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
246 /* Give target some time to notice card ejection */
247 timer_mod(s
->insert_timer
,
248 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
251 s
->prnsts
= 0x1ff0000;
252 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
253 s
->norintsts
|= SDHC_NIS_INSERT
;
256 s
->prnsts
= 0x1fa0000;
257 s
->pwrcon
&= ~SDHC_POWER_ON
;
258 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
259 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
260 s
->norintsts
|= SDHC_NIS_REMOVE
;
267 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
269 SDHCIState
*s
= (SDHCIState
*)dev
;
272 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
275 s
->prnsts
|= SDHC_WRITE_PROTECT
;
279 static void sdhci_reset(SDHCIState
*s
)
281 DeviceState
*dev
= DEVICE(s
);
283 timer_del(s
->insert_timer
);
284 timer_del(s
->transfer_timer
);
286 /* Set all registers to 0. Capabilities/Version registers are not cleared
287 * and assumed to always preserve their value, given to them during
289 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
291 /* Reset other state based on current card insertion/readonly status */
292 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
293 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
296 s
->stopped_state
= sdhc_not_stopped
;
297 s
->pending_insert_state
= false;
300 static void sdhci_poweron_reset(DeviceState
*dev
)
302 /* QOM (ie power-on) reset. This is identical to reset
303 * commanded via device register apart from handling of the
304 * 'pending insert on powerup' quirk.
306 SDHCIState
*s
= (SDHCIState
*)dev
;
310 if (s
->pending_insert_quirk
) {
311 s
->pending_insert_state
= true;
315 static void sdhci_data_transfer(void *opaque
);
317 static void sdhci_send_command(SDHCIState
*s
)
320 uint8_t response
[16];
325 request
.cmd
= s
->cmdreg
>> 8;
326 request
.arg
= s
->argument
;
328 trace_sdhci_send_command(request
.cmd
, request
.arg
);
329 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
331 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
333 s
->rspreg
[0] = ldl_be_p(response
);
334 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
335 trace_sdhci_response4(s
->rspreg
[0]);
336 } else if (rlen
== 16) {
337 s
->rspreg
[0] = ldl_be_p(&response
[11]);
338 s
->rspreg
[1] = ldl_be_p(&response
[7]);
339 s
->rspreg
[2] = ldl_be_p(&response
[3]);
340 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
342 trace_sdhci_response16(s
->rspreg
[3], s
->rspreg
[2],
343 s
->rspreg
[1], s
->rspreg
[0]);
345 trace_sdhci_error("timeout waiting for command response");
346 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
347 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
348 s
->norintsts
|= SDHC_NIS_ERR
;
352 if (!(s
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
) &&
353 (s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
354 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
355 s
->norintsts
|= SDHC_NIS_TRSCMP
;
359 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
360 s
->norintsts
|= SDHC_NIS_CMDCMP
;
365 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
367 sdhci_data_transfer(s
);
371 static void sdhci_end_transfer(SDHCIState
*s
)
373 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
374 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
376 uint8_t response
[16];
380 trace_sdhci_end_transfer(request
.cmd
, request
.arg
);
381 sdbus_do_command(&s
->sdbus
, &request
, response
);
382 /* Auto CMD12 response goes to the upper Response register */
383 s
->rspreg
[3] = ldl_be_p(response
);
386 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
387 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
388 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
390 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
391 s
->norintsts
|= SDHC_NIS_TRSCMP
;
398 * Programmed i/o data transfer
400 #define BLOCK_SIZE_MASK (4 * KiB - 1)
402 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
403 static void sdhci_read_block_from_card(SDHCIState
*s
)
405 const uint16_t blk_size
= s
->blksize
& BLOCK_SIZE_MASK
;
407 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
408 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
412 if (!FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
413 /* Device is not in tuning */
414 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, blk_size
);
417 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
418 /* Device is in tuning */
419 s
->hostctl2
&= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK
;
420 s
->hostctl2
|= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK
;
421 s
->prnsts
&= ~(SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
|
426 /* New data now available for READ through Buffer Port Register */
427 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
428 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
429 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
432 /* Clear DAT line active status if that was the last block */
433 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
434 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
435 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
438 /* If stop at block gap request was set and it's not the last block of
439 * data - generate Block Event interrupt */
440 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
442 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
443 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
444 s
->norintsts
|= SDHC_EIS_BLKGAP
;
452 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
453 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
458 /* first check that a valid data exists in host controller input buffer */
459 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
460 trace_sdhci_error("read from empty buffer");
464 for (i
= 0; i
< size
; i
++) {
465 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
467 /* check if we've read all valid data (blksize bytes) from buffer */
468 if ((s
->data_count
) >= (s
->blksize
& BLOCK_SIZE_MASK
)) {
469 trace_sdhci_read_dataport(s
->data_count
);
470 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
471 s
->data_count
= 0; /* next buff read must start at position [0] */
473 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
477 /* if that was the last block of data */
478 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
479 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
480 /* stop at gap request */
481 (s
->stopped_state
== sdhc_gap_read
&&
482 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
483 sdhci_end_transfer(s
);
484 } else { /* if there are more data, read next block from card */
485 sdhci_read_block_from_card(s
);
494 /* Write data from host controller FIFO to card */
495 static void sdhci_write_block_to_card(SDHCIState
*s
)
497 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
498 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
499 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
505 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
506 if (s
->blkcnt
== 0) {
513 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, s
->blksize
& BLOCK_SIZE_MASK
);
515 /* Next data can be written through BUFFER DATORT register */
516 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
518 /* Finish transfer if that was the last block of data */
519 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
520 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
521 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
522 sdhci_end_transfer(s
);
523 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
524 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
527 /* Generate Block Gap Event if requested and if not the last block */
528 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
530 s
->prnsts
&= ~SDHC_DOING_WRITE
;
531 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
532 s
->norintsts
|= SDHC_EIS_BLKGAP
;
534 sdhci_end_transfer(s
);
540 /* Write @size bytes of @value data to host controller @s Buffer Data Port
542 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
546 /* Check that there is free space left in a buffer */
547 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
548 trace_sdhci_error("Can't write to data buffer: buffer full");
552 for (i
= 0; i
< size
; i
++) {
553 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
556 if (s
->data_count
>= (s
->blksize
& BLOCK_SIZE_MASK
)) {
557 trace_sdhci_write_dataport(s
->data_count
);
559 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
560 if (s
->prnsts
& SDHC_DOING_WRITE
) {
561 sdhci_write_block_to_card(s
);
568 * Single DMA data transfer
571 /* Multi block SDMA transfer */
572 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
574 bool page_aligned
= false;
576 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
577 uint32_t boundary_chk
= 1 << (((s
->blksize
& ~BLOCK_SIZE_MASK
) >> 12) + 12);
578 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
580 if (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || !s
->blkcnt
) {
581 qemu_log_mask(LOG_UNIMP
, "infinite transfer is not supported\n");
585 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
586 * possible stop at page boundary if initial address is not page aligned,
587 * allow them to work properly */
588 if ((s
->sdmasysad
% boundary_chk
) == 0) {
592 if (s
->trnmod
& SDHC_TRNS_READ
) {
593 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
594 SDHC_DAT_LINE_ACTIVE
;
596 if (s
->data_count
== 0) {
597 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
599 begin
= s
->data_count
;
600 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
601 s
->data_count
= boundary_count
+ begin
;
604 s
->data_count
= block_size
;
605 boundary_count
-= block_size
- begin
;
606 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
610 dma_memory_write(s
->dma_as
, s
->sdmasysad
,
611 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
612 s
->sdmasysad
+= s
->data_count
- begin
;
613 if (s
->data_count
== block_size
) {
616 if (page_aligned
&& boundary_count
== 0) {
621 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
622 SDHC_DAT_LINE_ACTIVE
;
624 begin
= s
->data_count
;
625 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
626 s
->data_count
= boundary_count
+ begin
;
629 s
->data_count
= block_size
;
630 boundary_count
-= block_size
- begin
;
632 dma_memory_read(s
->dma_as
, s
->sdmasysad
,
633 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
634 s
->sdmasysad
+= s
->data_count
- begin
;
635 if (s
->data_count
== block_size
) {
636 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
638 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
642 if (page_aligned
&& boundary_count
== 0) {
648 if (s
->blkcnt
== 0) {
649 sdhci_end_transfer(s
);
651 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
652 s
->norintsts
|= SDHC_NIS_DMA
;
658 /* single block SDMA transfer */
659 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
661 uint32_t datacnt
= s
->blksize
& BLOCK_SIZE_MASK
;
663 if (s
->trnmod
& SDHC_TRNS_READ
) {
664 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, datacnt
);
665 dma_memory_write(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
667 dma_memory_read(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
668 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, datacnt
);
672 sdhci_end_transfer(s
);
675 typedef struct ADMADescr
{
682 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
686 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
687 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
688 case SDHC_CTRL_ADMA2_32
:
689 dma_memory_read(s
->dma_as
, entry_addr
, &adma2
, sizeof(adma2
));
690 adma2
= le64_to_cpu(adma2
);
691 /* The spec does not specify endianness of descriptor table.
692 * We currently assume that it is LE.
694 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
695 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
696 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
699 case SDHC_CTRL_ADMA1_32
:
700 dma_memory_read(s
->dma_as
, entry_addr
, &adma1
, sizeof(adma1
));
701 adma1
= le32_to_cpu(adma1
);
702 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
703 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
705 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
706 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
708 dscr
->length
= 4 * KiB
;
711 case SDHC_CTRL_ADMA2_64
:
712 dma_memory_read(s
->dma_as
, entry_addr
, &dscr
->attr
, 1);
713 dma_memory_read(s
->dma_as
, entry_addr
+ 2, &dscr
->length
, 2);
714 dscr
->length
= le16_to_cpu(dscr
->length
);
715 dma_memory_read(s
->dma_as
, entry_addr
+ 4, &dscr
->addr
, 8);
716 dscr
->addr
= le64_to_cpu(dscr
->addr
);
717 dscr
->attr
&= (uint8_t) ~0xC0;
723 /* Advanced DMA data transfer */
725 static void sdhci_do_adma(SDHCIState
*s
)
727 unsigned int begin
, length
;
728 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
732 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
733 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
735 get_adma_description(s
, &dscr
);
736 trace_sdhci_adma_loop(dscr
.addr
, dscr
.length
, dscr
.attr
);
738 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
739 /* Indicate that error occurred in ST_FDS state */
740 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
741 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
743 /* Generate ADMA error interrupt */
744 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
745 s
->errintsts
|= SDHC_EIS_ADMAERR
;
746 s
->norintsts
|= SDHC_NIS_ERR
;
753 length
= dscr
.length
? dscr
.length
: 64 * KiB
;
755 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
756 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
758 if (s
->trnmod
& SDHC_TRNS_READ
) {
760 if (s
->data_count
== 0) {
761 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
763 begin
= s
->data_count
;
764 if ((length
+ begin
) < block_size
) {
765 s
->data_count
= length
+ begin
;
768 s
->data_count
= block_size
;
769 length
-= block_size
- begin
;
771 dma_memory_write(s
->dma_as
, dscr
.addr
,
772 &s
->fifo_buffer
[begin
],
773 s
->data_count
- begin
);
774 dscr
.addr
+= s
->data_count
- begin
;
775 if (s
->data_count
== block_size
) {
777 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
779 if (s
->blkcnt
== 0) {
787 begin
= s
->data_count
;
788 if ((length
+ begin
) < block_size
) {
789 s
->data_count
= length
+ begin
;
792 s
->data_count
= block_size
;
793 length
-= block_size
- begin
;
795 dma_memory_read(s
->dma_as
, dscr
.addr
,
796 &s
->fifo_buffer
[begin
],
797 s
->data_count
- begin
);
798 dscr
.addr
+= s
->data_count
- begin
;
799 if (s
->data_count
== block_size
) {
800 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
802 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
804 if (s
->blkcnt
== 0) {
811 s
->admasysaddr
+= dscr
.incr
;
813 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
814 s
->admasysaddr
= dscr
.addr
;
815 trace_sdhci_adma("link", s
->admasysaddr
);
818 s
->admasysaddr
+= dscr
.incr
;
822 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
823 trace_sdhci_adma("interrupt", s
->admasysaddr
);
824 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
825 s
->norintsts
|= SDHC_NIS_DMA
;
831 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
832 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
833 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
834 trace_sdhci_adma_transfer_completed();
835 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
836 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
838 trace_sdhci_error("SD/MMC host ADMA length mismatch");
839 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
840 SDHC_ADMAERR_STATE_ST_TFR
;
841 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
842 trace_sdhci_error("Set ADMA error flag");
843 s
->errintsts
|= SDHC_EIS_ADMAERR
;
844 s
->norintsts
|= SDHC_NIS_ERR
;
849 sdhci_end_transfer(s
);
855 /* we have unfinished business - reschedule to continue ADMA */
856 timer_mod(s
->transfer_timer
,
857 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
860 /* Perform data transfer according to controller configuration */
862 static void sdhci_data_transfer(void *opaque
)
864 SDHCIState
*s
= (SDHCIState
*)opaque
;
866 if (s
->trnmod
& SDHC_TRNS_DMA
) {
867 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
869 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
870 sdhci_sdma_transfer_single_block(s
);
872 sdhci_sdma_transfer_multi_blocks(s
);
876 case SDHC_CTRL_ADMA1_32
:
877 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA1_MASK
)) {
878 trace_sdhci_error("ADMA1 not supported");
884 case SDHC_CTRL_ADMA2_32
:
885 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
)) {
886 trace_sdhci_error("ADMA2 not supported");
892 case SDHC_CTRL_ADMA2_64
:
893 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
) ||
894 !(s
->capareg
& R_SDHC_CAPAB_BUS64BIT_MASK
)) {
895 trace_sdhci_error("64 bit ADMA not supported");
902 trace_sdhci_error("Unsupported DMA type");
906 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
907 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
908 SDHC_DAT_LINE_ACTIVE
;
909 sdhci_read_block_from_card(s
);
911 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
912 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
913 sdhci_write_block_to_card(s
);
918 static bool sdhci_can_issue_command(SDHCIState
*s
)
920 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
921 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
922 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
923 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
924 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
931 /* The Buffer Data Port register must be accessed in sequential and
932 * continuous manner */
934 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
936 if ((s
->data_count
& 0x3) != byte_num
) {
937 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
944 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
946 SDHCIState
*s
= (SDHCIState
*)opaque
;
949 switch (offset
& ~0x3) {
954 ret
= s
->blksize
| (s
->blkcnt
<< 16);
960 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
962 case SDHC_RSPREG0
... SDHC_RSPREG3
:
963 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
966 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
967 ret
= sdhci_read_dataport(s
, size
);
968 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
974 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, DAT_LVL
,
975 sdbus_get_dat_lines(&s
->sdbus
));
976 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, CMD_LVL
,
977 sdbus_get_cmd_line(&s
->sdbus
));
980 ret
= s
->hostctl1
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
984 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
987 ret
= s
->norintsts
| (s
->errintsts
<< 16);
989 case SDHC_NORINTSTSEN
:
990 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
992 case SDHC_NORINTSIGEN
:
993 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
995 case SDHC_ACMD12ERRSTS
:
996 ret
= s
->acmd12errsts
| (s
->hostctl2
<< 16);
999 ret
= (uint32_t)s
->capareg
;
1001 case SDHC_CAPAB
+ 4:
1002 ret
= (uint32_t)(s
->capareg
>> 32);
1005 ret
= (uint32_t)s
->maxcurr
;
1007 case SDHC_MAXCURR
+ 4:
1008 ret
= (uint32_t)(s
->maxcurr
>> 32);
1013 case SDHC_ADMASYSADDR
:
1014 ret
= (uint32_t)s
->admasysaddr
;
1016 case SDHC_ADMASYSADDR
+ 4:
1017 ret
= (uint32_t)(s
->admasysaddr
>> 32);
1019 case SDHC_SLOT_INT_STATUS
:
1020 ret
= (s
->version
<< 16) | sdhci_slotint(s
);
1023 qemu_log_mask(LOG_UNIMP
, "SDHC rd_%ub @0x%02" HWADDR_PRIx
" "
1024 "not implemented\n", size
, offset
);
1028 ret
>>= (offset
& 0x3) * 8;
1029 ret
&= (1ULL << (size
* 8)) - 1;
1030 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
1034 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
1036 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
1039 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
1041 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
1042 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
1043 if (s
->stopped_state
== sdhc_gap_read
) {
1044 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
1045 sdhci_read_block_from_card(s
);
1047 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
1048 sdhci_write_block_to_card(s
);
1050 s
->stopped_state
= sdhc_not_stopped
;
1051 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
1052 if (s
->prnsts
& SDHC_DOING_READ
) {
1053 s
->stopped_state
= sdhc_gap_read
;
1054 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
1055 s
->stopped_state
= sdhc_gap_write
;
1060 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
1063 case SDHC_RESET_ALL
:
1066 case SDHC_RESET_CMD
:
1067 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
1068 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
1070 case SDHC_RESET_DATA
:
1072 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
1073 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
1074 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
1075 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
1076 s
->stopped_state
= sdhc_not_stopped
;
1077 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
1078 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
1084 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1086 SDHCIState
*s
= (SDHCIState
*)opaque
;
1087 unsigned shift
= 8 * (offset
& 0x3);
1088 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
1089 uint32_t value
= val
;
1092 switch (offset
& ~0x3) {
1094 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1095 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1096 /* Writing to last byte of sdmasysad might trigger transfer */
1097 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1098 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl1
) == SDHC_CTRL_SDMA
) {
1099 if (s
->trnmod
& SDHC_TRNS_MULTI
) {
1100 sdhci_sdma_transfer_multi_blocks(s
);
1102 sdhci_sdma_transfer_single_block(s
);
1107 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1108 MASKED_WRITE(s
->blksize
, mask
, value
);
1109 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1112 /* Limit block size to the maximum buffer size */
1113 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1114 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than "
1115 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1118 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1123 MASKED_WRITE(s
->argument
, mask
, value
);
1126 /* DMA can be enabled only if it is supported as indicated by
1127 * capabilities register */
1128 if (!(s
->capareg
& R_SDHC_CAPAB_SDMA_MASK
)) {
1129 value
&= ~SDHC_TRNS_DMA
;
1131 MASKED_WRITE(s
->trnmod
, mask
, value
& SDHC_TRNMOD_MASK
);
1132 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1134 /* Writing to the upper byte of CMDREG triggers SD command generation */
1135 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1139 sdhci_send_command(s
);
1142 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1143 sdhci_write_dataport(s
, value
>> shift
, size
);
1147 if (!(mask
& 0xFF0000)) {
1148 sdhci_blkgap_write(s
, value
>> 16);
1150 MASKED_WRITE(s
->hostctl1
, mask
, value
);
1151 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1152 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1153 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1154 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1155 s
->pwrcon
&= ~SDHC_POWER_ON
;
1159 if (!(mask
& 0xFF000000)) {
1160 sdhci_reset_write(s
, value
>> 24);
1162 MASKED_WRITE(s
->clkcon
, mask
, value
);
1163 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1164 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1165 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1167 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1170 case SDHC_NORINTSTS
:
1171 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1172 value
&= ~SDHC_NIS_CARDINT
;
1174 s
->norintsts
&= mask
| ~value
;
1175 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1177 s
->norintsts
|= SDHC_NIS_ERR
;
1179 s
->norintsts
&= ~SDHC_NIS_ERR
;
1181 sdhci_update_irq(s
);
1183 case SDHC_NORINTSTSEN
:
1184 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1185 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1186 s
->norintsts
&= s
->norintstsen
;
1187 s
->errintsts
&= s
->errintstsen
;
1189 s
->norintsts
|= SDHC_NIS_ERR
;
1191 s
->norintsts
&= ~SDHC_NIS_ERR
;
1193 /* Quirk for Raspberry Pi: pending card insert interrupt
1194 * appears when first enabled after power on */
1195 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert_state
) {
1196 assert(s
->pending_insert_quirk
);
1197 s
->norintsts
|= SDHC_NIS_INSERT
;
1198 s
->pending_insert_state
= false;
1200 sdhci_update_irq(s
);
1202 case SDHC_NORINTSIGEN
:
1203 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1204 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1205 sdhci_update_irq(s
);
1208 MASKED_WRITE(s
->admaerr
, mask
, value
);
1210 case SDHC_ADMASYSADDR
:
1211 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1212 (uint64_t)mask
)) | (uint64_t)value
;
1214 case SDHC_ADMASYSADDR
+ 4:
1215 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1216 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1219 s
->acmd12errsts
|= value
;
1220 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1221 if (s
->acmd12errsts
) {
1222 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1225 s
->norintsts
|= SDHC_NIS_ERR
;
1227 sdhci_update_irq(s
);
1229 case SDHC_ACMD12ERRSTS
:
1230 MASKED_WRITE(s
->acmd12errsts
, mask
, value
& UINT16_MAX
);
1231 if (s
->uhs_mode
>= UHS_I
) {
1232 MASKED_WRITE(s
->hostctl2
, mask
>> 16, value
>> 16);
1234 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, V18_ENA
)) {
1235 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_1_8V
);
1237 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_3_3V
);
1243 case SDHC_CAPAB
+ 4:
1245 case SDHC_MAXCURR
+ 4:
1246 qemu_log_mask(LOG_GUEST_ERROR
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1247 " <- 0x%08x read-only\n", size
, offset
, value
>> shift
);
1251 qemu_log_mask(LOG_UNIMP
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
" <- 0x%08x "
1252 "not implemented\n", size
, offset
, value
>> shift
);
1255 trace_sdhci_access("wr", size
<< 3, offset
, "<-",
1256 value
>> shift
, value
>> shift
);
1259 static const MemoryRegionOps sdhci_mmio_ops
= {
1261 .write
= sdhci_write
,
1263 .min_access_size
= 1,
1264 .max_access_size
= 4,
1267 .endianness
= DEVICE_LITTLE_ENDIAN
,
1270 static void sdhci_init_readonly_registers(SDHCIState
*s
, Error
**errp
)
1274 switch (s
->sd_spec_version
) {
1278 error_setg(errp
, "Only Spec v2/v3 are supported");
1281 s
->version
= (SDHC_HCVER_VENDOR
<< 8) | (s
->sd_spec_version
- 1);
1283 sdhci_check_capareg(s
, errp
);
1289 /* --- qdev common --- */
1291 void sdhci_initfn(SDHCIState
*s
)
1293 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1294 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1296 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1297 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1299 s
->io_ops
= &sdhci_mmio_ops
;
1302 void sdhci_uninitfn(SDHCIState
*s
)
1304 timer_del(s
->insert_timer
);
1305 timer_free(s
->insert_timer
);
1306 timer_del(s
->transfer_timer
);
1307 timer_free(s
->transfer_timer
);
1309 g_free(s
->fifo_buffer
);
1310 s
->fifo_buffer
= NULL
;
1313 void sdhci_common_realize(SDHCIState
*s
, Error
**errp
)
1317 sdhci_init_readonly_registers(s
, errp
);
1321 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1322 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1324 memory_region_init_io(&s
->iomem
, OBJECT(s
), s
->io_ops
, s
, "sdhci",
1325 SDHC_REGISTERS_MAP_SIZE
);
1328 void sdhci_common_unrealize(SDHCIState
*s
)
1330 /* This function is expected to be called only once for each class:
1331 * - SysBus: via DeviceClass->unrealize(),
1332 * - PCI: via PCIDeviceClass->exit().
1333 * However to avoid double-free and/or use-after-free we still nullify
1334 * this variable (better safe than sorry!). */
1335 g_free(s
->fifo_buffer
);
1336 s
->fifo_buffer
= NULL
;
1339 static bool sdhci_pending_insert_vmstate_needed(void *opaque
)
1341 SDHCIState
*s
= opaque
;
1343 return s
->pending_insert_state
;
1346 static const VMStateDescription sdhci_pending_insert_vmstate
= {
1347 .name
= "sdhci/pending-insert",
1349 .minimum_version_id
= 1,
1350 .needed
= sdhci_pending_insert_vmstate_needed
,
1351 .fields
= (VMStateField
[]) {
1352 VMSTATE_BOOL(pending_insert_state
, SDHCIState
),
1353 VMSTATE_END_OF_LIST()
1357 const VMStateDescription sdhci_vmstate
= {
1360 .minimum_version_id
= 1,
1361 .fields
= (VMStateField
[]) {
1362 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1363 VMSTATE_UINT16(blksize
, SDHCIState
),
1364 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1365 VMSTATE_UINT32(argument
, SDHCIState
),
1366 VMSTATE_UINT16(trnmod
, SDHCIState
),
1367 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1368 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1369 VMSTATE_UINT32(prnsts
, SDHCIState
),
1370 VMSTATE_UINT8(hostctl1
, SDHCIState
),
1371 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1372 VMSTATE_UINT8(blkgap
, SDHCIState
),
1373 VMSTATE_UINT8(wakcon
, SDHCIState
),
1374 VMSTATE_UINT16(clkcon
, SDHCIState
),
1375 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1376 VMSTATE_UINT8(admaerr
, SDHCIState
),
1377 VMSTATE_UINT16(norintsts
, SDHCIState
),
1378 VMSTATE_UINT16(errintsts
, SDHCIState
),
1379 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1380 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1381 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1382 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1383 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1384 VMSTATE_UINT16(data_count
, SDHCIState
),
1385 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1386 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1387 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, buf_maxsz
),
1388 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1389 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1390 VMSTATE_END_OF_LIST()
1392 .subsections
= (const VMStateDescription
*[]) {
1393 &sdhci_pending_insert_vmstate
,
1398 void sdhci_common_class_init(ObjectClass
*klass
, void *data
)
1400 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1402 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1403 dc
->vmsd
= &sdhci_vmstate
;
1404 dc
->reset
= sdhci_poweron_reset
;
1407 /* --- qdev SysBus --- */
1409 static Property sdhci_sysbus_properties
[] = {
1410 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1411 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert_quirk
,
1413 DEFINE_PROP_LINK("dma", SDHCIState
,
1414 dma_mr
, TYPE_MEMORY_REGION
, MemoryRegion
*),
1415 DEFINE_PROP_END_OF_LIST(),
1418 static void sdhci_sysbus_init(Object
*obj
)
1420 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1425 static void sdhci_sysbus_finalize(Object
*obj
)
1427 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1430 object_unparent(OBJECT(s
->dma_mr
));
1436 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
**errp
)
1439 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1440 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1442 sdhci_common_realize(s
, errp
);
1448 s
->dma_as
= &s
->sysbus_dma_as
;
1449 address_space_init(s
->dma_as
, s
->dma_mr
, "sdhci-dma");
1451 /* use system_memory() if property "dma" not set */
1452 s
->dma_as
= &address_space_memory
;
1455 sysbus_init_irq(sbd
, &s
->irq
);
1457 sysbus_init_mmio(sbd
, &s
->iomem
);
1460 static void sdhci_sysbus_unrealize(DeviceState
*dev
)
1462 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1464 sdhci_common_unrealize(s
);
1467 address_space_destroy(s
->dma_as
);
1471 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1473 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1475 device_class_set_props(dc
, sdhci_sysbus_properties
);
1476 dc
->realize
= sdhci_sysbus_realize
;
1477 dc
->unrealize
= sdhci_sysbus_unrealize
;
1479 sdhci_common_class_init(klass
, data
);
1482 static const TypeInfo sdhci_sysbus_info
= {
1483 .name
= TYPE_SYSBUS_SDHCI
,
1484 .parent
= TYPE_SYS_BUS_DEVICE
,
1485 .instance_size
= sizeof(SDHCIState
),
1486 .instance_init
= sdhci_sysbus_init
,
1487 .instance_finalize
= sdhci_sysbus_finalize
,
1488 .class_init
= sdhci_sysbus_class_init
,
1491 /* --- qdev bus master --- */
1493 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1495 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1497 sbc
->set_inserted
= sdhci_set_inserted
;
1498 sbc
->set_readonly
= sdhci_set_readonly
;
1501 static const TypeInfo sdhci_bus_info
= {
1502 .name
= TYPE_SDHCI_BUS
,
1503 .parent
= TYPE_SD_BUS
,
1504 .instance_size
= sizeof(SDBus
),
1505 .class_init
= sdhci_bus_class_init
,
1508 /* --- qdev i.MX eSDHC --- */
1510 static uint64_t usdhc_read(void *opaque
, hwaddr offset
, unsigned size
)
1512 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1518 return sdhci_read(opaque
, offset
, size
);
1522 * For a detailed explanation on the following bit
1523 * manipulation code see comments in a similar part of
1526 hostctl1
= SDHC_DMA_TYPE(s
->hostctl1
) << (8 - 3);
1528 if (s
->hostctl1
& SDHC_CTRL_8BITBUS
) {
1529 hostctl1
|= ESDHC_CTRL_8BITBUS
;
1532 if (s
->hostctl1
& SDHC_CTRL_4BITBUS
) {
1533 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1537 ret
|= (uint32_t)s
->blkgap
<< 16;
1538 ret
|= (uint32_t)s
->wakcon
<< 24;
1543 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1544 ret
= sdhci_read(opaque
, offset
, size
) & ~ESDHC_PRNSTS_SDSTB
;
1545 if (s
->clkcon
& SDHC_CLOCK_INT_STABLE
) {
1546 ret
|= ESDHC_PRNSTS_SDSTB
;
1550 case ESDHC_VENDOR_SPEC
:
1551 ret
= s
->vendor_spec
;
1553 case ESDHC_DLL_CTRL
:
1554 case ESDHC_TUNE_CTRL_STATUS
:
1555 case ESDHC_UNDOCUMENTED_REG27
:
1556 case ESDHC_TUNING_CTRL
:
1557 case ESDHC_MIX_CTRL
:
1558 case ESDHC_WTMK_LVL
:
1567 usdhc_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1569 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1571 uint32_t value
= (uint32_t)val
;
1574 case ESDHC_DLL_CTRL
:
1575 case ESDHC_TUNE_CTRL_STATUS
:
1576 case ESDHC_UNDOCUMENTED_REG27
:
1577 case ESDHC_TUNING_CTRL
:
1578 case ESDHC_WTMK_LVL
:
1581 case ESDHC_VENDOR_SPEC
:
1582 s
->vendor_spec
= value
;
1583 switch (s
->vendor
) {
1584 case SDHCI_VENDOR_IMX
:
1585 if (value
& ESDHC_IMX_FRC_SDCLK_ON
) {
1586 s
->prnsts
&= ~SDHC_IMX_CLOCK_GATE_OFF
;
1588 s
->prnsts
|= SDHC_IMX_CLOCK_GATE_OFF
;
1598 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1601 * |-----------+--------+--------+-----------+----------+---------|
1602 * | Card | Card | Endian | DATA3 | Data | Led |
1603 * | Detect | Detect | Mode | as Card | Transfer | Control |
1604 * | Signal | Test | | Detection | Width | |
1605 * | Selection | Level | | Pin | | |
1606 * |-----------+--------+--------+-----------+----------+---------|
1611 * |----------+------|
1612 * | Reserved | DMA |
1615 * |----------+------|
1617 * and here's what SDCHI spec expects those offsets to be:
1619 * 0x28 (Host Control Register)
1622 * |--------+--------+----------+------+--------+----------+---------|
1623 * | Card | Card | Extended | DMA | High | Data | LED |
1624 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1625 * | Signal | Test | Transfer | | Enable | Width | |
1626 * | Sel. | Level | Width | | | | |
1627 * |--------+--------+----------+------+--------+----------+---------|
1629 * and 0x29 (Power Control Register)
1631 * |----------------------------------|
1632 * | Power Control Register |
1634 * | Description omitted, |
1635 * | since it has no analog in ESDHCI |
1637 * |----------------------------------|
1639 * Since offsets 0x2A and 0x2B should be compatible between
1640 * both IP specs we only need to reconcile least 16-bit of the
1641 * word we've been given.
1645 * First, save bits 7 6 and 0 since they are identical
1647 hostctl1
= value
& (SDHC_CTRL_LED
|
1648 SDHC_CTRL_CDTEST_INS
|
1649 SDHC_CTRL_CDTEST_EN
);
1651 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1654 if (value
& ESDHC_CTRL_8BITBUS
) {
1655 hostctl1
|= SDHC_CTRL_8BITBUS
;
1658 if (value
& ESDHC_CTRL_4BITBUS
) {
1659 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1663 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1665 hostctl1
|= SDHC_DMA_TYPE(value
>> (8 - 3));
1668 * Now place the corrected value into low 16-bit of the value
1669 * we are going to give standard SDHCI write function
1671 * NOTE: This transformation should be the inverse of what can
1672 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1675 value
&= ~UINT16_MAX
;
1677 value
|= (uint16_t)s
->pwrcon
<< 8;
1679 sdhci_write(opaque
, offset
, value
, size
);
1682 case ESDHC_MIX_CTRL
:
1684 * So, when SD/MMC stack in Linux tries to write to "Transfer
1685 * Mode Register", ESDHC i.MX quirk code will translate it
1686 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1687 * order to get where we started
1689 * Note that Auto CMD23 Enable bit is located in a wrong place
1690 * on i.MX, but since it is not used by QEMU we do not care.
1692 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1693 * here becuase it will result in a call to
1694 * sdhci_send_command(s) which we don't want.
1697 s
->trnmod
= value
& UINT16_MAX
;
1701 * Similar to above, but this time a write to "Command
1702 * Register" will be translated into a 4-byte write to
1703 * "Transfer Mode register" where lower 16-bit of value would
1704 * be set to zero. So what we do is fill those bits with
1705 * cached value from s->trnmod and let the SDHCI
1706 * infrastructure handle the rest
1708 sdhci_write(opaque
, offset
, val
| s
->trnmod
, size
);
1712 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1713 * Linux driver will try to zero this field out which will
1714 * break the rest of SDHCI emulation.
1716 * Linux defaults to maximum possible setting (512K boundary)
1717 * and it seems to be the only option that i.MX IP implements,
1718 * so we artificially set it to that value.
1723 sdhci_write(opaque
, offset
, val
, size
);
1728 static const MemoryRegionOps usdhc_mmio_ops
= {
1730 .write
= usdhc_write
,
1732 .min_access_size
= 1,
1733 .max_access_size
= 4,
1736 .endianness
= DEVICE_LITTLE_ENDIAN
,
1739 static void imx_usdhc_init(Object
*obj
)
1741 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1743 s
->io_ops
= &usdhc_mmio_ops
;
1744 s
->quirks
= SDHCI_QUIRK_NO_BUSY_IRQ
;
1747 static const TypeInfo imx_usdhc_info
= {
1748 .name
= TYPE_IMX_USDHC
,
1749 .parent
= TYPE_SYSBUS_SDHCI
,
1750 .instance_init
= imx_usdhc_init
,
1753 /* --- qdev Samsung s3c --- */
1755 #define S3C_SDHCI_CONTROL2 0x80
1756 #define S3C_SDHCI_CONTROL3 0x84
1757 #define S3C_SDHCI_CONTROL4 0x8c
1759 static uint64_t sdhci_s3c_read(void *opaque
, hwaddr offset
, unsigned size
)
1764 case S3C_SDHCI_CONTROL2
:
1765 case S3C_SDHCI_CONTROL3
:
1766 case S3C_SDHCI_CONTROL4
:
1771 ret
= sdhci_read(opaque
, offset
, size
);
1778 static void sdhci_s3c_write(void *opaque
, hwaddr offset
, uint64_t val
,
1782 case S3C_SDHCI_CONTROL2
:
1783 case S3C_SDHCI_CONTROL3
:
1784 case S3C_SDHCI_CONTROL4
:
1788 sdhci_write(opaque
, offset
, val
, size
);
1793 static const MemoryRegionOps sdhci_s3c_mmio_ops
= {
1794 .read
= sdhci_s3c_read
,
1795 .write
= sdhci_s3c_write
,
1797 .min_access_size
= 1,
1798 .max_access_size
= 4,
1801 .endianness
= DEVICE_LITTLE_ENDIAN
,
1804 static void sdhci_s3c_init(Object
*obj
)
1806 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1808 s
->io_ops
= &sdhci_s3c_mmio_ops
;
1811 static const TypeInfo sdhci_s3c_info
= {
1812 .name
= TYPE_S3C_SDHCI
,
1813 .parent
= TYPE_SYSBUS_SDHCI
,
1814 .instance_init
= sdhci_s3c_init
,
1817 static void sdhci_register_types(void)
1819 type_register_static(&sdhci_sysbus_info
);
1820 type_register_static(&sdhci_bus_info
);
1821 type_register_static(&imx_usdhc_info
);
1822 type_register_static(&sdhci_s3c_info
);
1825 type_init(sdhci_register_types
)