2 * sPAPR CPU core device, acts as container of CPU thread devices.
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
11 #include "hw/cpu/core.h"
12 #include "hw/ppc/spapr_cpu_core.h"
13 #include "hw/qdev-properties.h"
14 #include "migration/vmstate.h"
15 #include "target/ppc/cpu.h"
16 #include "hw/ppc/spapr.h"
17 #include "qapi/error.h"
18 #include "sysemu/cpus.h"
19 #include "sysemu/kvm.h"
20 #include "target/ppc/kvm_ppc.h"
21 #include "hw/ppc/ppc.h"
22 #include "target/ppc/mmu-hash64.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/reset.h"
25 #include "sysemu/hw_accel.h"
26 #include "qemu/error-report.h"
28 static void spapr_reset_vcpu(PowerPCCPU
*cpu
)
30 CPUState
*cs
= CPU(cpu
);
31 CPUPPCState
*env
= &cpu
->env
;
32 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
33 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
35 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
39 env
->spr
[SPR_HIOR
] = 0;
41 lpcr
= env
->spr
[SPR_LPCR
];
43 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
44 * under KVM, the actual HW LPCR will be set differently by KVM itself,
45 * the settings below ensure proper operations with TCG in absence of
48 * Disable Power-saving mode Exit Cause exceptions for the CPU, so
49 * we don't get spurious wakups before an RTAS start-cpu call.
50 * For the same reason, set PSSCR_EC.
52 lpcr
&= ~(LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
| pcc
->lpcr_pm
);
53 lpcr
|= LPCR_LPES0
| LPCR_LPES1
;
54 env
->spr
[SPR_PSSCR
] |= PSSCR_EC
;
56 ppc_store_lpcr(cpu
, lpcr
);
58 /* Set a full AMOR so guest can use the AMR as it sees fit */
59 env
->spr
[SPR_AMOR
] = 0xffffffffffffffffull
;
61 spapr_cpu
->vpa_addr
= 0;
62 spapr_cpu
->slb_shadow_addr
= 0;
63 spapr_cpu
->slb_shadow_size
= 0;
64 spapr_cpu
->dtl_addr
= 0;
65 spapr_cpu
->dtl_size
= 0;
67 spapr_caps_cpu_apply(spapr
, cpu
);
69 kvm_check_mmu(cpu
, &error_fatal
);
71 spapr_irq_cpu_intc_reset(spapr
, cpu
);
74 void spapr_cpu_set_entry_state(PowerPCCPU
*cpu
, target_ulong nip
,
75 target_ulong r1
, target_ulong r3
,
78 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
79 CPUPPCState
*env
= &cpu
->env
;
85 kvmppc_set_reg_ppc_online(cpu
, 1);
87 /* Enable Power-saving mode Exit Cause exceptions */
88 ppc_store_lpcr(cpu
, env
->spr
[SPR_LPCR
] | pcc
->lpcr_pm
);
92 * Return the sPAPR CPU core type for @model which essentially is the CPU
93 * model specified with -cpu cmdline option.
95 const char *spapr_get_cpu_core_type(const char *cpu_type
)
97 int len
= strlen(cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
98 char *core_type
= g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
100 ObjectClass
*oc
= object_class_by_name(core_type
);
107 return object_class_get_name(oc
);
110 static bool slb_shadow_needed(void *opaque
)
112 SpaprCpuState
*spapr_cpu
= opaque
;
114 return spapr_cpu
->slb_shadow_addr
!= 0;
117 static const VMStateDescription vmstate_spapr_cpu_slb_shadow
= {
118 .name
= "spapr_cpu/vpa/slb_shadow",
120 .minimum_version_id
= 1,
121 .needed
= slb_shadow_needed
,
122 .fields
= (VMStateField
[]) {
123 VMSTATE_UINT64(slb_shadow_addr
, SpaprCpuState
),
124 VMSTATE_UINT64(slb_shadow_size
, SpaprCpuState
),
125 VMSTATE_END_OF_LIST()
129 static bool dtl_needed(void *opaque
)
131 SpaprCpuState
*spapr_cpu
= opaque
;
133 return spapr_cpu
->dtl_addr
!= 0;
136 static const VMStateDescription vmstate_spapr_cpu_dtl
= {
137 .name
= "spapr_cpu/vpa/dtl",
139 .minimum_version_id
= 1,
140 .needed
= dtl_needed
,
141 .fields
= (VMStateField
[]) {
142 VMSTATE_UINT64(dtl_addr
, SpaprCpuState
),
143 VMSTATE_UINT64(dtl_size
, SpaprCpuState
),
144 VMSTATE_END_OF_LIST()
148 static bool vpa_needed(void *opaque
)
150 SpaprCpuState
*spapr_cpu
= opaque
;
152 return spapr_cpu
->vpa_addr
!= 0;
155 static const VMStateDescription vmstate_spapr_cpu_vpa
= {
156 .name
= "spapr_cpu/vpa",
158 .minimum_version_id
= 1,
159 .needed
= vpa_needed
,
160 .fields
= (VMStateField
[]) {
161 VMSTATE_UINT64(vpa_addr
, SpaprCpuState
),
162 VMSTATE_END_OF_LIST()
164 .subsections
= (const VMStateDescription
* []) {
165 &vmstate_spapr_cpu_slb_shadow
,
166 &vmstate_spapr_cpu_dtl
,
171 static const VMStateDescription vmstate_spapr_cpu_state
= {
174 .minimum_version_id
= 1,
175 .fields
= (VMStateField
[]) {
176 VMSTATE_END_OF_LIST()
178 .subsections
= (const VMStateDescription
* []) {
179 &vmstate_spapr_cpu_vpa
,
184 static void spapr_unrealize_vcpu(PowerPCCPU
*cpu
, SpaprCpuCore
*sc
)
186 if (!sc
->pre_3_0_migration
) {
187 vmstate_unregister(NULL
, &vmstate_spapr_cpu_state
, cpu
->machine_data
);
189 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu
);
190 cpu_remove_sync(CPU(cpu
));
191 object_unparent(OBJECT(cpu
));
195 * Called when CPUs are hot-plugged.
197 static void spapr_cpu_core_reset(DeviceState
*dev
)
199 CPUCore
*cc
= CPU_CORE(dev
);
200 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(dev
);
203 for (i
= 0; i
< cc
->nr_threads
; i
++) {
204 spapr_reset_vcpu(sc
->threads
[i
]);
209 * Called by the machine reset.
211 static void spapr_cpu_core_reset_handler(void *opaque
)
213 spapr_cpu_core_reset(opaque
);
216 static void spapr_cpu_core_unrealize(DeviceState
*dev
)
218 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
219 CPUCore
*cc
= CPU_CORE(dev
);
222 qemu_unregister_reset(spapr_cpu_core_reset_handler
, sc
);
224 for (i
= 0; i
< cc
->nr_threads
; i
++) {
225 spapr_unrealize_vcpu(sc
->threads
[i
], sc
);
230 static void spapr_realize_vcpu(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
231 SpaprCpuCore
*sc
, Error
**errp
)
233 CPUPPCState
*env
= &cpu
->env
;
234 CPUState
*cs
= CPU(cpu
);
235 Error
*local_err
= NULL
;
237 if (!qdev_realize(DEVICE(cpu
), NULL
, errp
)) {
241 /* Set time-base frequency to 512 MHz */
242 cpu_ppc_tb_init(env
, SPAPR_TIMEBASE_FREQ
);
244 cpu_ppc_set_vhyp(cpu
, PPC_VIRTUAL_HYPERVISOR(spapr
));
245 kvmppc_set_papr(cpu
);
247 if (spapr_irq_cpu_intc_create(spapr
, cpu
, &local_err
) < 0) {
248 cpu_remove_sync(CPU(cpu
));
252 if (!sc
->pre_3_0_migration
) {
253 vmstate_register(NULL
, cs
->cpu_index
, &vmstate_spapr_cpu_state
,
258 static PowerPCCPU
*spapr_create_vcpu(SpaprCpuCore
*sc
, int i
, Error
**errp
)
260 SpaprCpuCoreClass
*scc
= SPAPR_CPU_CORE_GET_CLASS(sc
);
261 CPUCore
*cc
= CPU_CORE(sc
);
266 Error
*local_err
= NULL
;
268 obj
= object_new(scc
->cpu_type
);
271 cpu
= POWERPC_CPU(obj
);
273 * All CPUs start halted. CPU0 is unhalted from the machine level reset code
274 * and the rest are explicitly started up by the guest using an RTAS call.
276 cs
->start_powered_off
= true;
277 cs
->cpu_index
= cc
->core_id
+ i
;
278 spapr_set_vcpu_id(cpu
, cs
->cpu_index
, &local_err
);
283 cpu
->node_id
= sc
->node_id
;
285 id
= g_strdup_printf("thread[%d]", i
);
286 object_property_add_child(OBJECT(sc
), id
, obj
);
289 cpu
->machine_data
= g_new0(SpaprCpuState
, 1);
296 error_propagate(errp
, local_err
);
300 static void spapr_delete_vcpu(PowerPCCPU
*cpu
, SpaprCpuCore
*sc
)
302 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
304 cpu
->machine_data
= NULL
;
306 object_unparent(OBJECT(cpu
));
309 static void spapr_cpu_core_realize(DeviceState
*dev
, Error
**errp
)
311 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
312 * tries to add a sPAPR CPU core to a non-pseries machine.
314 SpaprMachineState
*spapr
=
315 (SpaprMachineState
*) object_dynamic_cast(qdev_get_machine(),
317 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
318 CPUCore
*cc
= CPU_CORE(OBJECT(dev
));
319 Error
*local_err
= NULL
;
323 error_setg(errp
, TYPE_SPAPR_CPU_CORE
" needs a pseries machine");
327 sc
->threads
= g_new(PowerPCCPU
*, cc
->nr_threads
);
328 for (i
= 0; i
< cc
->nr_threads
; i
++) {
329 sc
->threads
[i
] = spapr_create_vcpu(sc
, i
, &local_err
);
335 for (j
= 0; j
< cc
->nr_threads
; j
++) {
336 spapr_realize_vcpu(sc
->threads
[j
], spapr
, sc
, &local_err
);
342 qemu_register_reset(spapr_cpu_core_reset_handler
, sc
);
347 spapr_unrealize_vcpu(sc
->threads
[j
], sc
);
351 spapr_delete_vcpu(sc
->threads
[i
], sc
);
354 error_propagate(errp
, local_err
);
357 static Property spapr_cpu_core_properties
[] = {
358 DEFINE_PROP_INT32("node-id", SpaprCpuCore
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
359 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore
, pre_3_0_migration
,
361 DEFINE_PROP_END_OF_LIST()
364 static void spapr_cpu_core_class_init(ObjectClass
*oc
, void *data
)
366 DeviceClass
*dc
= DEVICE_CLASS(oc
);
367 SpaprCpuCoreClass
*scc
= SPAPR_CPU_CORE_CLASS(oc
);
369 dc
->realize
= spapr_cpu_core_realize
;
370 dc
->unrealize
= spapr_cpu_core_unrealize
;
371 dc
->reset
= spapr_cpu_core_reset
;
372 device_class_set_props(dc
, spapr_cpu_core_properties
);
373 scc
->cpu_type
= data
;
376 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
378 .parent = TYPE_SPAPR_CPU_CORE, \
379 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
380 .class_init = spapr_cpu_core_class_init, \
381 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
384 static const TypeInfo spapr_cpu_core_type_infos
[] = {
386 .name
= TYPE_SPAPR_CPU_CORE
,
387 .parent
= TYPE_CPU_CORE
,
389 .instance_size
= sizeof(SpaprCpuCore
),
390 .class_size
= sizeof(SpaprCpuCoreClass
),
392 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
393 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
394 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
395 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
396 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
397 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
398 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
399 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
400 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
401 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
402 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
403 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
405 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
409 DEFINE_TYPES(spapr_cpu_core_type_infos
)