hw/ppc/ppc4xx_pci.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  13  *
  14  * Copyright IBM Corp. 2008
  15  *
  16  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  17  */
  18
  19 /* This file implements emulation of the 32-bit PCI controller found in some
  20  * 4xx SoCs, such as the 440EP. */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/irq.h"
  24 #include "hw/ppc/ppc.h"
  25 #include "hw/ppc/ppc4xx.h"
  26 #include "migration/vmstate.h"
  27 #include "qemu/module.h"
  28 #include "sysemu/reset.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "exec/address-spaces.h"
  32 #include "trace.h"
  33 #include "qom/object.h"
  34
  35 struct PCIMasterMap {
  36     uint32_t la;
  37     uint32_t ma;
  38     uint32_t pcila;
  39     uint32_t pciha;
  40 };
  41
  42 struct PCITargetMap {
  43     uint32_t ms;
  44     uint32_t la;
  45 };
  46
  47 typedef struct PPC4xxPCIState PPC4xxPCIState;
  48 DECLARE_INSTANCE_CHECKER(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE,
  49                          TYPE_PPC4xx_PCI_HOST_BRIDGE)
  50
  51 #define PPC4xx_PCI_NR_PMMS 3
  52 #define PPC4xx_PCI_NR_PTMS 2
  53
  54 struct PPC4xxPCIState {
  55     PCIHostState parent_obj;
  56
  57     struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
  58     struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
  59     qemu_irq irq[4];
  60
  61     MemoryRegion container;
  62     MemoryRegion iomem;
  63 };
  64
  65 #define PCIC0_CFGADDR       0x0
  66 #define PCIC0_CFGDATA       0x4
  67
  68 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
  69  * PCI accesses. */
  70 #define PCIL0_PMM0LA        0x0
  71 #define PCIL0_PMM0MA        0x4
  72 #define PCIL0_PMM0PCILA     0x8
  73 #define PCIL0_PMM0PCIHA     0xc
  74 #define PCIL0_PMM1LA        0x10
  75 #define PCIL0_PMM1MA        0x14
  76 #define PCIL0_PMM1PCILA     0x18
  77 #define PCIL0_PMM1PCIHA     0x1c
  78 #define PCIL0_PMM2LA        0x20
  79 #define PCIL0_PMM2MA        0x24
  80 #define PCIL0_PMM2PCILA     0x28
  81 #define PCIL0_PMM2PCIHA     0x2c
  82
  83 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
  84  * PLB accesses. */
  85 #define PCIL0_PTM1MS        0x30
  86 #define PCIL0_PTM1LA        0x34
  87 #define PCIL0_PTM2MS        0x38
  88 #define PCIL0_PTM2LA        0x3c
  89 #define PCI_REG_BASE        0x800000
  90 #define PCI_REG_SIZE        0x40
  91
  92 #define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)
  93
  94 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
  95                                   uint64_t value, unsigned size)
  96 {
  97     struct PPC4xxPCIState *pci = opaque;
  98
  99     /* We ignore all target attempts at PCI configuration, effectively
 100      * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
 101
 102     switch (offset) {
 103     case PCIL0_PMM0LA:
 104         pci->pmm[0].la = value;
 105         break;
 106     case PCIL0_PMM0MA:
 107         pci->pmm[0].ma = value;
 108         break;
 109     case PCIL0_PMM0PCIHA:
 110         pci->pmm[0].pciha = value;
 111         break;
 112     case PCIL0_PMM0PCILA:
 113         pci->pmm[0].pcila = value;
 114         break;
 115
 116     case PCIL0_PMM1LA:
 117         pci->pmm[1].la = value;
 118         break;
 119     case PCIL0_PMM1MA:
 120         pci->pmm[1].ma = value;
 121         break;
 122     case PCIL0_PMM1PCIHA:
 123         pci->pmm[1].pciha = value;
 124         break;
 125     case PCIL0_PMM1PCILA:
 126         pci->pmm[1].pcila = value;
 127         break;
 128
 129     case PCIL0_PMM2LA:
 130         pci->pmm[2].la = value;
 131         break;
 132     case PCIL0_PMM2MA:
 133         pci->pmm[2].ma = value;
 134         break;
 135     case PCIL0_PMM2PCIHA:
 136         pci->pmm[2].pciha = value;
 137         break;
 138     case PCIL0_PMM2PCILA:
 139         pci->pmm[2].pcila = value;
 140         break;
 141
 142     case PCIL0_PTM1MS:
 143         pci->ptm[0].ms = value;
 144         break;
 145     case PCIL0_PTM1LA:
 146         pci->ptm[0].la = value;
 147         break;
 148     case PCIL0_PTM2MS:
 149         pci->ptm[1].ms = value;
 150         break;
 151     case PCIL0_PTM2LA:
 152         pci->ptm[1].la = value;
 153         break;
 154
 155     default:
 156         printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
 157                (unsigned long)offset);
 158         break;
 159     }
 160 }
 161
 162 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
 163                                      unsigned size)
 164 {
 165     struct PPC4xxPCIState *pci = opaque;
 166     uint32_t value;
 167
 168     switch (offset) {
 169     case PCIL0_PMM0LA:
 170         value = pci->pmm[0].la;
 171         break;
 172     case PCIL0_PMM0MA:
 173         value = pci->pmm[0].ma;
 174         break;
 175     case PCIL0_PMM0PCIHA:
 176         value = pci->pmm[0].pciha;
 177         break;
 178     case PCIL0_PMM0PCILA:
 179         value = pci->pmm[0].pcila;
 180         break;
 181
 182     case PCIL0_PMM1LA:
 183         value = pci->pmm[1].la;
 184         break;
 185     case PCIL0_PMM1MA:
 186         value = pci->pmm[1].ma;
 187         break;
 188     case PCIL0_PMM1PCIHA:
 189         value = pci->pmm[1].pciha;
 190         break;
 191     case PCIL0_PMM1PCILA:
 192         value = pci->pmm[1].pcila;
 193         break;
 194
 195     case PCIL0_PMM2LA:
 196         value = pci->pmm[2].la;
 197         break;
 198     case PCIL0_PMM2MA:
 199         value = pci->pmm[2].ma;
 200         break;
 201     case PCIL0_PMM2PCIHA:
 202         value = pci->pmm[2].pciha;
 203         break;
 204     case PCIL0_PMM2PCILA:
 205         value = pci->pmm[2].pcila;
 206         break;
 207
 208     case PCIL0_PTM1MS:
 209         value = pci->ptm[0].ms;
 210         break;
 211     case PCIL0_PTM1LA:
 212         value = pci->ptm[0].la;
 213         break;
 214     case PCIL0_PTM2MS:
 215         value = pci->ptm[1].ms;
 216         break;
 217     case PCIL0_PTM2LA:
 218         value = pci->ptm[1].la;
 219         break;
 220
 221     default:
 222         printf("%s: invalid PCI internal register 0x%lx\n", __func__,
 223                (unsigned long)offset);
 224         value = 0;
 225     }
 226
 227     return value;
 228 }
 229
 230 static const MemoryRegionOps pci_reg_ops = {
 231     .read = ppc4xx_pci_reg_read4,
 232     .write = ppc4xx_pci_reg_write4,
 233     .endianness = DEVICE_LITTLE_ENDIAN,
 234 };
 235
 236 static void ppc4xx_pci_reset(void *opaque)
 237 {
 238     struct PPC4xxPCIState *pci = opaque;
 239
 240     memset(pci->pmm, 0, sizeof(pci->pmm));
 241     memset(pci->ptm, 0, sizeof(pci->ptm));
 242 }
 243
 244 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 245  * may need further refactoring for other boards. */
 246 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 247 {
 248     int slot = pci_dev->devfn >> 3;
 249
 250     trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
 251
 252     return slot - 1;
 253 }
 254
 255 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
 256 {
 257     qemu_irq *pci_irqs = opaque;
 258
 259     trace_ppc4xx_pci_set_irq(irq_num);
 260     assert(irq_num >= 0);
 261     qemu_set_irq(pci_irqs[irq_num], level);
 262 }
 263
 264 static const VMStateDescription vmstate_pci_master_map = {
 265     .name = "pci_master_map",
 266     .version_id = 0,
 267     .minimum_version_id = 0,
 268     .fields = (VMStateField[]) {
 269         VMSTATE_UINT32(la, struct PCIMasterMap),
 270         VMSTATE_UINT32(ma, struct PCIMasterMap),
 271         VMSTATE_UINT32(pcila, struct PCIMasterMap),
 272         VMSTATE_UINT32(pciha, struct PCIMasterMap),
 273         VMSTATE_END_OF_LIST()
 274     }
 275 };
 276
 277 static const VMStateDescription vmstate_pci_target_map = {
 278     .name = "pci_target_map",
 279     .version_id = 0,
 280     .minimum_version_id = 0,
 281     .fields = (VMStateField[]) {
 282         VMSTATE_UINT32(ms, struct PCITargetMap),
 283         VMSTATE_UINT32(la, struct PCITargetMap),
 284         VMSTATE_END_OF_LIST()
 285     }
 286 };
 287
 288 static const VMStateDescription vmstate_ppc4xx_pci = {
 289     .name = "ppc4xx_pci",
 290     .version_id = 1,
 291     .minimum_version_id = 1,
 292     .fields = (VMStateField[]) {
 293         VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
 294                              vmstate_pci_master_map,
 295                              struct PCIMasterMap),
 296         VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
 297                              vmstate_pci_target_map,
 298                              struct PCITargetMap),
 299         VMSTATE_END_OF_LIST()
 300     }
 301 };
 302
 303 /* XXX Interrupt acknowledge cycles not supported. */
 304 static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
 305 {
 306     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 307     PPC4xxPCIState *s;
 308     PCIHostState *h;
 309     PCIBus *b;
 310     int i;
 311
 312     h = PCI_HOST_BRIDGE(dev);
 313     s = PPC4xx_PCI_HOST_BRIDGE(dev);
 314
 315     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 316         sysbus_init_irq(sbd, &s->irq[i]);
 317     }
 318
 319     b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
 320                               ppc4xx_pci_map_irq, s->irq, get_system_memory(),
 321                               get_system_io(), 0, ARRAY_SIZE(s->irq),
 322                               TYPE_PCI_BUS);
 323     h->bus = b;
 324
 325     pci_create_simple(b, 0, "ppc4xx-host-bridge");
 326
 327     /* XXX split into 2 memory regions, one for config space, one for regs */
 328     memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
 329     memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
 330                           "pci-conf-idx", 4);
 331     memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
 332                           "pci-conf-data", 4);
 333     memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
 334                           "pci.reg", PCI_REG_SIZE);
 335     memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
 336     memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
 337     memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
 338     sysbus_init_mmio(sbd, &s->container);
 339     qemu_register_reset(ppc4xx_pci_reset, s);
 340 }
 341
 342 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
 343 {
 344     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 345     DeviceClass *dc = DEVICE_CLASS(klass);
 346
 347     dc->desc        = "Host bridge";
 348     k->vendor_id    = PCI_VENDOR_ID_IBM;
 349     k->device_id    = PCI_DEVICE_ID_IBM_440GX;
 350     k->class_id     = PCI_CLASS_BRIDGE_OTHER;
 351     /*
 352      * PCI-facing part of the host bridge, not usable without the
 353      * host-facing part, which can't be device_add'ed, yet.
 354      */
 355     dc->user_creatable = false;
 356 }
 357
 358 static const TypeInfo ppc4xx_host_bridge_info = {
 359     .name          = "ppc4xx-host-bridge",
 360     .parent        = TYPE_PCI_DEVICE,
 361     .instance_size = sizeof(PCIDevice),
 362     .class_init    = ppc4xx_host_bridge_class_init,
 363     .interfaces = (InterfaceInfo[]) {
 364         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 365         { },
 366     },
 367 };
 368
 369 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
 370 {
 371     DeviceClass *dc = DEVICE_CLASS(klass);
 372
 373     dc->realize = ppc4xx_pcihost_realize;
 374     dc->vmsd = &vmstate_ppc4xx_pci;
 375 }
 376
 377 static const TypeInfo ppc4xx_pcihost_info = {
 378     .name          = TYPE_PPC4xx_PCI_HOST_BRIDGE,
 379     .parent        = TYPE_PCI_HOST_BRIDGE,
 380     .instance_size = sizeof(PPC4xxPCIState),
 381     .class_init    = ppc4xx_pcihost_class_init,
 382 };
 383
 384 static void ppc4xx_pci_register_types(void)
 385 {
 386     type_register_static(&ppc4xx_pcihost_info);
 387     type_register_static(&ppc4xx_host_bridge_info);
 388 }
 389
 390 type_init(ppc4xx_pci_register_types)