hw/dma/rc4030.c

   1 /*
   2  * QEMU JAZZ RC4030 chipset
   3  *
   4  * Copyright (c) 2007-2013 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/irq.h"
  28 #include "hw/mips/mips.h"
  29 #include "hw/sysbus.h"
  30 #include "migration/vmstate.h"
  31 #include "qapi/error.h"
  32 #include "qemu/timer.h"
  33 #include "qemu/log.h"
  34 #include "qemu/module.h"
  35 #include "exec/address-spaces.h"
  36 #include "trace.h"
  37 #include "qom/object.h"
  38
  39 /********************************************************/
  40 /* rc4030 emulation                                     */
  41
  42 typedef struct dma_pagetable_entry {
  43     int32_t frame;
  44     int32_t owner;
  45 } QEMU_PACKED dma_pagetable_entry;
  46
  47 #define DMA_PAGESIZE    4096
  48 #define DMA_REG_ENABLE  1
  49 #define DMA_REG_COUNT   2
  50 #define DMA_REG_ADDRESS 3
  51
  52 #define DMA_FLAG_ENABLE     0x0001
  53 #define DMA_FLAG_MEM_TO_DEV 0x0002
  54 #define DMA_FLAG_TC_INTR    0x0100
  55 #define DMA_FLAG_MEM_INTR   0x0200
  56 #define DMA_FLAG_ADDR_INTR  0x0400
  57
  58 #define TYPE_RC4030 "rc4030"
  59 typedef struct rc4030State rc4030State;
  60 DECLARE_INSTANCE_CHECKER(rc4030State, RC4030,
  61                          TYPE_RC4030)
  62
  63 #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
  64
  65 struct rc4030State {
  66
  67     SysBusDevice parent;
  68
  69     uint32_t config; /* 0x0000: RC4030 config register */
  70     uint32_t revision; /* 0x0008: RC4030 Revision register */
  71     uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
  72
  73     /* DMA */
  74     uint32_t dma_regs[8][4];
  75     uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
  76     uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
  77
  78     /* cache */
  79     uint32_t cache_maint; /* 0x0030: Cache Maintenance */
  80     uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
  81     uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
  82     uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
  83     uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
  84     uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
  85
  86     uint32_t nmi_interrupt; /* 0x0200: interrupt source */
  87     uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */
  88     uint32_t nvram_protect; /* 0x0220: NV ram protect register */
  89     uint32_t rem_speed[16];
  90     uint32_t imr_jazz; /* Local bus int enable mask */
  91     uint32_t isr_jazz; /* Local bus int source */
  92
  93     /* timer */
  94     QEMUTimer *periodic_timer;
  95     uint32_t itr; /* Interval timer reload */
  96
  97     qemu_irq timer_irq;
  98     qemu_irq jazz_bus_irq;
  99
 100     /* whole DMA memory region, root of DMA address space */
 101     IOMMUMemoryRegion dma_mr;
 102     AddressSpace dma_as;
 103
 104     MemoryRegion iomem_chipset;
 105     MemoryRegion iomem_jazzio;
 106 };
 107
 108 static void set_next_tick(rc4030State *s)
 109 {
 110     uint32_t tm_hz;
 111     qemu_irq_lower(s->timer_irq);
 112
 113     tm_hz = 1000 / (s->itr + 1);
 114
 115     timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 116                    NANOSECONDS_PER_SECOND / tm_hz);
 117 }
 118
 119 /* called for accesses to rc4030 */
 120 static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size)
 121 {
 122     rc4030State *s = opaque;
 123     uint32_t val;
 124
 125     addr &= 0x3fff;
 126     switch (addr & ~0x3) {
 127     /* Global config register */
 128     case 0x0000:
 129         val = s->config;
 130         break;
 131     /* Revision register */
 132     case 0x0008:
 133         val = s->revision;
 134         break;
 135     /* Invalid Address register */
 136     case 0x0010:
 137         val = s->invalid_address_register;
 138         break;
 139     /* DMA transl. table base */
 140     case 0x0018:
 141         val = s->dma_tl_base;
 142         break;
 143     /* DMA transl. table limit */
 144     case 0x0020:
 145         val = s->dma_tl_limit;
 146         break;
 147     /* Remote Failed Address */
 148     case 0x0038:
 149         val = s->remote_failed_address;
 150         break;
 151     /* Memory Failed Address */
 152     case 0x0040:
 153         val = s->memory_failed_address;
 154         break;
 155     /* I/O Cache Byte Mask */
 156     case 0x0058:
 157         val = s->cache_bmask;
 158         /* HACK */
 159         if (s->cache_bmask == (uint32_t)-1) {
 160             s->cache_bmask = 0;
 161         }
 162         break;
 163     /* Remote Speed Registers */
 164     case 0x0070:
 165     case 0x0078:
 166     case 0x0080:
 167     case 0x0088:
 168     case 0x0090:
 169     case 0x0098:
 170     case 0x00a0:
 171     case 0x00a8:
 172     case 0x00b0:
 173     case 0x00b8:
 174     case 0x00c0:
 175     case 0x00c8:
 176     case 0x00d0:
 177     case 0x00d8:
 178     case 0x00e0:
 179     case 0x00e8:
 180         val = s->rem_speed[(addr - 0x0070) >> 3];
 181         break;
 182     /* DMA channel base address */
 183     case 0x0100:
 184     case 0x0108:
 185     case 0x0110:
 186     case 0x0118:
 187     case 0x0120:
 188     case 0x0128:
 189     case 0x0130:
 190     case 0x0138:
 191     case 0x0140:
 192     case 0x0148:
 193     case 0x0150:
 194     case 0x0158:
 195     case 0x0160:
 196     case 0x0168:
 197     case 0x0170:
 198     case 0x0178:
 199     case 0x0180:
 200     case 0x0188:
 201     case 0x0190:
 202     case 0x0198:
 203     case 0x01a0:
 204     case 0x01a8:
 205     case 0x01b0:
 206     case 0x01b8:
 207     case 0x01c0:
 208     case 0x01c8:
 209     case 0x01d0:
 210     case 0x01d8:
 211     case 0x01e0:
 212     case 0x01e8:
 213     case 0x01f0:
 214     case 0x01f8:
 215         {
 216             int entry = (addr - 0x0100) >> 5;
 217             int idx = (addr & 0x1f) >> 3;
 218             val = s->dma_regs[entry][idx];
 219         }
 220         break;
 221     /* Interrupt source */
 222     case 0x0200:
 223         val = s->nmi_interrupt;
 224         break;
 225     /* Error type */
 226     case 0x0208:
 227         val = 0;
 228         break;
 229     /* Memory refresh rate */
 230     case 0x0210:
 231         val = s->memory_refresh_rate;
 232         break;
 233     /* NV ram protect register */
 234     case 0x0220:
 235         val = s->nvram_protect;
 236         break;
 237     /* Interval timer count */
 238     case 0x0230:
 239         val = 0;
 240         qemu_irq_lower(s->timer_irq);
 241         break;
 242     /* EISA interrupt */
 243     case 0x0238:
 244         val = 7; /* FIXME: should be read from EISA controller */
 245         break;
 246     default:
 247         qemu_log_mask(LOG_GUEST_ERROR,
 248                       "rc4030: invalid read at 0x%x", (int)addr);
 249         val = 0;
 250         break;
 251     }
 252
 253     if ((addr & ~3) != 0x230) {
 254         trace_rc4030_read(addr, val);
 255     }
 256
 257     return val;
 258 }
 259
 260 static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
 261                          unsigned int size)
 262 {
 263     rc4030State *s = opaque;
 264     uint32_t val = data;
 265     addr &= 0x3fff;
 266
 267     trace_rc4030_write(addr, val);
 268
 269     switch (addr & ~0x3) {
 270     /* Global config register */
 271     case 0x0000:
 272         s->config = val;
 273         break;
 274     /* DMA transl. table base */
 275     case 0x0018:
 276         s->dma_tl_base = val;
 277         break;
 278     /* DMA transl. table limit */
 279     case 0x0020:
 280         s->dma_tl_limit = val;
 281         break;
 282     /* DMA transl. table invalidated */
 283     case 0x0028:
 284         break;
 285     /* Cache Maintenance */
 286     case 0x0030:
 287         s->cache_maint = val;
 288         break;
 289     /* I/O Cache Physical Tag */
 290     case 0x0048:
 291         s->cache_ptag = val;
 292         break;
 293     /* I/O Cache Logical Tag */
 294     case 0x0050:
 295         s->cache_ltag = val;
 296         break;
 297     /* I/O Cache Byte Mask */
 298     case 0x0058:
 299         s->cache_bmask |= val; /* HACK */
 300         break;
 301     /* I/O Cache Buffer Window */
 302     case 0x0060:
 303         /* HACK */
 304         if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
 305             hwaddr dest = s->cache_ptag & ~0x1;
 306             dest += (s->cache_maint & 0x3) << 3;
 307             cpu_physical_memory_write(dest, &val, 4);
 308         }
 309         break;
 310     /* Remote Speed Registers */
 311     case 0x0070:
 312     case 0x0078:
 313     case 0x0080:
 314     case 0x0088:
 315     case 0x0090:
 316     case 0x0098:
 317     case 0x00a0:
 318     case 0x00a8:
 319     case 0x00b0:
 320     case 0x00b8:
 321     case 0x00c0:
 322     case 0x00c8:
 323     case 0x00d0:
 324     case 0x00d8:
 325     case 0x00e0:
 326     case 0x00e8:
 327         s->rem_speed[(addr - 0x0070) >> 3] = val;
 328         break;
 329     /* DMA channel base address */
 330     case 0x0100:
 331     case 0x0108:
 332     case 0x0110:
 333     case 0x0118:
 334     case 0x0120:
 335     case 0x0128:
 336     case 0x0130:
 337     case 0x0138:
 338     case 0x0140:
 339     case 0x0148:
 340     case 0x0150:
 341     case 0x0158:
 342     case 0x0160:
 343     case 0x0168:
 344     case 0x0170:
 345     case 0x0178:
 346     case 0x0180:
 347     case 0x0188:
 348     case 0x0190:
 349     case 0x0198:
 350     case 0x01a0:
 351     case 0x01a8:
 352     case 0x01b0:
 353     case 0x01b8:
 354     case 0x01c0:
 355     case 0x01c8:
 356     case 0x01d0:
 357     case 0x01d8:
 358     case 0x01e0:
 359     case 0x01e8:
 360     case 0x01f0:
 361     case 0x01f8:
 362         {
 363             int entry = (addr - 0x0100) >> 5;
 364             int idx = (addr & 0x1f) >> 3;
 365             s->dma_regs[entry][idx] = val;
 366         }
 367         break;
 368     /* Memory refresh rate */
 369     case 0x0210:
 370         s->memory_refresh_rate = val;
 371         break;
 372     /* Interval timer reload */
 373     case 0x0228:
 374         s->itr = val & 0x01FF;
 375         qemu_irq_lower(s->timer_irq);
 376         set_next_tick(s);
 377         break;
 378     /* EISA interrupt */
 379     case 0x0238:
 380         break;
 381     default:
 382         qemu_log_mask(LOG_GUEST_ERROR,
 383                       "rc4030: invalid write of 0x%02x at 0x%x",
 384                       val, (int)addr);
 385         break;
 386     }
 387 }
 388
 389 static const MemoryRegionOps rc4030_ops = {
 390     .read = rc4030_read,
 391     .write = rc4030_write,
 392     .impl.min_access_size = 4,
 393     .impl.max_access_size = 4,
 394     .endianness = DEVICE_NATIVE_ENDIAN,
 395 };
 396
 397 static void update_jazz_irq(rc4030State *s)
 398 {
 399     uint16_t pending;
 400
 401     pending = s->isr_jazz & s->imr_jazz;
 402
 403     if (pending != 0) {
 404         qemu_irq_raise(s->jazz_bus_irq);
 405     } else {
 406         qemu_irq_lower(s->jazz_bus_irq);
 407     }
 408 }
 409
 410 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
 411 {
 412     rc4030State *s = opaque;
 413
 414     if (level) {
 415         s->isr_jazz |= 1 << irq;
 416     } else {
 417         s->isr_jazz &= ~(1 << irq);
 418     }
 419
 420     update_jazz_irq(s);
 421 }
 422
 423 static void rc4030_periodic_timer(void *opaque)
 424 {
 425     rc4030State *s = opaque;
 426
 427     set_next_tick(s);
 428     qemu_irq_raise(s->timer_irq);
 429 }
 430
 431 static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size)
 432 {
 433     rc4030State *s = opaque;
 434     uint32_t val;
 435     uint32_t irq;
 436     addr &= 0xfff;
 437
 438     switch (addr) {
 439     /* Local bus int source */
 440     case 0x00: {
 441         uint32_t pending = s->isr_jazz & s->imr_jazz;
 442         val = 0;
 443         irq = 0;
 444         while (pending) {
 445             if (pending & 1) {
 446                 val = (irq + 1) << 2;
 447                 break;
 448             }
 449             irq++;
 450             pending >>= 1;
 451         }
 452         break;
 453     }
 454     /* Local bus int enable mask */
 455     case 0x02:
 456         val = s->imr_jazz;
 457         break;
 458     default:
 459         qemu_log_mask(LOG_GUEST_ERROR,
 460                       "rc4030/jazzio: invalid read at 0x%x", (int)addr);
 461         val = 0;
 462         break;
 463     }
 464
 465     trace_jazzio_read(addr, val);
 466
 467     return val;
 468 }
 469
 470 static void jazzio_write(void *opaque, hwaddr addr, uint64_t data,
 471                          unsigned int size)
 472 {
 473     rc4030State *s = opaque;
 474     uint32_t val = data;
 475     addr &= 0xfff;
 476
 477     trace_jazzio_write(addr, val);
 478
 479     switch (addr) {
 480     /* Local bus int enable mask */
 481     case 0x02:
 482         s->imr_jazz = val;
 483         update_jazz_irq(s);
 484         break;
 485     default:
 486         qemu_log_mask(LOG_GUEST_ERROR,
 487                       "rc4030/jazzio: invalid write of 0x%02x at 0x%x",
 488                       val, (int)addr);
 489         break;
 490     }
 491 }
 492
 493 static const MemoryRegionOps jazzio_ops = {
 494     .read = jazzio_read,
 495     .write = jazzio_write,
 496     .impl.min_access_size = 2,
 497     .impl.max_access_size = 2,
 498     .endianness = DEVICE_NATIVE_ENDIAN,
 499 };
 500
 501 static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
 502                                           IOMMUAccessFlags flag, int iommu_idx)
 503 {
 504     rc4030State *s = container_of(iommu, rc4030State, dma_mr);
 505     IOMMUTLBEntry ret = {
 506         .target_as = &address_space_memory,
 507         .iova = addr & ~(DMA_PAGESIZE - 1),
 508         .translated_addr = 0,
 509         .addr_mask = DMA_PAGESIZE - 1,
 510         .perm = IOMMU_NONE,
 511     };
 512     uint64_t i, entry_address;
 513     dma_pagetable_entry entry;
 514
 515     i = addr / DMA_PAGESIZE;
 516     if (i < s->dma_tl_limit / sizeof(entry)) {
 517         entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
 518         if (address_space_read(ret.target_as, entry_address,
 519                                MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry))
 520                 == MEMTX_OK) {
 521             ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
 522             ret.perm = IOMMU_RW;
 523         }
 524     }
 525
 526     return ret;
 527 }
 528
 529 static void rc4030_reset(DeviceState *dev)
 530 {
 531     rc4030State *s = RC4030(dev);
 532     int i;
 533
 534     s->config = 0x410; /* some boards seem to accept 0x104 too */
 535     s->revision = 1;
 536     s->invalid_address_register = 0;
 537
 538     memset(s->dma_regs, 0, sizeof(s->dma_regs));
 539
 540     s->remote_failed_address = s->memory_failed_address = 0;
 541     s->cache_maint = 0;
 542     s->cache_ptag = s->cache_ltag = 0;
 543     s->cache_bmask = 0;
 544
 545     s->memory_refresh_rate = 0x18186;
 546     s->nvram_protect = 7;
 547     for (i = 0; i < 15; i++) {
 548         s->rem_speed[i] = 7;
 549     }
 550     s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
 551     s->isr_jazz = 0;
 552
 553     s->itr = 0;
 554
 555     qemu_irq_lower(s->timer_irq);
 556     qemu_irq_lower(s->jazz_bus_irq);
 557 }
 558
 559 static int rc4030_post_load(void *opaque, int version_id)
 560 {
 561     rc4030State *s = opaque;
 562
 563     set_next_tick(s);
 564     update_jazz_irq(s);
 565
 566     return 0;
 567 }
 568
 569 static const VMStateDescription vmstate_rc4030 = {
 570     .name = "rc4030",
 571     .version_id = 3,
 572     .post_load = rc4030_post_load,
 573     .fields = (VMStateField []) {
 574         VMSTATE_UINT32(config, rc4030State),
 575         VMSTATE_UINT32(invalid_address_register, rc4030State),
 576         VMSTATE_UINT32_2DARRAY(dma_regs, rc4030State, 8, 4),
 577         VMSTATE_UINT32(dma_tl_base, rc4030State),
 578         VMSTATE_UINT32(dma_tl_limit, rc4030State),
 579         VMSTATE_UINT32(cache_maint, rc4030State),
 580         VMSTATE_UINT32(remote_failed_address, rc4030State),
 581         VMSTATE_UINT32(memory_failed_address, rc4030State),
 582         VMSTATE_UINT32(cache_ptag, rc4030State),
 583         VMSTATE_UINT32(cache_ltag, rc4030State),
 584         VMSTATE_UINT32(cache_bmask, rc4030State),
 585         VMSTATE_UINT32(memory_refresh_rate, rc4030State),
 586         VMSTATE_UINT32(nvram_protect, rc4030State),
 587         VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16),
 588         VMSTATE_UINT32(imr_jazz, rc4030State),
 589         VMSTATE_UINT32(isr_jazz, rc4030State),
 590         VMSTATE_UINT32(itr, rc4030State),
 591         VMSTATE_END_OF_LIST()
 592     }
 593 };
 594
 595 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf,
 596                           int len, bool is_write)
 597 {
 598     rc4030State *s = opaque;
 599     hwaddr dma_addr;
 600     int dev_to_mem;
 601
 602     s->dma_regs[n][DMA_REG_ENABLE] &=
 603            ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
 604
 605     /* Check DMA channel consistency */
 606     dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
 607     if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
 608         (is_write != dev_to_mem)) {
 609         s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
 610         s->nmi_interrupt |= 1 << n;
 611         return;
 612     }
 613
 614     /* Get start address and len */
 615     if (len > s->dma_regs[n][DMA_REG_COUNT]) {
 616         len = s->dma_regs[n][DMA_REG_COUNT];
 617     }
 618     dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
 619
 620     /* Read/write data at right place */
 621     address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED,
 622                      buf, len, is_write);
 623
 624     s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
 625     s->dma_regs[n][DMA_REG_COUNT] -= len;
 626 }
 627
 628 struct rc4030DMAState {
 629     void *opaque;
 630     int n;
 631 };
 632
 633 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
 634 {
 635     rc4030_dma s = dma;
 636     rc4030_do_dma(s->opaque, s->n, buf, len, false);
 637 }
 638
 639 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
 640 {
 641     rc4030_dma s = dma;
 642     rc4030_do_dma(s->opaque, s->n, buf, len, true);
 643 }
 644
 645 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
 646 {
 647     rc4030_dma *s;
 648     struct rc4030DMAState *p;
 649     int i;
 650
 651     s = (rc4030_dma *)g_new0(rc4030_dma, n);
 652     p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n);
 653     for (i = 0; i < n; i++) {
 654         p->opaque = opaque;
 655         p->n = i;
 656         s[i] = p;
 657         p++;
 658     }
 659     return s;
 660 }
 661
 662 static void rc4030_initfn(Object *obj)
 663 {
 664     DeviceState *dev = DEVICE(obj);
 665     rc4030State *s = RC4030(obj);
 666     SysBusDevice *sysbus = SYS_BUS_DEVICE(obj);
 667
 668     qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16);
 669
 670     sysbus_init_irq(sysbus, &s->timer_irq);
 671     sysbus_init_irq(sysbus, &s->jazz_bus_irq);
 672
 673     sysbus_init_mmio(sysbus, &s->iomem_chipset);
 674     sysbus_init_mmio(sysbus, &s->iomem_jazzio);
 675 }
 676
 677 static void rc4030_realize(DeviceState *dev, Error **errp)
 678 {
 679     rc4030State *s = RC4030(dev);
 680     Object *o = OBJECT(dev);
 681
 682     s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 683                                      rc4030_periodic_timer, s);
 684
 685     memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s,
 686                           "rc4030.chipset", 0x300);
 687     memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s,
 688                           "rc4030.jazzio", 0x00001000);
 689
 690     memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),
 691                              TYPE_RC4030_IOMMU_MEMORY_REGION,
 692                              o, "rc4030.dma", 4 * GiB);
 693     address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma");
 694 }
 695
 696 static void rc4030_unrealize(DeviceState *dev)
 697 {
 698     rc4030State *s = RC4030(dev);
 699
 700     timer_free(s->periodic_timer);
 701
 702     address_space_destroy(&s->dma_as);
 703     object_unparent(OBJECT(&s->dma_mr));
 704 }
 705
 706 static void rc4030_class_init(ObjectClass *klass, void *class_data)
 707 {
 708     DeviceClass *dc = DEVICE_CLASS(klass);
 709
 710     dc->realize = rc4030_realize;
 711     dc->unrealize = rc4030_unrealize;
 712     dc->reset = rc4030_reset;
 713     dc->vmsd = &vmstate_rc4030;
 714 }
 715
 716 static const TypeInfo rc4030_info = {
 717     .name = TYPE_RC4030,
 718     .parent = TYPE_SYS_BUS_DEVICE,
 719     .instance_size = sizeof(rc4030State),
 720     .instance_init = rc4030_initfn,
 721     .class_init = rc4030_class_init,
 722 };
 723
 724 static void rc4030_iommu_memory_region_class_init(ObjectClass *klass,
 725                                                   void *data)
 726 {
 727     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 728
 729     imrc->translate = rc4030_dma_translate;
 730 }
 731
 732 static const TypeInfo rc4030_iommu_memory_region_info = {
 733     .parent = TYPE_IOMMU_MEMORY_REGION,
 734     .name = TYPE_RC4030_IOMMU_MEMORY_REGION,
 735     .class_init = rc4030_iommu_memory_region_class_init,
 736 };
 737
 738 static void rc4030_register_types(void)
 739 {
 740     type_register_static(&rc4030_info);
 741     type_register_static(&rc4030_iommu_memory_region_info);
 742 }
 743
 744 type_init(rc4030_register_types)
 745
 746 DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr)
 747 {
 748     DeviceState *dev;
 749
 750     dev = qdev_new(TYPE_RC4030);
 751     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 752
 753     *dmas = rc4030_allocate_dmas(dev, 4);
 754     *dma_mr = &RC4030(dev)->dma_mr;
 755     return dev;
 756 }