hw/dma/puv3_dma.c

   1 /*
   2  * DMA device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "qom/object.h"
  15
  16 #undef DEBUG_PUV3
  17 #include "hw/unicore32/puv3.h"
  18 #include "qemu/module.h"
  19 #include "qemu/log.h"
  20
  21 #define PUV3_DMA_CH_NR          (6)
  22 #define PUV3_DMA_CH_MASK        (0xff)
  23 #define PUV3_DMA_CH(offset)     ((offset) >> 8)
  24
  25 #define TYPE_PUV3_DMA "puv3_dma"
  26 typedef struct PUV3DMAState PUV3DMAState;
  27 DECLARE_INSTANCE_CHECKER(PUV3DMAState, PUV3_DMA,
  28                          TYPE_PUV3_DMA)
  29
  30 struct PUV3DMAState {
  31     SysBusDevice parent_obj;
  32
  33     MemoryRegion iomem;
  34     uint32_t reg_CFG[PUV3_DMA_CH_NR];
  35 };
  36
  37 static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
  38         unsigned size)
  39 {
  40     PUV3DMAState *s = opaque;
  41     uint32_t ret = 0;
  42
  43     assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  44
  45     switch (offset & PUV3_DMA_CH_MASK) {
  46     case 0x10:
  47         ret = s->reg_CFG[PUV3_DMA_CH(offset)];
  48         break;
  49     default:
  50         qemu_log_mask(LOG_GUEST_ERROR,
  51                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  52                       __func__, offset);
  53     }
  54     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  55
  56     return ret;
  57 }
  58
  59 static void puv3_dma_write(void *opaque, hwaddr offset,
  60         uint64_t value, unsigned size)
  61 {
  62     PUV3DMAState *s = opaque;
  63
  64     assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  65
  66     switch (offset & PUV3_DMA_CH_MASK) {
  67     case 0x10:
  68         s->reg_CFG[PUV3_DMA_CH(offset)] = value;
  69         break;
  70     default:
  71         qemu_log_mask(LOG_GUEST_ERROR,
  72                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  73                       __func__, offset);
  74     }
  75     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  76 }
  77
  78 static const MemoryRegionOps puv3_dma_ops = {
  79     .read = puv3_dma_read,
  80     .write = puv3_dma_write,
  81     .impl = {
  82         .min_access_size = 4,
  83         .max_access_size = 4,
  84     },
  85     .endianness = DEVICE_NATIVE_ENDIAN,
  86 };
  87
  88 static void puv3_dma_realize(DeviceState *dev, Error **errp)
  89 {
  90     PUV3DMAState *s = PUV3_DMA(dev);
  91     int i;
  92
  93     for (i = 0; i < PUV3_DMA_CH_NR; i++) {
  94         s->reg_CFG[i] = 0x0;
  95     }
  96
  97     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
  98             PUV3_REGS_OFFSET);
  99     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 100 }
 101
 102 static void puv3_dma_class_init(ObjectClass *klass, void *data)
 103 {
 104     DeviceClass *dc = DEVICE_CLASS(klass);
 105
 106     dc->realize = puv3_dma_realize;
 107 }
 108
 109 static const TypeInfo puv3_dma_info = {
 110     .name = TYPE_PUV3_DMA,
 111     .parent = TYPE_SYS_BUS_DEVICE,
 112     .instance_size = sizeof(PUV3DMAState),
 113     .class_init = puv3_dma_class_init,
 114 };
 115
 116 static void puv3_dma_register_type(void)
 117 {
 118     type_register_static(&puv3_dma_info);
 119 }
 120
 121 type_init(puv3_dma_register_type)