hw/char/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/irq.h"
  27 #include "hw/qdev-properties.h"
  28 #include "hw/sysbus.h"
  29 #include "migration/vmstate.h"
  30 #include "trace.h"
  31 #include "chardev/char-fe.h"
  32 #include "qemu/error-report.h"
  33 #include "qemu/module.h"
  34 #include "qom/object.h"
  35
  36 enum {
  37     R_RXTX = 0,
  38     R_IER,
  39     R_IIR,
  40     R_LCR,
  41     R_MCR,
  42     R_LSR,
  43     R_MSR,
  44     R_DIV,
  45     R_MAX
  46 };
  47
  48 enum {
  49     IER_RBRI = (1<<0),
  50     IER_THRI = (1<<1),
  51     IER_RLSI = (1<<2),
  52     IER_MSI  = (1<<3),
  53 };
  54
  55 enum {
  56     IIR_STAT = (1<<0),
  57     IIR_ID0  = (1<<1),
  58     IIR_ID1  = (1<<2),
  59 };
  60
  61 enum {
  62     LCR_WLS0 = (1<<0),
  63     LCR_WLS1 = (1<<1),
  64     LCR_STB  = (1<<2),
  65     LCR_PEN  = (1<<3),
  66     LCR_EPS  = (1<<4),
  67     LCR_SP   = (1<<5),
  68     LCR_SB   = (1<<6),
  69 };
  70
  71 enum {
  72     MCR_DTR  = (1<<0),
  73     MCR_RTS  = (1<<1),
  74 };
  75
  76 enum {
  77     LSR_DR   = (1<<0),
  78     LSR_OE   = (1<<1),
  79     LSR_PE   = (1<<2),
  80     LSR_FE   = (1<<3),
  81     LSR_BI   = (1<<4),
  82     LSR_THRE = (1<<5),
  83     LSR_TEMT = (1<<6),
  84 };
  85
  86 enum {
  87     MSR_DCTS = (1<<0),
  88     MSR_DDSR = (1<<1),
  89     MSR_TERI = (1<<2),
  90     MSR_DDCD = (1<<3),
  91     MSR_CTS  = (1<<4),
  92     MSR_DSR  = (1<<5),
  93     MSR_RI   = (1<<6),
  94     MSR_DCD  = (1<<7),
  95 };
  96
  97 #define TYPE_LM32_UART "lm32-uart"
  98 typedef struct LM32UartState LM32UartState;
  99 DECLARE_INSTANCE_CHECKER(LM32UartState, LM32_UART,
 100                          TYPE_LM32_UART)
 101
 102 struct LM32UartState {
 103     SysBusDevice parent_obj;
 104
 105     MemoryRegion iomem;
 106     CharBackend chr;
 107     qemu_irq irq;
 108
 109     uint32_t regs[R_MAX];
 110 };
 111
 112 static void uart_update_irq(LM32UartState *s)
 113 {
 114     unsigned int irq;
 115
 116     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 117             && (s->regs[R_IER] & IER_RLSI)) {
 118         irq = 1;
 119         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 120     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 121         irq = 1;
 122         s->regs[R_IIR] = IIR_ID1;
 123     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 124         irq = 1;
 125         s->regs[R_IIR] = IIR_ID0;
 126     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 127         irq = 1;
 128         s->regs[R_IIR] = 0;
 129     } else {
 130         irq = 0;
 131         s->regs[R_IIR] = IIR_STAT;
 132     }
 133
 134     trace_lm32_uart_irq_state(irq);
 135     qemu_set_irq(s->irq, irq);
 136 }
 137
 138 static uint64_t uart_read(void *opaque, hwaddr addr,
 139                           unsigned size)
 140 {
 141     LM32UartState *s = opaque;
 142     uint32_t r = 0;
 143
 144     addr >>= 2;
 145     switch (addr) {
 146     case R_RXTX:
 147         r = s->regs[R_RXTX];
 148         s->regs[R_LSR] &= ~LSR_DR;
 149         uart_update_irq(s);
 150         qemu_chr_fe_accept_input(&s->chr);
 151         break;
 152     case R_IIR:
 153     case R_LSR:
 154     case R_MSR:
 155         r = s->regs[addr];
 156         break;
 157     case R_IER:
 158     case R_LCR:
 159     case R_MCR:
 160     case R_DIV:
 161         error_report("lm32_uart: read access to write only register 0x"
 162                 TARGET_FMT_plx, addr << 2);
 163         break;
 164     default:
 165         error_report("lm32_uart: read access to unknown register 0x"
 166                 TARGET_FMT_plx, addr << 2);
 167         break;
 168     }
 169
 170     trace_lm32_uart_memory_read(addr << 2, r);
 171     return r;
 172 }
 173
 174 static void uart_write(void *opaque, hwaddr addr,
 175                        uint64_t value, unsigned size)
 176 {
 177     LM32UartState *s = opaque;
 178     unsigned char ch = value;
 179
 180     trace_lm32_uart_memory_write(addr, value);
 181
 182     addr >>= 2;
 183     switch (addr) {
 184     case R_RXTX:
 185         /* XXX this blocks entire thread. Rewrite to use
 186          * qemu_chr_fe_write and background I/O callbacks */
 187         qemu_chr_fe_write_all(&s->chr, &ch, 1);
 188         break;
 189     case R_IER:
 190     case R_LCR:
 191     case R_MCR:
 192     case R_DIV:
 193         s->regs[addr] = value;
 194         break;
 195     case R_IIR:
 196     case R_LSR:
 197     case R_MSR:
 198         error_report("lm32_uart: write access to read only register 0x"
 199                 TARGET_FMT_plx, addr << 2);
 200         break;
 201     default:
 202         error_report("lm32_uart: write access to unknown register 0x"
 203                 TARGET_FMT_plx, addr << 2);
 204         break;
 205     }
 206     uart_update_irq(s);
 207 }
 208
 209 static const MemoryRegionOps uart_ops = {
 210     .read = uart_read,
 211     .write = uart_write,
 212     .endianness = DEVICE_NATIVE_ENDIAN,
 213     .valid = {
 214         .min_access_size = 4,
 215         .max_access_size = 4,
 216     },
 217 };
 218
 219 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 220 {
 221     LM32UartState *s = opaque;
 222
 223     if (s->regs[R_LSR] & LSR_DR) {
 224         s->regs[R_LSR] |= LSR_OE;
 225     }
 226
 227     s->regs[R_LSR] |= LSR_DR;
 228     s->regs[R_RXTX] = *buf;
 229
 230     uart_update_irq(s);
 231 }
 232
 233 static int uart_can_rx(void *opaque)
 234 {
 235     LM32UartState *s = opaque;
 236
 237     return !(s->regs[R_LSR] & LSR_DR);
 238 }
 239
 240 static void uart_event(void *opaque, QEMUChrEvent event)
 241 {
 242 }
 243
 244 static void uart_reset(DeviceState *d)
 245 {
 246     LM32UartState *s = LM32_UART(d);
 247     int i;
 248
 249     for (i = 0; i < R_MAX; i++) {
 250         s->regs[i] = 0;
 251     }
 252
 253     /* defaults */
 254     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 255 }
 256
 257 static void lm32_uart_init(Object *obj)
 258 {
 259     LM32UartState *s = LM32_UART(obj);
 260     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 261
 262     sysbus_init_irq(dev, &s->irq);
 263
 264     memory_region_init_io(&s->iomem, obj, &uart_ops, s,
 265                           "uart", R_MAX * 4);
 266     sysbus_init_mmio(dev, &s->iomem);
 267 }
 268
 269 static void lm32_uart_realize(DeviceState *dev, Error **errp)
 270 {
 271     LM32UartState *s = LM32_UART(dev);
 272
 273     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 274                              uart_event, NULL, s, NULL, true);
 275 }
 276
 277 static const VMStateDescription vmstate_lm32_uart = {
 278     .name = "lm32-uart",
 279     .version_id = 1,
 280     .minimum_version_id = 1,
 281     .fields = (VMStateField[]) {
 282         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 283         VMSTATE_END_OF_LIST()
 284     }
 285 };
 286
 287 static Property lm32_uart_properties[] = {
 288     DEFINE_PROP_CHR("chardev", LM32UartState, chr),
 289     DEFINE_PROP_END_OF_LIST(),
 290 };
 291
 292 static void lm32_uart_class_init(ObjectClass *klass, void *data)
 293 {
 294     DeviceClass *dc = DEVICE_CLASS(klass);
 295
 296     dc->reset = uart_reset;
 297     dc->vmsd = &vmstate_lm32_uart;
 298     device_class_set_props(dc, lm32_uart_properties);
 299     dc->realize = lm32_uart_realize;
 300 }
 301
 302 static const TypeInfo lm32_uart_info = {
 303     .name          = TYPE_LM32_UART,
 304     .parent        = TYPE_SYS_BUS_DEVICE,
 305     .instance_size = sizeof(LM32UartState),
 306     .instance_init = lm32_uart_init,
 307     .class_init    = lm32_uart_class_init,
 308 };
 309
 310 static void lm32_uart_register_types(void)
 311 {
 312     type_register_static(&lm32_uart_info);
 313 }
 314
 315 type_init(lm32_uart_register_types)