hw/char/exynos4210_uart.c

   1 /*
   2  *  Exynos4210 UART Emulation
   3  *
   4  *  Copyright (C) 2011 Samsung Electronics Co Ltd.
   5  *    Maksim Kozlov, <m.kozlov@samsung.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License as published by the
   9  *  Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "qapi/error.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/module.h"
  28 #include "qemu/timer.h"
  29 #include "chardev/char-fe.h"
  30 #include "chardev/char-serial.h"
  31
  32 #include "hw/arm/exynos4210.h"
  33 #include "hw/irq.h"
  34 #include "hw/qdev-properties.h"
  35
  36 #include "trace.h"
  37 #include "qom/object.h"
  38
  39 /*
  40  *  Offsets for UART registers relative to SFR base address
  41  *  for UARTn
  42  *
  43  */
  44 #define ULCON      0x0000 /* Line Control             */
  45 #define UCON       0x0004 /* Control                  */
  46 #define UFCON      0x0008 /* FIFO Control             */
  47 #define UMCON      0x000C /* Modem Control            */
  48 #define UTRSTAT    0x0010 /* Tx/Rx Status             */
  49 #define UERSTAT    0x0014 /* UART Error Status        */
  50 #define UFSTAT     0x0018 /* FIFO Status              */
  51 #define UMSTAT     0x001C /* Modem Status             */
  52 #define UTXH       0x0020 /* Transmit Buffer          */
  53 #define URXH       0x0024 /* Receive Buffer           */
  54 #define UBRDIV     0x0028 /* Baud Rate Divisor        */
  55 #define UFRACVAL   0x002C /* Divisor Fractional Value */
  56 #define UINTP      0x0030 /* Interrupt Pending        */
  57 #define UINTSP     0x0034 /* Interrupt Source Pending */
  58 #define UINTM      0x0038 /* Interrupt Mask           */
  59
  60 /*
  61  * for indexing register in the uint32_t array
  62  *
  63  * 'reg' - register offset (see offsets definitions above)
  64  *
  65  */
  66 #define I_(reg) (reg / sizeof(uint32_t))
  67
  68 typedef struct Exynos4210UartReg {
  69     const char         *name; /* the only reason is the debug output */
  70     hwaddr  offset;
  71     uint32_t            reset_value;
  72 } Exynos4210UartReg;
  73
  74 static const Exynos4210UartReg exynos4210_uart_regs[] = {
  75     {"ULCON",    ULCON,    0x00000000},
  76     {"UCON",     UCON,     0x00003000},
  77     {"UFCON",    UFCON,    0x00000000},
  78     {"UMCON",    UMCON,    0x00000000},
  79     {"UTRSTAT",  UTRSTAT,  0x00000006}, /* RO */
  80     {"UERSTAT",  UERSTAT,  0x00000000}, /* RO */
  81     {"UFSTAT",   UFSTAT,   0x00000000}, /* RO */
  82     {"UMSTAT",   UMSTAT,   0x00000000}, /* RO */
  83     {"UTXH",     UTXH,     0x5c5c5c5c}, /* WO, undefined reset value*/
  84     {"URXH",     URXH,     0x00000000}, /* RO */
  85     {"UBRDIV",   UBRDIV,   0x00000000},
  86     {"UFRACVAL", UFRACVAL, 0x00000000},
  87     {"UINTP",    UINTP,    0x00000000},
  88     {"UINTSP",   UINTSP,   0x00000000},
  89     {"UINTM",    UINTM,    0x00000000},
  90 };
  91
  92 #define EXYNOS4210_UART_REGS_MEM_SIZE    0x3C
  93
  94 /* UART FIFO Control */
  95 #define UFCON_FIFO_ENABLE                    0x1
  96 #define UFCON_Rx_FIFO_RESET                  0x2
  97 #define UFCON_Tx_FIFO_RESET                  0x4
  98 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT    8
  99 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
 100 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT    4
 101 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
 102
 103 /* Uart FIFO Status */
 104 #define UFSTAT_Rx_FIFO_COUNT        0xff
 105 #define UFSTAT_Rx_FIFO_FULL         0x100
 106 #define UFSTAT_Rx_FIFO_ERROR        0x200
 107 #define UFSTAT_Tx_FIFO_COUNT_SHIFT  16
 108 #define UFSTAT_Tx_FIFO_COUNT        (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
 109 #define UFSTAT_Tx_FIFO_FULL_SHIFT   24
 110 #define UFSTAT_Tx_FIFO_FULL         (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
 111
 112 /* UART Interrupt Source Pending */
 113 #define UINTSP_RXD      0x1 /* Receive interrupt  */
 114 #define UINTSP_ERROR    0x2 /* Error interrupt    */
 115 #define UINTSP_TXD      0x4 /* Transmit interrupt */
 116 #define UINTSP_MODEM    0x8 /* Modem interrupt    */
 117
 118 /* UART Line Control */
 119 #define ULCON_IR_MODE_SHIFT   6
 120 #define ULCON_PARITY_SHIFT    3
 121 #define ULCON_STOP_BIT_SHIFT  1
 122
 123 /* UART Tx/Rx Status */
 124 #define UTRSTAT_Rx_TIMEOUT              0x8
 125 #define UTRSTAT_TRANSMITTER_EMPTY       0x4
 126 #define UTRSTAT_Tx_BUFFER_EMPTY         0x2
 127 #define UTRSTAT_Rx_BUFFER_DATA_READY    0x1
 128
 129 /* UART Error Status */
 130 #define UERSTAT_OVERRUN  0x1
 131 #define UERSTAT_PARITY   0x2
 132 #define UERSTAT_FRAME    0x4
 133 #define UERSTAT_BREAK    0x8
 134
 135 typedef struct {
 136     uint8_t    *data;
 137     uint32_t    sp, rp; /* store and retrieve pointers */
 138     uint32_t    size;
 139 } Exynos4210UartFIFO;
 140
 141 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
 142 typedef struct Exynos4210UartState Exynos4210UartState;
 143 DECLARE_INSTANCE_CHECKER(Exynos4210UartState, EXYNOS4210_UART,
 144                          TYPE_EXYNOS4210_UART)
 145
 146 struct Exynos4210UartState {
 147     SysBusDevice parent_obj;
 148
 149     MemoryRegion iomem;
 150
 151     uint32_t             reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
 152     Exynos4210UartFIFO   rx;
 153     Exynos4210UartFIFO   tx;
 154
 155     QEMUTimer *fifo_timeout_timer;
 156     uint64_t wordtime;        /* word time in ns */
 157
 158     CharBackend       chr;
 159     qemu_irq          irq;
 160     qemu_irq          dmairq;
 161
 162     uint32_t channel;
 163
 164 };
 165
 166
 167 /* Used only for tracing */
 168 static const char *exynos4210_uart_regname(hwaddr  offset)
 169 {
 170
 171     int i;
 172
 173     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
 174         if (offset == exynos4210_uart_regs[i].offset) {
 175             return exynos4210_uart_regs[i].name;
 176         }
 177     }
 178
 179     return NULL;
 180 }
 181
 182
 183 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
 184 {
 185     q->data[q->sp] = ch;
 186     q->sp = (q->sp + 1) % q->size;
 187 }
 188
 189 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
 190 {
 191     uint8_t ret = q->data[q->rp];
 192     q->rp = (q->rp + 1) % q->size;
 193     return  ret;
 194 }
 195
 196 static int fifo_elements_number(const Exynos4210UartFIFO *q)
 197 {
 198     if (q->sp < q->rp) {
 199         return q->size - q->rp + q->sp;
 200     }
 201
 202     return q->sp - q->rp;
 203 }
 204
 205 static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
 206 {
 207     return q->size - fifo_elements_number(q);
 208 }
 209
 210 static void fifo_reset(Exynos4210UartFIFO *q)
 211 {
 212     g_free(q->data);
 213     q->data = NULL;
 214
 215     q->data = (uint8_t *)g_malloc0(q->size);
 216
 217     q->sp = 0;
 218     q->rp = 0;
 219 }
 220
 221 static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel,
 222                                                    uint32_t reg)
 223 {
 224     uint32_t level;
 225
 226     switch (channel) {
 227     case 0:
 228         level = reg * 32;
 229         break;
 230     case 1:
 231     case 4:
 232         level = reg * 8;
 233         break;
 234     case 2:
 235     case 3:
 236         level = reg * 2;
 237         break;
 238     default:
 239         level = 0;
 240         trace_exynos_uart_channel_error(channel);
 241         break;
 242     }
 243     return level;
 244 }
 245
 246 static uint32_t
 247 exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
 248 {
 249     uint32_t reg;
 250
 251     reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
 252             UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
 253
 254     return exynos4210_uart_FIFO_trigger_level(s->channel, reg);
 255 }
 256
 257 static uint32_t
 258 exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s)
 259 {
 260     uint32_t reg;
 261
 262     reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >>
 263             UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1;
 264
 265     return exynos4210_uart_FIFO_trigger_level(s->channel, reg);
 266 }
 267
 268 /*
 269  * Update Rx DMA busy signal if Rx DMA is enabled. For simplicity,
 270  * mark DMA as busy if DMA is enabled and the receive buffer is empty.
 271  */
 272 static void exynos4210_uart_update_dmabusy(Exynos4210UartState *s)
 273 {
 274     bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02;
 275     uint32_t count = fifo_elements_number(&s->rx);
 276
 277     if (rx_dma_enabled && !count) {
 278         qemu_irq_raise(s->dmairq);
 279         trace_exynos_uart_dmabusy(s->channel);
 280     } else {
 281         qemu_irq_lower(s->dmairq);
 282         trace_exynos_uart_dmaready(s->channel);
 283     }
 284 }
 285
 286 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
 287 {
 288     /*
 289      * The Tx interrupt is always requested if the number of data in the
 290      * transmit FIFO is smaller than the trigger level.
 291      */
 292     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 293         uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
 294                 UFSTAT_Tx_FIFO_COUNT_SHIFT;
 295
 296         if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
 297             s->reg[I_(UINTSP)] |= UINTSP_TXD;
 298         }
 299
 300         /*
 301          * Rx interrupt if trigger level is reached or if rx timeout
 302          * interrupt is disabled and there is data in the receive buffer
 303          */
 304         count = fifo_elements_number(&s->rx);
 305         if ((count && !(s->reg[I_(UCON)] & 0x80)) ||
 306             count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) {
 307             exynos4210_uart_update_dmabusy(s);
 308             s->reg[I_(UINTSP)] |= UINTSP_RXD;
 309             timer_del(s->fifo_timeout_timer);
 310         }
 311     } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) {
 312         exynos4210_uart_update_dmabusy(s);
 313         s->reg[I_(UINTSP)] |= UINTSP_RXD;
 314     }
 315
 316     s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
 317
 318     if (s->reg[I_(UINTP)]) {
 319         qemu_irq_raise(s->irq);
 320         trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]);
 321     } else {
 322         qemu_irq_lower(s->irq);
 323         trace_exynos_uart_irq_lowered(s->channel);
 324     }
 325 }
 326
 327 static void exynos4210_uart_timeout_int(void *opaque)
 328 {
 329     Exynos4210UartState *s = opaque;
 330
 331     trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)],
 332                                  s->reg[I_(UINTSP)]);
 333
 334     if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) ||
 335         (s->reg[I_(UCON)] & (1 << 11))) {
 336         s->reg[I_(UINTSP)] |= UINTSP_RXD;
 337         s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT;
 338         exynos4210_uart_update_dmabusy(s);
 339         exynos4210_uart_update_irq(s);
 340     }
 341 }
 342
 343 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
 344 {
 345     int speed, parity, data_bits, stop_bits;
 346     QEMUSerialSetParams ssp;
 347     uint64_t uclk_rate;
 348
 349     if (s->reg[I_(UBRDIV)] == 0) {
 350         return;
 351     }
 352
 353     if (s->reg[I_(ULCON)] & 0x20) {
 354         if (s->reg[I_(ULCON)] & 0x28) {
 355             parity = 'E';
 356         } else {
 357             parity = 'O';
 358         }
 359     } else {
 360         parity = 'N';
 361     }
 362
 363     if (s->reg[I_(ULCON)] & 0x4) {
 364         stop_bits = 2;
 365     } else {
 366         stop_bits = 1;
 367     }
 368
 369     data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
 370
 371     uclk_rate = 24000000;
 372
 373     speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
 374             (s->reg[I_(UFRACVAL)] & 0x7) + 16);
 375
 376     ssp.speed     = speed;
 377     ssp.parity    = parity;
 378     ssp.data_bits = data_bits;
 379     ssp.stop_bits = stop_bits;
 380
 381     s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed;
 382
 383     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 384
 385     trace_exynos_uart_update_params(
 386                 s->channel, speed, parity, data_bits, stop_bits, s->wordtime);
 387 }
 388
 389 static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s)
 390 {
 391     if (s->reg[I_(UCON)] & 0x80) {
 392         uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime;
 393
 394         timer_mod(s->fifo_timeout_timer,
 395                   qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
 396     } else {
 397         timer_del(s->fifo_timeout_timer);
 398     }
 399 }
 400
 401 static void exynos4210_uart_write(void *opaque, hwaddr offset,
 402                                uint64_t val, unsigned size)
 403 {
 404     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 405     uint8_t ch;
 406
 407     trace_exynos_uart_write(s->channel, offset,
 408                             exynos4210_uart_regname(offset), val);
 409
 410     switch (offset) {
 411     case ULCON:
 412     case UBRDIV:
 413     case UFRACVAL:
 414         s->reg[I_(offset)] = val;
 415         exynos4210_uart_update_parameters(s);
 416         break;
 417     case UFCON:
 418         s->reg[I_(UFCON)] = val;
 419         if (val & UFCON_Rx_FIFO_RESET) {
 420             fifo_reset(&s->rx);
 421             s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
 422             trace_exynos_uart_rx_fifo_reset(s->channel);
 423         }
 424         if (val & UFCON_Tx_FIFO_RESET) {
 425             fifo_reset(&s->tx);
 426             s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
 427             trace_exynos_uart_tx_fifo_reset(s->channel);
 428         }
 429         break;
 430
 431     case UTXH:
 432         if (qemu_chr_fe_backend_connected(&s->chr)) {
 433             s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
 434                     UTRSTAT_Tx_BUFFER_EMPTY);
 435             ch = (uint8_t)val;
 436             /* XXX this blocks entire thread. Rewrite to use
 437              * qemu_chr_fe_write and background I/O callbacks */
 438             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 439             trace_exynos_uart_tx(s->channel, ch);
 440             s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
 441                     UTRSTAT_Tx_BUFFER_EMPTY;
 442             s->reg[I_(UINTSP)]  |= UINTSP_TXD;
 443             exynos4210_uart_update_irq(s);
 444         }
 445         break;
 446
 447     case UINTP:
 448         s->reg[I_(UINTP)] &= ~val;
 449         s->reg[I_(UINTSP)] &= ~val;
 450         trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]);
 451         exynos4210_uart_update_irq(s);
 452         break;
 453     case UTRSTAT:
 454         if (val & UTRSTAT_Rx_TIMEOUT) {
 455             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT;
 456         }
 457         break;
 458     case UERSTAT:
 459     case UFSTAT:
 460     case UMSTAT:
 461     case URXH:
 462         trace_exynos_uart_ro_write(
 463                     s->channel, exynos4210_uart_regname(offset), offset);
 464         break;
 465     case UINTSP:
 466         s->reg[I_(UINTSP)]  &= ~val;
 467         break;
 468     case UINTM:
 469         s->reg[I_(UINTM)] = val;
 470         exynos4210_uart_update_irq(s);
 471         break;
 472     case UCON:
 473     case UMCON:
 474     default:
 475         s->reg[I_(offset)] = val;
 476         break;
 477     }
 478 }
 479
 480 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
 481                                   unsigned size)
 482 {
 483     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 484     uint32_t res;
 485
 486     switch (offset) {
 487     case UERSTAT: /* Read Only */
 488         res = s->reg[I_(UERSTAT)];
 489         s->reg[I_(UERSTAT)] = 0;
 490         trace_exynos_uart_read(s->channel, offset,
 491                                exynos4210_uart_regname(offset), res);
 492         return res;
 493     case UFSTAT: /* Read Only */
 494         s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
 495         if (fifo_empty_elements_number(&s->rx) == 0) {
 496             s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
 497             s->reg[I_(UFSTAT)] &= ~0xff;
 498         }
 499         trace_exynos_uart_read(s->channel, offset,
 500                                exynos4210_uart_regname(offset),
 501                                s->reg[I_(UFSTAT)]);
 502         return s->reg[I_(UFSTAT)];
 503     case URXH:
 504         if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 505             if (fifo_elements_number(&s->rx)) {
 506                 res = fifo_retrieve(&s->rx);
 507                 trace_exynos_uart_rx(s->channel, res);
 508                 if (!fifo_elements_number(&s->rx)) {
 509                     s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
 510                 } else {
 511                     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 512                 }
 513             } else {
 514                 trace_exynos_uart_rx_error(s->channel);
 515                 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
 516                 exynos4210_uart_update_irq(s);
 517                 res = 0;
 518             }
 519         } else {
 520             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
 521             res = s->reg[I_(URXH)];
 522         }
 523         exynos4210_uart_update_dmabusy(s);
 524         trace_exynos_uart_read(s->channel, offset,
 525                                exynos4210_uart_regname(offset), res);
 526         return res;
 527     case UTXH:
 528         trace_exynos_uart_wo_read(s->channel, exynos4210_uart_regname(offset),
 529                                   offset);
 530         break;
 531     default:
 532         trace_exynos_uart_read(s->channel, offset,
 533                                exynos4210_uart_regname(offset),
 534                                s->reg[I_(offset)]);
 535         return s->reg[I_(offset)];
 536     }
 537
 538     trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset),
 539                            0);
 540     return 0;
 541 }
 542
 543 static const MemoryRegionOps exynos4210_uart_ops = {
 544     .read = exynos4210_uart_read,
 545     .write = exynos4210_uart_write,
 546     .endianness = DEVICE_NATIVE_ENDIAN,
 547     .valid = {
 548         .max_access_size = 4,
 549         .unaligned = false
 550     },
 551 };
 552
 553 static int exynos4210_uart_can_receive(void *opaque)
 554 {
 555     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 556
 557     return fifo_empty_elements_number(&s->rx);
 558 }
 559
 560 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
 561 {
 562     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 563     int i;
 564
 565     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 566         if (fifo_empty_elements_number(&s->rx) < size) {
 567             size = fifo_empty_elements_number(&s->rx);
 568             s->reg[I_(UINTSP)] |= UINTSP_ERROR;
 569         }
 570         for (i = 0; i < size; i++) {
 571             fifo_store(&s->rx, buf[i]);
 572         }
 573         exynos4210_uart_rx_timeout_set(s);
 574     } else {
 575         s->reg[I_(URXH)] = buf[0];
 576     }
 577     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 578
 579     exynos4210_uart_update_irq(s);
 580 }
 581
 582
 583 static void exynos4210_uart_event(void *opaque, QEMUChrEvent event)
 584 {
 585     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 586
 587     if (event == CHR_EVENT_BREAK) {
 588         /* When the RxDn is held in logic 0, then a null byte is pushed into the
 589          * fifo */
 590         fifo_store(&s->rx, '\0');
 591         s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
 592         exynos4210_uart_update_irq(s);
 593     }
 594 }
 595
 596
 597 static void exynos4210_uart_reset(DeviceState *dev)
 598 {
 599     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 600     int i;
 601
 602     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
 603         s->reg[I_(exynos4210_uart_regs[i].offset)] =
 604                 exynos4210_uart_regs[i].reset_value;
 605     }
 606
 607     fifo_reset(&s->rx);
 608     fifo_reset(&s->tx);
 609
 610     trace_exynos_uart_rxsize(s->channel, s->rx.size);
 611 }
 612
 613 static int exynos4210_uart_post_load(void *opaque, int version_id)
 614 {
 615     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 616
 617     exynos4210_uart_update_parameters(s);
 618     exynos4210_uart_rx_timeout_set(s);
 619
 620     return 0;
 621 }
 622
 623 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
 624     .name = "exynos4210.uart.fifo",
 625     .version_id = 1,
 626     .minimum_version_id = 1,
 627     .post_load = exynos4210_uart_post_load,
 628     .fields = (VMStateField[]) {
 629         VMSTATE_UINT32(sp, Exynos4210UartFIFO),
 630         VMSTATE_UINT32(rp, Exynos4210UartFIFO),
 631         VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size),
 632         VMSTATE_END_OF_LIST()
 633     }
 634 };
 635
 636 static const VMStateDescription vmstate_exynos4210_uart = {
 637     .name = "exynos4210.uart",
 638     .version_id = 1,
 639     .minimum_version_id = 1,
 640     .fields = (VMStateField[]) {
 641         VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
 642                        vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
 643         VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
 644                              EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
 645         VMSTATE_END_OF_LIST()
 646     }
 647 };
 648
 649 DeviceState *exynos4210_uart_create(hwaddr addr,
 650                                     int fifo_size,
 651                                     int channel,
 652                                     Chardev *chr,
 653                                     qemu_irq irq)
 654 {
 655     DeviceState  *dev;
 656     SysBusDevice *bus;
 657
 658     dev = qdev_new(TYPE_EXYNOS4210_UART);
 659
 660     qdev_prop_set_chr(dev, "chardev", chr);
 661     qdev_prop_set_uint32(dev, "channel", channel);
 662     qdev_prop_set_uint32(dev, "rx-size", fifo_size);
 663     qdev_prop_set_uint32(dev, "tx-size", fifo_size);
 664
 665     bus = SYS_BUS_DEVICE(dev);
 666     sysbus_realize_and_unref(bus, &error_fatal);
 667     if (addr != (hwaddr)-1) {
 668         sysbus_mmio_map(bus, 0, addr);
 669     }
 670     sysbus_connect_irq(bus, 0, irq);
 671
 672     return dev;
 673 }
 674
 675 static void exynos4210_uart_init(Object *obj)
 676 {
 677     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 678     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 679
 680     s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600;
 681
 682     /* memory mapping */
 683     memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,
 684                           "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
 685     sysbus_init_mmio(dev, &s->iomem);
 686
 687     sysbus_init_irq(dev, &s->irq);
 688     sysbus_init_irq(dev, &s->dmairq);
 689 }
 690
 691 static void exynos4210_uart_realize(DeviceState *dev, Error **errp)
 692 {
 693     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 694
 695     s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 696                                          exynos4210_uart_timeout_int, s);
 697
 698     qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
 699                              exynos4210_uart_receive, exynos4210_uart_event,
 700                              NULL, s, NULL, true);
 701 }
 702
 703 static Property exynos4210_uart_properties[] = {
 704     DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
 705     DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
 706     DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
 707     DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
 708     DEFINE_PROP_END_OF_LIST(),
 709 };
 710
 711 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
 712 {
 713     DeviceClass *dc = DEVICE_CLASS(klass);
 714
 715     dc->realize = exynos4210_uart_realize;
 716     dc->reset = exynos4210_uart_reset;
 717     device_class_set_props(dc, exynos4210_uart_properties);
 718     dc->vmsd = &vmstate_exynos4210_uart;
 719 }
 720
 721 static const TypeInfo exynos4210_uart_info = {
 722     .name          = TYPE_EXYNOS4210_UART,
 723     .parent        = TYPE_SYS_BUS_DEVICE,
 724     .instance_size = sizeof(Exynos4210UartState),
 725     .instance_init = exynos4210_uart_init,
 726     .class_init    = exynos4210_uart_class_init,
 727 };
 728
 729 static void exynos4210_uart_register(void)
 730 {
 731     type_register_static(&exynos4210_uart_info);
 732 }
 733
 734 type_init(exynos4210_uart_register)