2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "qemu/osdep.h"
31 #include "qemu-common.h"
33 #include "hw/boards.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/sysbus.h"
37 #include "migration/vmstate.h"
38 #include "strongarm.h"
39 #include "qemu/error-report.h"
40 #include "hw/arm/boot.h"
41 #include "chardev/char-fe.h"
42 #include "chardev/char-serial.h"
43 #include "sysemu/sysemu.h"
44 #include "hw/ssi/ssi.h"
45 #include "qapi/error.h"
46 #include "qemu/cutils.h"
48 #include "qom/object.h"
54 - Implement cp15, c14 ?
55 - Implement cp15, c15 !!! (idle used in L)
56 - Implement idle mode handling/DIM
57 - Implement sleep mode/Wake sources
58 - Implement reset control
59 - Implement memory control regs
61 - Maybe support MBGNT/MBREQ
66 - Enhance UART with modem signals
70 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
72 # define DPRINTF(format, ...) do { } while (0)
79 { 0x80010000, SA_PIC_UART1
},
80 { 0x80030000, SA_PIC_UART2
},
81 { 0x80050000, SA_PIC_UART3
},
85 /* Interrupt Controller */
87 #define TYPE_STRONGARM_PIC "strongarm_pic"
88 typedef struct StrongARMPICState StrongARMPICState
;
89 DECLARE_INSTANCE_CHECKER(StrongARMPICState
, STRONGARM_PIC
,
92 struct StrongARMPICState
{
93 SysBusDevice parent_obj
;
112 #define SA_PIC_SRCS 32
115 static void strongarm_pic_update(void *opaque
)
117 StrongARMPICState
*s
= opaque
;
119 /* FIXME: reflect DIM */
120 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
121 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
124 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
126 StrongARMPICState
*s
= opaque
;
129 s
->pending
|= 1 << irq
;
131 s
->pending
&= ~(1 << irq
);
134 strongarm_pic_update(s
);
137 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
140 StrongARMPICState
*s
= opaque
;
144 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
150 return s
->int_idle
== 0;
152 return s
->pending
& s
->is_fiq
& s
->enabled
;
156 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
162 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
163 uint64_t value
, unsigned size
)
165 StrongARMPICState
*s
= opaque
;
175 s
->int_idle
= (value
& 1) ? 0 : ~0;
178 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
182 strongarm_pic_update(s
);
185 static const MemoryRegionOps strongarm_pic_ops
= {
186 .read
= strongarm_pic_mem_read
,
187 .write
= strongarm_pic_mem_write
,
188 .endianness
= DEVICE_NATIVE_ENDIAN
,
191 static void strongarm_pic_initfn(Object
*obj
)
193 DeviceState
*dev
= DEVICE(obj
);
194 StrongARMPICState
*s
= STRONGARM_PIC(obj
);
195 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
197 qdev_init_gpio_in(dev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
198 memory_region_init_io(&s
->iomem
, obj
, &strongarm_pic_ops
, s
,
200 sysbus_init_mmio(sbd
, &s
->iomem
);
201 sysbus_init_irq(sbd
, &s
->irq
);
202 sysbus_init_irq(sbd
, &s
->fiq
);
205 static int strongarm_pic_post_load(void *opaque
, int version_id
)
207 strongarm_pic_update(opaque
);
211 static VMStateDescription vmstate_strongarm_pic_regs
= {
212 .name
= "strongarm_pic",
214 .minimum_version_id
= 0,
215 .post_load
= strongarm_pic_post_load
,
216 .fields
= (VMStateField
[]) {
217 VMSTATE_UINT32(pending
, StrongARMPICState
),
218 VMSTATE_UINT32(enabled
, StrongARMPICState
),
219 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
220 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
221 VMSTATE_END_OF_LIST(),
225 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
227 DeviceClass
*dc
= DEVICE_CLASS(klass
);
229 dc
->desc
= "StrongARM PIC";
230 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
233 static const TypeInfo strongarm_pic_info
= {
234 .name
= TYPE_STRONGARM_PIC
,
235 .parent
= TYPE_SYS_BUS_DEVICE
,
236 .instance_size
= sizeof(StrongARMPICState
),
237 .instance_init
= strongarm_pic_initfn
,
238 .class_init
= strongarm_pic_class_init
,
241 /* Real-Time Clock */
242 #define RTAR 0x00 /* RTC Alarm register */
243 #define RCNR 0x04 /* RTC Counter register */
244 #define RTTR 0x08 /* RTC Timer Trim register */
245 #define RTSR 0x10 /* RTC Status register */
247 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
248 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
249 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
250 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
252 /* 16 LSB of RTTR are clockdiv for internal trim logic,
253 * trim delete isn't emulated, so
254 * f = 32 768 / (RTTR_trim + 1) */
256 #define TYPE_STRONGARM_RTC "strongarm-rtc"
257 typedef struct StrongARMRTCState StrongARMRTCState
;
258 DECLARE_INSTANCE_CHECKER(StrongARMRTCState
, STRONGARM_RTC
,
261 struct StrongARMRTCState
{
262 SysBusDevice parent_obj
;
270 QEMUTimer
*rtc_alarm
;
276 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
278 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
279 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
282 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
284 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
285 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
286 (1000 * ((s
->rttr
& 0xffff) + 1));
290 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
292 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
293 timer_mod(s
->rtc_hz
, s
->last_hz
+ 1000);
295 timer_del(s
->rtc_hz
);
298 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
299 timer_mod(s
->rtc_alarm
, s
->last_hz
+
300 (((s
->rtar
- s
->last_rcnr
) * 1000 *
301 ((s
->rttr
& 0xffff) + 1)) >> 15));
303 timer_del(s
->rtc_alarm
);
307 static inline void strongarm_rtc_alarm_tick(void *opaque
)
309 StrongARMRTCState
*s
= opaque
;
311 strongarm_rtc_timer_update(s
);
312 strongarm_rtc_int_update(s
);
315 static inline void strongarm_rtc_hz_tick(void *opaque
)
317 StrongARMRTCState
*s
= opaque
;
319 strongarm_rtc_timer_update(s
);
320 strongarm_rtc_int_update(s
);
323 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
326 StrongARMRTCState
*s
= opaque
;
336 return s
->last_rcnr
+
337 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
338 (1000 * ((s
->rttr
& 0xffff) + 1));
340 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
345 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
346 uint64_t value
, unsigned size
)
348 StrongARMRTCState
*s
= opaque
;
353 strongarm_rtc_hzupdate(s
);
355 strongarm_rtc_timer_update(s
);
360 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
361 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
363 if (s
->rtsr
!= old_rtsr
) {
364 strongarm_rtc_timer_update(s
);
367 strongarm_rtc_int_update(s
);
372 strongarm_rtc_timer_update(s
);
376 strongarm_rtc_hzupdate(s
);
377 s
->last_rcnr
= value
;
378 strongarm_rtc_timer_update(s
);
382 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
386 static const MemoryRegionOps strongarm_rtc_ops
= {
387 .read
= strongarm_rtc_read
,
388 .write
= strongarm_rtc_write
,
389 .endianness
= DEVICE_NATIVE_ENDIAN
,
392 static void strongarm_rtc_init(Object
*obj
)
394 StrongARMRTCState
*s
= STRONGARM_RTC(obj
);
395 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
401 qemu_get_timedate(&tm
, 0);
403 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
404 s
->last_hz
= qemu_clock_get_ms(rtc_clock
);
406 sysbus_init_irq(dev
, &s
->rtc_irq
);
407 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
409 memory_region_init_io(&s
->iomem
, obj
, &strongarm_rtc_ops
, s
,
411 sysbus_init_mmio(dev
, &s
->iomem
);
414 static void strongarm_rtc_realize(DeviceState
*dev
, Error
**errp
)
416 StrongARMRTCState
*s
= STRONGARM_RTC(dev
);
417 s
->rtc_alarm
= timer_new_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
418 s
->rtc_hz
= timer_new_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
421 static int strongarm_rtc_pre_save(void *opaque
)
423 StrongARMRTCState
*s
= opaque
;
425 strongarm_rtc_hzupdate(s
);
430 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
432 StrongARMRTCState
*s
= opaque
;
434 strongarm_rtc_timer_update(s
);
435 strongarm_rtc_int_update(s
);
440 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
441 .name
= "strongarm-rtc",
443 .minimum_version_id
= 0,
444 .pre_save
= strongarm_rtc_pre_save
,
445 .post_load
= strongarm_rtc_post_load
,
446 .fields
= (VMStateField
[]) {
447 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
448 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
449 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
450 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
451 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
452 VMSTATE_END_OF_LIST(),
456 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
458 DeviceClass
*dc
= DEVICE_CLASS(klass
);
460 dc
->desc
= "StrongARM RTC Controller";
461 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
462 dc
->realize
= strongarm_rtc_realize
;
465 static const TypeInfo strongarm_rtc_sysbus_info
= {
466 .name
= TYPE_STRONGARM_RTC
,
467 .parent
= TYPE_SYS_BUS_DEVICE
,
468 .instance_size
= sizeof(StrongARMRTCState
),
469 .instance_init
= strongarm_rtc_init
,
470 .class_init
= strongarm_rtc_sysbus_class_init
,
483 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
484 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
485 DECLARE_INSTANCE_CHECKER(StrongARMGPIOInfo
, STRONGARM_GPIO
,
488 struct StrongARMGPIOInfo
{
491 qemu_irq handler
[28];
507 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
510 for (i
= 0; i
< 11; i
++) {
511 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
514 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
517 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
519 StrongARMGPIOInfo
*s
= opaque
;
525 s
->status
|= s
->rising
& mask
&
526 ~s
->ilevel
& ~s
->dir
;
529 s
->status
|= s
->falling
& mask
&
534 if (s
->status
& mask
) {
535 strongarm_gpio_irq_update(s
);
539 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
541 uint32_t level
, diff
;
544 level
= s
->olevel
& s
->dir
;
546 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
548 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
551 s
->prev_level
= level
;
554 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
557 StrongARMGPIOInfo
*s
= opaque
;
560 case GPDR
: /* GPIO Pin-Direction registers */
563 case GPSR
: /* GPIO Pin-Output Set registers */
564 qemu_log_mask(LOG_GUEST_ERROR
,
565 "strongarm GPIO: read from write only register GPSR\n");
568 case GPCR
: /* GPIO Pin-Output Clear registers */
569 qemu_log_mask(LOG_GUEST_ERROR
,
570 "strongarm GPIO: read from write only register GPCR\n");
573 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
576 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
579 case GAFR
: /* GPIO Alternate Function registers */
582 case GPLR
: /* GPIO Pin-Level registers */
583 return (s
->olevel
& s
->dir
) |
584 (s
->ilevel
& ~s
->dir
);
586 case GEDR
: /* GPIO Edge Detect Status registers */
590 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
596 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
597 uint64_t value
, unsigned size
)
599 StrongARMGPIOInfo
*s
= opaque
;
602 case GPDR
: /* GPIO Pin-Direction registers */
603 s
->dir
= value
& 0x0fffffff;
604 strongarm_gpio_handler_update(s
);
607 case GPSR
: /* GPIO Pin-Output Set registers */
608 s
->olevel
|= value
& 0x0fffffff;
609 strongarm_gpio_handler_update(s
);
612 case GPCR
: /* GPIO Pin-Output Clear registers */
614 strongarm_gpio_handler_update(s
);
617 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
621 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
625 case GAFR
: /* GPIO Alternate Function registers */
629 case GEDR
: /* GPIO Edge Detect Status registers */
631 strongarm_gpio_irq_update(s
);
635 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
639 static const MemoryRegionOps strongarm_gpio_ops
= {
640 .read
= strongarm_gpio_read
,
641 .write
= strongarm_gpio_write
,
642 .endianness
= DEVICE_NATIVE_ENDIAN
,
645 static DeviceState
*strongarm_gpio_init(hwaddr base
,
651 dev
= qdev_new(TYPE_STRONGARM_GPIO
);
652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
654 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
655 for (i
= 0; i
< 12; i
++)
656 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
657 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
662 static void strongarm_gpio_initfn(Object
*obj
)
664 DeviceState
*dev
= DEVICE(obj
);
665 StrongARMGPIOInfo
*s
= STRONGARM_GPIO(obj
);
666 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
669 qdev_init_gpio_in(dev
, strongarm_gpio_set
, 28);
670 qdev_init_gpio_out(dev
, s
->handler
, 28);
672 memory_region_init_io(&s
->iomem
, obj
, &strongarm_gpio_ops
, s
,
675 sysbus_init_mmio(sbd
, &s
->iomem
);
676 for (i
= 0; i
< 11; i
++) {
677 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
679 sysbus_init_irq(sbd
, &s
->irqX
);
682 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
683 .name
= "strongarm-gpio",
685 .minimum_version_id
= 0,
686 .fields
= (VMStateField
[]) {
687 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
688 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
689 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
690 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
691 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
692 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
693 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
694 VMSTATE_UINT32(prev_level
, StrongARMGPIOInfo
),
695 VMSTATE_END_OF_LIST(),
699 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
701 DeviceClass
*dc
= DEVICE_CLASS(klass
);
703 dc
->desc
= "StrongARM GPIO controller";
704 dc
->vmsd
= &vmstate_strongarm_gpio_regs
;
707 static const TypeInfo strongarm_gpio_info
= {
708 .name
= TYPE_STRONGARM_GPIO
,
709 .parent
= TYPE_SYS_BUS_DEVICE
,
710 .instance_size
= sizeof(StrongARMGPIOInfo
),
711 .instance_init
= strongarm_gpio_initfn
,
712 .class_init
= strongarm_gpio_class_init
,
715 /* Peripheral Pin Controller */
722 #define TYPE_STRONGARM_PPC "strongarm-ppc"
723 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
724 DECLARE_INSTANCE_CHECKER(StrongARMPPCInfo
, STRONGARM_PPC
,
727 struct StrongARMPPCInfo
{
728 SysBusDevice parent_obj
;
731 qemu_irq handler
[28];
743 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
745 StrongARMPPCInfo
*s
= opaque
;
748 s
->ilevel
|= 1 << line
;
750 s
->ilevel
&= ~(1 << line
);
754 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
756 uint32_t level
, diff
;
759 level
= s
->olevel
& s
->dir
;
761 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
763 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
766 s
->prev_level
= level
;
769 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
772 StrongARMPPCInfo
*s
= opaque
;
775 case PPDR
: /* PPC Pin Direction registers */
776 return s
->dir
| ~0x3fffff;
778 case PPSR
: /* PPC Pin State registers */
779 return (s
->olevel
& s
->dir
) |
780 (s
->ilevel
& ~s
->dir
) |
784 return s
->ppar
| ~0x41000;
790 return s
->ppfr
| ~0x7f001;
793 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
799 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
800 uint64_t value
, unsigned size
)
802 StrongARMPPCInfo
*s
= opaque
;
805 case PPDR
: /* PPC Pin Direction registers */
806 s
->dir
= value
& 0x3fffff;
807 strongarm_ppc_handler_update(s
);
810 case PPSR
: /* PPC Pin State registers */
811 s
->olevel
= value
& s
->dir
& 0x3fffff;
812 strongarm_ppc_handler_update(s
);
816 s
->ppar
= value
& 0x41000;
820 s
->psdr
= value
& 0x3fffff;
824 s
->ppfr
= value
& 0x7f001;
828 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
832 static const MemoryRegionOps strongarm_ppc_ops
= {
833 .read
= strongarm_ppc_read
,
834 .write
= strongarm_ppc_write
,
835 .endianness
= DEVICE_NATIVE_ENDIAN
,
838 static void strongarm_ppc_init(Object
*obj
)
840 DeviceState
*dev
= DEVICE(obj
);
841 StrongARMPPCInfo
*s
= STRONGARM_PPC(obj
);
842 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
844 qdev_init_gpio_in(dev
, strongarm_ppc_set
, 22);
845 qdev_init_gpio_out(dev
, s
->handler
, 22);
847 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ppc_ops
, s
,
850 sysbus_init_mmio(sbd
, &s
->iomem
);
853 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
854 .name
= "strongarm-ppc",
856 .minimum_version_id
= 0,
857 .fields
= (VMStateField
[]) {
858 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
859 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
860 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
861 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
862 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
863 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
864 VMSTATE_UINT32(prev_level
, StrongARMPPCInfo
),
865 VMSTATE_END_OF_LIST(),
869 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
871 DeviceClass
*dc
= DEVICE_CLASS(klass
);
873 dc
->desc
= "StrongARM PPC controller";
874 dc
->vmsd
= &vmstate_strongarm_ppc_regs
;
877 static const TypeInfo strongarm_ppc_info
= {
878 .name
= TYPE_STRONGARM_PPC
,
879 .parent
= TYPE_SYS_BUS_DEVICE
,
880 .instance_size
= sizeof(StrongARMPPCInfo
),
881 .instance_init
= strongarm_ppc_init
,
882 .class_init
= strongarm_ppc_class_init
,
894 #define UTCR0_PE (1 << 0) /* Parity enable */
895 #define UTCR0_OES (1 << 1) /* Even parity */
896 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
897 #define UTCR0_DSS (1 << 3) /* 8-bit data */
899 #define UTCR3_RXE (1 << 0) /* Rx enable */
900 #define UTCR3_TXE (1 << 1) /* Tx enable */
901 #define UTCR3_BRK (1 << 2) /* Force Break */
902 #define UTCR3_RIE (1 << 3) /* Rx int enable */
903 #define UTCR3_TIE (1 << 4) /* Tx int enable */
904 #define UTCR3_LBM (1 << 5) /* Loopback */
906 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
907 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
908 #define UTSR0_RID (1 << 2) /* Receiver Idle */
909 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
910 #define UTSR0_REB (1 << 4) /* Receiver end break */
911 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
913 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
914 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
915 #define UTSR1_PRE (1 << 3) /* Parity error */
916 #define UTSR1_FRE (1 << 4) /* Frame error */
917 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
919 #define RX_FIFO_PRE (1 << 8)
920 #define RX_FIFO_FRE (1 << 9)
921 #define RX_FIFO_ROR (1 << 10)
923 #define TYPE_STRONGARM_UART "strongarm-uart"
924 typedef struct StrongARMUARTState StrongARMUARTState
;
925 DECLARE_INSTANCE_CHECKER(StrongARMUARTState
, STRONGARM_UART
,
928 struct StrongARMUARTState
{
929 SysBusDevice parent_obj
;
944 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
948 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
950 QEMUTimer
*rx_timeout_timer
;
954 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
958 if (s
->tx_len
!= 8) {
962 if (s
->rx_len
!= 0) {
963 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
966 if (ent
& RX_FIFO_PRE
) {
967 s
->utsr1
|= UTSR1_PRE
;
969 if (ent
& RX_FIFO_FRE
) {
970 s
->utsr1
|= UTSR1_FRE
;
972 if (ent
& RX_FIFO_ROR
) {
973 s
->utsr1
|= UTSR1_ROR
;
980 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
982 uint16_t utsr0
= s
->utsr0
&
983 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
986 if ((s
->utcr3
& UTCR3_TXE
) &&
987 (s
->utcr3
& UTCR3_TIE
) &&
992 if ((s
->utcr3
& UTCR3_RXE
) &&
993 (s
->utcr3
& UTCR3_RIE
) &&
998 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
999 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
1005 qemu_set_irq(s
->irq
, utsr0
);
1008 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
1010 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
1011 QEMUSerialSetParams ssp
;
1015 if (s
->utcr0
& UTCR0_PE
) {
1018 if (s
->utcr0
& UTCR0_OES
) {
1026 if (s
->utcr0
& UTCR0_SBS
) {
1032 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
1033 frame_size
+= data_bits
+ stop_bits
;
1034 speed
= 3686400 / 16 / (s
->brd
+ 1);
1036 ssp
.parity
= parity
;
1037 ssp
.data_bits
= data_bits
;
1038 ssp
.stop_bits
= stop_bits
;
1039 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
1040 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1042 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1043 speed
, parity
, data_bits
, stop_bits
);
1046 static void strongarm_uart_rx_to(void *opaque
)
1048 StrongARMUARTState
*s
= opaque
;
1051 s
->utsr0
|= UTSR0_RID
;
1052 strongarm_uart_update_int_status(s
);
1056 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1058 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1063 if (s
->wait_break_end
) {
1064 s
->utsr0
|= UTSR0_REB
;
1065 s
->wait_break_end
= false;
1068 if (s
->rx_len
< 12) {
1069 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1072 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1075 static int strongarm_uart_can_receive(void *opaque
)
1077 StrongARMUARTState
*s
= opaque
;
1079 if (s
->rx_len
== 12) {
1082 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1083 if (s
->rx_len
< 8) {
1084 return 8 - s
->rx_len
;
1089 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1091 StrongARMUARTState
*s
= opaque
;
1094 for (i
= 0; i
< size
; i
++) {
1095 strongarm_uart_rx_push(s
, buf
[i
]);
1098 /* call the timeout receive callback in 3 char transmit time */
1099 timer_mod(s
->rx_timeout_timer
,
1100 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1102 strongarm_uart_update_status(s
);
1103 strongarm_uart_update_int_status(s
);
1106 static void strongarm_uart_event(void *opaque
, QEMUChrEvent event
)
1108 StrongARMUARTState
*s
= opaque
;
1109 if (event
== CHR_EVENT_BREAK
) {
1110 s
->utsr0
|= UTSR0_RBB
;
1111 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1112 s
->wait_break_end
= true;
1113 strongarm_uart_update_status(s
);
1114 strongarm_uart_update_int_status(s
);
1118 static void strongarm_uart_tx(void *opaque
)
1120 StrongARMUARTState
*s
= opaque
;
1121 uint64_t new_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1123 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1124 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1125 } else if (qemu_chr_fe_backend_connected(&s
->chr
)) {
1126 /* XXX this blocks entire thread. Rewrite to use
1127 * qemu_chr_fe_write and background I/O callbacks */
1128 qemu_chr_fe_write_all(&s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1131 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1134 timer_mod(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1136 strongarm_uart_update_status(s
);
1137 strongarm_uart_update_int_status(s
);
1140 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1143 StrongARMUARTState
*s
= opaque
;
1154 return s
->brd
& 0xff;
1160 if (s
->rx_len
!= 0) {
1161 ret
= s
->rx_fifo
[s
->rx_start
];
1162 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1164 strongarm_uart_update_status(s
);
1165 strongarm_uart_update_int_status(s
);
1177 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1182 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1183 uint64_t value
, unsigned size
)
1185 StrongARMUARTState
*s
= opaque
;
1189 s
->utcr0
= value
& 0x7f;
1190 strongarm_uart_update_parameters(s
);
1194 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1195 strongarm_uart_update_parameters(s
);
1199 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1200 strongarm_uart_update_parameters(s
);
1204 s
->utcr3
= value
& 0x3f;
1205 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1208 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1211 strongarm_uart_update_status(s
);
1212 strongarm_uart_update_int_status(s
);
1216 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1217 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1219 strongarm_uart_update_status(s
);
1220 strongarm_uart_update_int_status(s
);
1221 if (s
->tx_len
== 1) {
1222 strongarm_uart_tx(s
);
1228 s
->utsr0
= s
->utsr0
& ~(value
&
1229 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1230 strongarm_uart_update_int_status(s
);
1234 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1238 static const MemoryRegionOps strongarm_uart_ops
= {
1239 .read
= strongarm_uart_read
,
1240 .write
= strongarm_uart_write
,
1241 .endianness
= DEVICE_NATIVE_ENDIAN
,
1244 static void strongarm_uart_init(Object
*obj
)
1246 StrongARMUARTState
*s
= STRONGARM_UART(obj
);
1247 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1249 memory_region_init_io(&s
->iomem
, obj
, &strongarm_uart_ops
, s
,
1251 sysbus_init_mmio(dev
, &s
->iomem
);
1252 sysbus_init_irq(dev
, &s
->irq
);
1255 static void strongarm_uart_realize(DeviceState
*dev
, Error
**errp
)
1257 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1259 s
->rx_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
1260 strongarm_uart_rx_to
,
1262 s
->tx_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_tx
, s
);
1263 qemu_chr_fe_set_handlers(&s
->chr
,
1264 strongarm_uart_can_receive
,
1265 strongarm_uart_receive
,
1266 strongarm_uart_event
,
1267 NULL
, s
, NULL
, true);
1270 static void strongarm_uart_reset(DeviceState
*dev
)
1272 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1274 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1275 s
->brd
= 23; /* 9600 */
1276 /* enable send & recv - this actually violates spec */
1277 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1279 s
->rx_len
= s
->tx_len
= 0;
1281 strongarm_uart_update_parameters(s
);
1282 strongarm_uart_update_status(s
);
1283 strongarm_uart_update_int_status(s
);
1286 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1288 StrongARMUARTState
*s
= opaque
;
1290 strongarm_uart_update_parameters(s
);
1291 strongarm_uart_update_status(s
);
1292 strongarm_uart_update_int_status(s
);
1294 /* tx and restart timer */
1296 strongarm_uart_tx(s
);
1299 /* restart rx timeout timer */
1301 timer_mod(s
->rx_timeout_timer
,
1302 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1308 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1309 .name
= "strongarm-uart",
1311 .minimum_version_id
= 0,
1312 .post_load
= strongarm_uart_post_load
,
1313 .fields
= (VMStateField
[]) {
1314 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1315 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1316 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1317 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1318 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1319 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1320 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1321 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1322 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1323 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1324 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1325 VMSTATE_END_OF_LIST(),
1329 static Property strongarm_uart_properties
[] = {
1330 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1331 DEFINE_PROP_END_OF_LIST(),
1334 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1336 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1338 dc
->desc
= "StrongARM UART controller";
1339 dc
->reset
= strongarm_uart_reset
;
1340 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1341 device_class_set_props(dc
, strongarm_uart_properties
);
1342 dc
->realize
= strongarm_uart_realize
;
1345 static const TypeInfo strongarm_uart_info
= {
1346 .name
= TYPE_STRONGARM_UART
,
1347 .parent
= TYPE_SYS_BUS_DEVICE
,
1348 .instance_size
= sizeof(StrongARMUARTState
),
1349 .instance_init
= strongarm_uart_init
,
1350 .class_init
= strongarm_uart_class_init
,
1353 /* Synchronous Serial Ports */
1355 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1356 typedef struct StrongARMSSPState StrongARMSSPState
;
1357 DECLARE_INSTANCE_CHECKER(StrongARMSSPState
, STRONGARM_SSP
,
1360 struct StrongARMSSPState
{
1361 SysBusDevice parent_obj
;
1370 uint16_t rx_fifo
[8];
1375 #define SSCR0 0x60 /* SSP Control register 0 */
1376 #define SSCR1 0x64 /* SSP Control register 1 */
1377 #define SSDR 0x6c /* SSP Data register */
1378 #define SSSR 0x74 /* SSP Status register */
1380 /* Bitfields for above registers */
1381 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1382 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1383 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1384 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1385 #define SSCR0_SSE (1 << 7)
1386 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1387 #define SSCR1_RIE (1 << 0)
1388 #define SSCR1_TIE (1 << 1)
1389 #define SSCR1_LBM (1 << 2)
1390 #define SSSR_TNF (1 << 2)
1391 #define SSSR_RNE (1 << 3)
1392 #define SSSR_TFS (1 << 5)
1393 #define SSSR_RFS (1 << 6)
1394 #define SSSR_ROR (1 << 7)
1395 #define SSSR_RW 0x0080
1397 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1401 level
|= (s
->sssr
& SSSR_ROR
);
1402 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1403 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1404 qemu_set_irq(s
->irq
, level
);
1407 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1409 s
->sssr
&= ~SSSR_TFS
;
1410 s
->sssr
&= ~SSSR_TNF
;
1411 if (s
->sscr
[0] & SSCR0_SSE
) {
1412 if (s
->rx_level
>= 4) {
1413 s
->sssr
|= SSSR_RFS
;
1415 s
->sssr
&= ~SSSR_RFS
;
1418 s
->sssr
|= SSSR_RNE
;
1420 s
->sssr
&= ~SSSR_RNE
;
1422 /* TX FIFO is never filled, so it is always in underrun
1423 condition if SSP is enabled */
1424 s
->sssr
|= SSSR_TFS
;
1425 s
->sssr
|= SSSR_TNF
;
1428 strongarm_ssp_int_update(s
);
1431 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1434 StrongARMSSPState
*s
= opaque
;
1445 if (~s
->sscr
[0] & SSCR0_SSE
) {
1448 if (s
->rx_level
< 1) {
1449 printf("%s: SSP Rx Underrun\n", __func__
);
1453 retval
= s
->rx_fifo
[s
->rx_start
++];
1455 strongarm_ssp_fifo_update(s
);
1458 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1464 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1465 uint64_t value
, unsigned size
)
1467 StrongARMSSPState
*s
= opaque
;
1471 s
->sscr
[0] = value
& 0xffbf;
1472 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1473 printf("%s: Wrong data size: %i bits\n", __func__
,
1474 (int)SSCR0_DSS(value
));
1476 if (!(value
& SSCR0_SSE
)) {
1480 strongarm_ssp_fifo_update(s
);
1484 s
->sscr
[1] = value
& 0x2f;
1485 if (value
& SSCR1_LBM
) {
1486 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1488 strongarm_ssp_fifo_update(s
);
1492 s
->sssr
&= ~(value
& SSSR_RW
);
1493 strongarm_ssp_int_update(s
);
1497 if (SSCR0_UWIRE(s
->sscr
[0])) {
1500 /* Note how 32bits overflow does no harm here */
1501 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1503 /* Data goes from here to the Tx FIFO and is shifted out from
1504 * there directly to the slave, no need to buffer it.
1506 if (s
->sscr
[0] & SSCR0_SSE
) {
1508 if (s
->sscr
[1] & SSCR1_LBM
) {
1511 readval
= ssi_transfer(s
->bus
, value
);
1514 if (s
->rx_level
< 0x08) {
1515 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1517 s
->sssr
|= SSSR_ROR
;
1520 strongarm_ssp_fifo_update(s
);
1524 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1529 static const MemoryRegionOps strongarm_ssp_ops
= {
1530 .read
= strongarm_ssp_read
,
1531 .write
= strongarm_ssp_write
,
1532 .endianness
= DEVICE_NATIVE_ENDIAN
,
1535 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1537 StrongARMSSPState
*s
= opaque
;
1539 strongarm_ssp_fifo_update(s
);
1544 static void strongarm_ssp_init(Object
*obj
)
1546 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1547 DeviceState
*dev
= DEVICE(sbd
);
1548 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1550 sysbus_init_irq(sbd
, &s
->irq
);
1552 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ssp_ops
, s
,
1554 sysbus_init_mmio(sbd
, &s
->iomem
);
1556 s
->bus
= ssi_create_bus(dev
, "ssi");
1559 static void strongarm_ssp_reset(DeviceState
*dev
)
1561 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1563 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1568 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1569 .name
= "strongarm-ssp",
1571 .minimum_version_id
= 0,
1572 .post_load
= strongarm_ssp_post_load
,
1573 .fields
= (VMStateField
[]) {
1574 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1575 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1576 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1577 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1578 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1579 VMSTATE_END_OF_LIST(),
1583 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1585 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1587 dc
->desc
= "StrongARM SSP controller";
1588 dc
->reset
= strongarm_ssp_reset
;
1589 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1592 static const TypeInfo strongarm_ssp_info
= {
1593 .name
= TYPE_STRONGARM_SSP
,
1594 .parent
= TYPE_SYS_BUS_DEVICE
,
1595 .instance_size
= sizeof(StrongARMSSPState
),
1596 .instance_init
= strongarm_ssp_init
,
1597 .class_init
= strongarm_ssp_class_init
,
1600 /* Main CPU functions */
1601 StrongARMState
*sa1110_init(const char *cpu_type
)
1606 s
= g_new0(StrongARMState
, 1);
1608 if (strncmp(cpu_type
, "sa1110", 6)) {
1609 error_report("Machine requires a SA1110 processor.");
1613 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
1615 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1616 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
),
1617 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
),
1620 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1621 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1622 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1623 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1624 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1627 sysbus_create_simple(TYPE_STRONGARM_RTC
, 0x90010000,
1628 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1630 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1632 s
->ppc
= sysbus_create_varargs(TYPE_STRONGARM_PPC
, 0x90060000, NULL
);
1634 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1635 DeviceState
*dev
= qdev_new(TYPE_STRONGARM_UART
);
1636 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
1637 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1638 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1639 sa_serial
[i
].io_base
);
1640 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1641 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1644 s
->ssp
= sysbus_create_varargs(TYPE_STRONGARM_SSP
, 0x80070000,
1645 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1646 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1651 static void strongarm_register_types(void)
1653 type_register_static(&strongarm_pic_info
);
1654 type_register_static(&strongarm_rtc_sysbus_info
);
1655 type_register_static(&strongarm_gpio_info
);
1656 type_register_static(&strongarm_ppc_info
);
1657 type_register_static(&strongarm_uart_info
);
1658 type_register_static(&strongarm_ssp_info
);
1661 type_init(strongarm_register_types
)