2 * Intel XScale PXA255/270 GPIO controller emulation.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
13 #include "hw/qdev-properties.h"
14 #include "hw/sysbus.h"
15 #include "migration/vmstate.h"
16 #include "hw/arm/pxa.h"
17 #include "qapi/error.h"
19 #include "qemu/module.h"
20 #include "qom/object.h"
22 #define PXA2XX_GPIO_BANKS 4
24 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
25 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo
;
26 DECLARE_INSTANCE_CHECKER(PXA2xxGPIOInfo
, PXA2XX_GPIO
,
29 struct PXA2xxGPIOInfo
{
31 SysBusDevice parent_obj
;
35 qemu_irq irq0
, irq1
, irqX
;
40 /* XXX: GNU C vectors are more suitable */
41 uint32_t ilevel
[PXA2XX_GPIO_BANKS
];
42 uint32_t olevel
[PXA2XX_GPIO_BANKS
];
43 uint32_t dir
[PXA2XX_GPIO_BANKS
];
44 uint32_t rising
[PXA2XX_GPIO_BANKS
];
45 uint32_t falling
[PXA2XX_GPIO_BANKS
];
46 uint32_t status
[PXA2XX_GPIO_BANKS
];
47 uint32_t gafr
[PXA2XX_GPIO_BANKS
* 2];
49 uint32_t prev_level
[PXA2XX_GPIO_BANKS
];
50 qemu_irq handler
[PXA2XX_GPIO_BANKS
* 32];
68 } pxa2xx_gpio_regs
[0x200] = {
69 [0 ... 0x1ff] = { GPIO_NONE
, 0 },
70 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
71 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
73 PXA2XX_REG(GPLR
, 0x000, 0x004, 0x008, 0x100)
74 PXA2XX_REG(GPSR
, 0x018, 0x01c, 0x020, 0x118)
75 PXA2XX_REG(GPCR
, 0x024, 0x028, 0x02c, 0x124)
76 PXA2XX_REG(GPDR
, 0x00c, 0x010, 0x014, 0x10c)
77 PXA2XX_REG(GRER
, 0x030, 0x034, 0x038, 0x130)
78 PXA2XX_REG(GFER
, 0x03c, 0x040, 0x044, 0x13c)
79 PXA2XX_REG(GEDR
, 0x048, 0x04c, 0x050, 0x148)
80 PXA2XX_REG(GAFR_L
, 0x054, 0x05c, 0x064, 0x06c)
81 PXA2XX_REG(GAFR_U
, 0x058, 0x060, 0x068, 0x070)
84 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo
*s
)
86 if (s
->status
[0] & (1 << 0))
87 qemu_irq_raise(s
->irq0
);
89 qemu_irq_lower(s
->irq0
);
91 if (s
->status
[0] & (1 << 1))
92 qemu_irq_raise(s
->irq1
);
94 qemu_irq_lower(s
->irq1
);
96 if ((s
->status
[0] & ~3) | s
->status
[1] | s
->status
[2] | s
->status
[3])
97 qemu_irq_raise(s
->irqX
);
99 qemu_irq_lower(s
->irqX
);
102 /* Bitmap of pins used as standby and sleep wake-up sources. */
103 static const int pxa2xx_gpio_wake
[PXA2XX_GPIO_BANKS
] = {
104 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
107 static void pxa2xx_gpio_set(void *opaque
, int line
, int level
)
109 PXA2xxGPIOInfo
*s
= (PXA2xxGPIOInfo
*) opaque
;
110 CPUState
*cpu
= CPU(s
->cpu
);
114 if (line
>= s
->lines
) {
115 printf("%s: No GPIO pin %i\n", __func__
, line
);
120 mask
= 1U << (line
& 31);
123 s
->status
[bank
] |= s
->rising
[bank
] & mask
&
124 ~s
->ilevel
[bank
] & ~s
->dir
[bank
];
125 s
->ilevel
[bank
] |= mask
;
127 s
->status
[bank
] |= s
->falling
[bank
] & mask
&
128 s
->ilevel
[bank
] & ~s
->dir
[bank
];
129 s
->ilevel
[bank
] &= ~mask
;
132 if (s
->status
[bank
] & mask
)
133 pxa2xx_gpio_irq_update(s
);
136 if (cpu
->halted
&& (mask
& ~s
->dir
[bank
] & pxa2xx_gpio_wake
[bank
])) {
137 cpu_interrupt(cpu
, CPU_INTERRUPT_EXITTB
);
141 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo
*s
) {
142 uint32_t level
, diff
;
144 for (i
= 0; i
< PXA2XX_GPIO_BANKS
; i
++) {
145 level
= s
->olevel
[i
] & s
->dir
[i
];
147 for (diff
= s
->prev_level
[i
] ^ level
; diff
; diff
^= 1 << bit
) {
150 qemu_set_irq(s
->handler
[line
], (level
>> bit
) & 1);
153 s
->prev_level
[i
] = level
;
157 static uint64_t pxa2xx_gpio_read(void *opaque
, hwaddr offset
,
160 PXA2xxGPIOInfo
*s
= (PXA2xxGPIOInfo
*) opaque
;
166 bank
= pxa2xx_gpio_regs
[offset
].bank
;
167 switch (pxa2xx_gpio_regs
[offset
].reg
) {
168 case GPDR
: /* GPIO Pin-Direction registers */
171 case GPSR
: /* GPIO Pin-Output Set registers */
172 qemu_log_mask(LOG_GUEST_ERROR
,
173 "pxa2xx GPIO: read from write only register GPSR\n");
176 case GPCR
: /* GPIO Pin-Output Clear registers */
177 qemu_log_mask(LOG_GUEST_ERROR
,
178 "pxa2xx GPIO: read from write only register GPCR\n");
181 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
182 return s
->rising
[bank
];
184 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
185 return s
->falling
[bank
];
187 case GAFR_L
: /* GPIO Alternate Function registers */
188 return s
->gafr
[bank
* 2];
190 case GAFR_U
: /* GPIO Alternate Function registers */
191 return s
->gafr
[bank
* 2 + 1];
193 case GPLR
: /* GPIO Pin-Level registers */
194 ret
= (s
->olevel
[bank
] & s
->dir
[bank
]) |
195 (s
->ilevel
[bank
] & ~s
->dir
[bank
]);
196 qemu_irq_raise(s
->read_notify
);
199 case GEDR
: /* GPIO Edge Detect Status registers */
200 return s
->status
[bank
];
203 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%" HWADDR_PRIX
"\n",
210 static void pxa2xx_gpio_write(void *opaque
, hwaddr offset
,
211 uint64_t value
, unsigned size
)
213 PXA2xxGPIOInfo
*s
= (PXA2xxGPIOInfo
*) opaque
;
218 bank
= pxa2xx_gpio_regs
[offset
].bank
;
219 switch (pxa2xx_gpio_regs
[offset
].reg
) {
220 case GPDR
: /* GPIO Pin-Direction registers */
221 s
->dir
[bank
] = value
;
222 pxa2xx_gpio_handler_update(s
);
225 case GPSR
: /* GPIO Pin-Output Set registers */
226 s
->olevel
[bank
] |= value
;
227 pxa2xx_gpio_handler_update(s
);
230 case GPCR
: /* GPIO Pin-Output Clear registers */
231 s
->olevel
[bank
] &= ~value
;
232 pxa2xx_gpio_handler_update(s
);
235 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
236 s
->rising
[bank
] = value
;
239 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
240 s
->falling
[bank
] = value
;
243 case GAFR_L
: /* GPIO Alternate Function registers */
244 s
->gafr
[bank
* 2] = value
;
247 case GAFR_U
: /* GPIO Alternate Function registers */
248 s
->gafr
[bank
* 2 + 1] = value
;
251 case GEDR
: /* GPIO Edge Detect Status registers */
252 s
->status
[bank
] &= ~value
;
253 pxa2xx_gpio_irq_update(s
);
257 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%" HWADDR_PRIX
"\n",
262 static const MemoryRegionOps pxa_gpio_ops
= {
263 .read
= pxa2xx_gpio_read
,
264 .write
= pxa2xx_gpio_write
,
265 .endianness
= DEVICE_NATIVE_ENDIAN
,
268 DeviceState
*pxa2xx_gpio_init(hwaddr base
,
269 ARMCPU
*cpu
, DeviceState
*pic
, int lines
)
271 CPUState
*cs
= CPU(cpu
);
274 dev
= qdev_new(TYPE_PXA2XX_GPIO
);
275 qdev_prop_set_int32(dev
, "lines", lines
);
276 qdev_prop_set_int32(dev
, "ncpu", cs
->cpu_index
);
277 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
279 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
280 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
281 qdev_get_gpio_in(pic
, PXA2XX_PIC_GPIO_0
));
282 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1,
283 qdev_get_gpio_in(pic
, PXA2XX_PIC_GPIO_1
));
284 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2,
285 qdev_get_gpio_in(pic
, PXA2XX_PIC_GPIO_X
));
290 static void pxa2xx_gpio_initfn(Object
*obj
)
292 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
293 DeviceState
*dev
= DEVICE(sbd
);
294 PXA2xxGPIOInfo
*s
= PXA2XX_GPIO(dev
);
296 memory_region_init_io(&s
->iomem
, obj
, &pxa_gpio_ops
,
297 s
, "pxa2xx-gpio", 0x1000);
298 sysbus_init_mmio(sbd
, &s
->iomem
);
299 sysbus_init_irq(sbd
, &s
->irq0
);
300 sysbus_init_irq(sbd
, &s
->irq1
);
301 sysbus_init_irq(sbd
, &s
->irqX
);
304 static void pxa2xx_gpio_realize(DeviceState
*dev
, Error
**errp
)
306 PXA2xxGPIOInfo
*s
= PXA2XX_GPIO(dev
);
308 s
->cpu
= ARM_CPU(qemu_get_cpu(s
->ncpu
));
310 qdev_init_gpio_in(dev
, pxa2xx_gpio_set
, s
->lines
);
311 qdev_init_gpio_out(dev
, s
->handler
, s
->lines
);
315 * Registers a callback to notify on GPLR reads. This normally
316 * shouldn't be needed but it is used for the hack on Spitz machines.
318 void pxa2xx_gpio_read_notifier(DeviceState
*dev
, qemu_irq handler
)
320 PXA2xxGPIOInfo
*s
= PXA2XX_GPIO(dev
);
322 s
->read_notify
= handler
;
325 static const VMStateDescription vmstate_pxa2xx_gpio_regs
= {
326 .name
= "pxa2xx-gpio",
328 .minimum_version_id
= 1,
329 .fields
= (VMStateField
[]) {
330 VMSTATE_UINT32_ARRAY(ilevel
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
331 VMSTATE_UINT32_ARRAY(olevel
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
332 VMSTATE_UINT32_ARRAY(dir
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
333 VMSTATE_UINT32_ARRAY(rising
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
334 VMSTATE_UINT32_ARRAY(falling
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
335 VMSTATE_UINT32_ARRAY(status
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
336 VMSTATE_UINT32_ARRAY(gafr
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
* 2),
337 VMSTATE_UINT32_ARRAY(prev_level
, PXA2xxGPIOInfo
, PXA2XX_GPIO_BANKS
),
338 VMSTATE_END_OF_LIST(),
342 static Property pxa2xx_gpio_properties
[] = {
343 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo
, lines
, 0),
344 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo
, ncpu
, 0),
345 DEFINE_PROP_END_OF_LIST(),
348 static void pxa2xx_gpio_class_init(ObjectClass
*klass
, void *data
)
350 DeviceClass
*dc
= DEVICE_CLASS(klass
);
352 dc
->desc
= "PXA2xx GPIO controller";
353 device_class_set_props(dc
, pxa2xx_gpio_properties
);
354 dc
->vmsd
= &vmstate_pxa2xx_gpio_regs
;
355 dc
->realize
= pxa2xx_gpio_realize
;
358 static const TypeInfo pxa2xx_gpio_info
= {
359 .name
= TYPE_PXA2XX_GPIO
,
360 .parent
= TYPE_SYS_BUS_DEVICE
,
361 .instance_size
= sizeof(PXA2xxGPIOInfo
),
362 .instance_init
= pxa2xx_gpio_initfn
,
363 .class_init
= pxa2xx_gpio_class_init
,
366 static void pxa2xx_gpio_register_types(void)
368 type_register_static(&pxa2xx_gpio_info
);
371 type_init(pxa2xx_gpio_register_types
)