hw/arm/mps2-tz.c

   1 /*
   2  * ARM V2M MPS2 board emulation, trustzone aware FPGA images
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * This source file covers the following FPGA images, for TrustZone cores:
  17  *  "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
  18  *  "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
  19  *
  20  * Links to the TRM for the board itself and to the various Application
  21  * Notes which document the FPGA images can be found here:
  22  * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
  23  *
  24  * Board TRM:
  25  * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
  26  * Application Note AN505:
  27  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
  28  * Application Note AN521:
  29  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html
  30  *
  31  * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
  32  * (ARM ECM0601256) for the details of some of the device layout:
  33  *   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  34  * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines
  35  * most of the device layout:
  36  *  http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
  37  *
  38  */
  39
  40 #include "qemu/osdep.h"
  41 #include "qemu/units.h"
  42 #include "qemu/cutils.h"
  43 #include "qapi/error.h"
  44 #include "qemu/error-report.h"
  45 #include "hw/arm/boot.h"
  46 #include "hw/arm/armv7m.h"
  47 #include "hw/or-irq.h"
  48 #include "hw/boards.h"
  49 #include "exec/address-spaces.h"
  50 #include "sysemu/sysemu.h"
  51 #include "hw/misc/unimp.h"
  52 #include "hw/char/cmsdk-apb-uart.h"
  53 #include "hw/timer/cmsdk-apb-timer.h"
  54 #include "hw/misc/mps2-scc.h"
  55 #include "hw/misc/mps2-fpgaio.h"
  56 #include "hw/misc/tz-mpc.h"
  57 #include "hw/misc/tz-msc.h"
  58 #include "hw/arm/armsse.h"
  59 #include "hw/dma/pl080.h"
  60 #include "hw/ssi/pl022.h"
  61 #include "hw/i2c/arm_sbcon_i2c.h"
  62 #include "hw/net/lan9118.h"
  63 #include "net/net.h"
  64 #include "hw/core/split-irq.h"
  65 #include "qom/object.h"
  66
  67 #define MPS2TZ_NUMIRQ 92
  68
  69 typedef enum MPS2TZFPGAType {
  70     FPGA_AN505,
  71     FPGA_AN521,
  72 } MPS2TZFPGAType;
  73
  74 struct MPS2TZMachineClass {
  75     MachineClass parent;
  76     MPS2TZFPGAType fpga_type;
  77     uint32_t scc_id;
  78     const char *armsse_type;
  79 };
  80 typedef struct MPS2TZMachineClass MPS2TZMachineClass;
  81
  82 struct MPS2TZMachineState {
  83     MachineState parent;
  84
  85     ARMSSE iotkit;
  86     MemoryRegion ssram[3];
  87     MemoryRegion ssram1_m;
  88     MPS2SCC scc;
  89     MPS2FPGAIO fpgaio;
  90     TZPPC ppc[5];
  91     TZMPC ssram_mpc[3];
  92     PL022State spi[5];
  93     ArmSbconI2CState i2c[4];
  94     UnimplementedDeviceState i2s_audio;
  95     UnimplementedDeviceState gpio[4];
  96     UnimplementedDeviceState gfx;
  97     PL080State dma[4];
  98     TZMSC msc[4];
  99     CMSDKAPBUART uart[5];
 100     SplitIRQ sec_resp_splitter;
 101     qemu_or_irq uart_irq_orgate;
 102     DeviceState *lan9118;
 103     SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
 104 };
 105 typedef struct MPS2TZMachineState MPS2TZMachineState;
 106
 107 #define TYPE_MPS2TZ_MACHINE "mps2tz"
 108 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
 109 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
 110
 111 DECLARE_OBJ_CHECKERS(MPS2TZMachineState, MPS2TZMachineClass,
 112                      MPS2TZ_MACHINE, TYPE_MPS2TZ_MACHINE)
 113
 114 /* Main SYSCLK frequency in Hz */
 115 #define SYSCLK_FRQ 20000000
 116
 117 /* Create an alias of an entire original MemoryRegion @orig
 118  * located at @base in the memory map.
 119  */
 120 static void make_ram_alias(MemoryRegion *mr, const char *name,
 121                            MemoryRegion *orig, hwaddr base)
 122 {
 123     memory_region_init_alias(mr, NULL, name, orig, 0,
 124                              memory_region_size(orig));
 125     memory_region_add_subregion(get_system_memory(), base, mr);
 126 }
 127
 128 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
 129 {
 130     /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
 131     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 132
 133     assert(irqno < MPS2TZ_NUMIRQ);
 134
 135     switch (mmc->fpga_type) {
 136     case FPGA_AN505:
 137         return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno);
 138     case FPGA_AN521:
 139         return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
 140     default:
 141         g_assert_not_reached();
 142     }
 143 }
 144
 145 /* Most of the devices in the AN505 FPGA image sit behind
 146  * Peripheral Protection Controllers. These data structures
 147  * define the layout of which devices sit behind which PPCs.
 148  * The devfn for each port is a function which creates, configures
 149  * and initializes the device, returning the MemoryRegion which
 150  * needs to be plugged into the downstream end of the PPC port.
 151  */
 152 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
 153                                 const char *name, hwaddr size);
 154
 155 typedef struct PPCPortInfo {
 156     const char *name;
 157     MakeDevFn *devfn;
 158     void *opaque;
 159     hwaddr addr;
 160     hwaddr size;
 161 } PPCPortInfo;
 162
 163 typedef struct PPCInfo {
 164     const char *name;
 165     PPCPortInfo ports[TZ_NUM_PORTS];
 166 } PPCInfo;
 167
 168 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
 169                                        void *opaque,
 170                                        const char *name, hwaddr size)
 171 {
 172     /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
 173      * and return a pointer to its MemoryRegion.
 174      */
 175     UnimplementedDeviceState *uds = opaque;
 176
 177     object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
 178     qdev_prop_set_string(DEVICE(uds), "name", name);
 179     qdev_prop_set_uint64(DEVICE(uds), "size", size);
 180     sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
 181     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
 182 }
 183
 184 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
 185                                const char *name, hwaddr size)
 186 {
 187     CMSDKAPBUART *uart = opaque;
 188     int i = uart - &mms->uart[0];
 189     int rxirqno = i * 2;
 190     int txirqno = i * 2 + 1;
 191     int combirqno = i + 10;
 192     SysBusDevice *s;
 193     DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
 194
 195     object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
 196     qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
 197     qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
 198     sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
 199     s = SYS_BUS_DEVICE(uart);
 200     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
 201     sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));
 202     sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
 203     sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
 204     sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno));
 205     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
 206 }
 207
 208 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
 209                               const char *name, hwaddr size)
 210 {
 211     MPS2SCC *scc = opaque;
 212     DeviceState *sccdev;
 213     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 214
 215     object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
 216     sccdev = DEVICE(scc);
 217     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 218     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 219     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 220     sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
 221     return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
 222 }
 223
 224 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
 225                                  const char *name, hwaddr size)
 226 {
 227     MPS2FPGAIO *fpgaio = opaque;
 228
 229     object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
 230     sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
 231     return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
 232 }
 233
 234 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
 235                                   const char *name, hwaddr size)
 236 {
 237     SysBusDevice *s;
 238     NICInfo *nd = &nd_table[0];
 239
 240     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 241      * except that it doesn't support the checksum-offload feature.
 242      */
 243     qemu_check_nic_model(nd, "lan9118");
 244     mms->lan9118 = qdev_new(TYPE_LAN9118);
 245     qdev_set_nic_properties(mms->lan9118, nd);
 246
 247     s = SYS_BUS_DEVICE(mms->lan9118);
 248     sysbus_realize_and_unref(s, &error_fatal);
 249     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
 250     return sysbus_mmio_get_region(s, 0);
 251 }
 252
 253 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
 254                               const char *name, hwaddr size)
 255 {
 256     TZMPC *mpc = opaque;
 257     int i = mpc - &mms->ssram_mpc[0];
 258     MemoryRegion *ssram = &mms->ssram[i];
 259     MemoryRegion *upstream;
 260     char *mpcname = g_strdup_printf("%s-mpc", name);
 261     static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };
 262     static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };
 263
 264     memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
 265
 266     object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
 267     object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram),
 268                              &error_fatal);
 269     sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
 270     /* Map the upstream end of the MPC into system memory */
 271     upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
 272     memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
 273     /* and connect its interrupt to the IoTKit */
 274     qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
 275                                 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 276                                                        "mpcexp_status", i));
 277
 278     /* The first SSRAM is a special case as it has an alias; accesses to
 279      * the alias region at 0x00400000 must also go to the MPC upstream.
 280      */
 281     if (i == 0) {
 282         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);
 283     }
 284
 285     g_free(mpcname);
 286     /* Return the register interface MR for our caller to map behind the PPC */
 287     return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
 288 }
 289
 290 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
 291                               const char *name, hwaddr size)
 292 {
 293     PL080State *dma = opaque;
 294     int i = dma - &mms->dma[0];
 295     SysBusDevice *s;
 296     char *mscname = g_strdup_printf("%s-msc", name);
 297     TZMSC *msc = &mms->msc[i];
 298     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 299     MemoryRegion *msc_upstream;
 300     MemoryRegion *msc_downstream;
 301
 302     /*
 303      * Each DMA device is a PL081 whose transaction master interface
 304      * is guarded by a Master Security Controller. The downstream end of
 305      * the MSC connects to the IoTKit AHB Slave Expansion port, so the
 306      * DMA devices can see all devices and memory that the CPU does.
 307      */
 308     object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC);
 309     msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
 310     object_property_set_link(OBJECT(msc), "downstream",
 311                              OBJECT(msc_downstream), &error_fatal);
 312     object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal);
 313     sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal);
 314
 315     qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
 316                                 qdev_get_gpio_in_named(iotkitdev,
 317                                                        "mscexp_status", i));
 318     qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i,
 319                                 qdev_get_gpio_in_named(DEVICE(msc),
 320                                                        "irq_clear", 0));
 321     qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i,
 322                                 qdev_get_gpio_in_named(DEVICE(msc),
 323                                                        "cfg_nonsec", 0));
 324     qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter),
 325                           ARRAY_SIZE(mms->ppc) + i,
 326                           qdev_get_gpio_in_named(DEVICE(msc),
 327                                                  "cfg_sec_resp", 0));
 328     msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
 329
 330     object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081);
 331     object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream),
 332                              &error_fatal);
 333     sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal);
 334
 335     s = SYS_BUS_DEVICE(dma);
 336     /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
 337     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3));
 338     sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3));
 339     sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3));
 340
 341     g_free(mscname);
 342     return sysbus_mmio_get_region(s, 0);
 343 }
 344
 345 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
 346                               const char *name, hwaddr size)
 347 {
 348     /*
 349      * The AN505 has five PL022 SPI controllers.
 350      * One of these should have the LCD controller behind it; the others
 351      * are connected only to the FPGA's "general purpose SPI connector"
 352      * or "shield" expansion connectors.
 353      * Note that if we do implement devices behind SPI, the chip select
 354      * lines are set via the "MISC" register in the MPS2 FPGAIO device.
 355      */
 356     PL022State *spi = opaque;
 357     int i = spi - &mms->spi[0];
 358     SysBusDevice *s;
 359
 360     object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
 361     sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
 362     s = SYS_BUS_DEVICE(spi);
 363     sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i));
 364     return sysbus_mmio_get_region(s, 0);
 365 }
 366
 367 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
 368                               const char *name, hwaddr size)
 369 {
 370     ArmSbconI2CState *i2c = opaque;
 371     SysBusDevice *s;
 372
 373     object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
 374     s = SYS_BUS_DEVICE(i2c);
 375     sysbus_realize(s, &error_fatal);
 376     return sysbus_mmio_get_region(s, 0);
 377 }
 378
 379 static void mps2tz_common_init(MachineState *machine)
 380 {
 381     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
 382     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 383     MachineClass *mc = MACHINE_GET_CLASS(machine);
 384     MemoryRegion *system_memory = get_system_memory();
 385     DeviceState *iotkitdev;
 386     DeviceState *dev_splitter;
 387     int i;
 388
 389     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 390         error_report("This board can only be used with CPU %s",
 391                      mc->default_cpu_type);
 392         exit(1);
 393     }
 394
 395     if (machine->ram_size != mc->default_ram_size) {
 396         char *sz = size_to_str(mc->default_ram_size);
 397         error_report("Invalid RAM size, should be %s", sz);
 398         g_free(sz);
 399         exit(EXIT_FAILURE);
 400     }
 401
 402     object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
 403                             mmc->armsse_type);
 404     iotkitdev = DEVICE(&mms->iotkit);
 405     object_property_set_link(OBJECT(&mms->iotkit), "memory",
 406                              OBJECT(system_memory), &error_abort);
 407     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
 408     qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
 409     sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
 410
 411     /*
 412      * The AN521 needs us to create splitters to feed the IRQ inputs
 413      * for each CPU in the SSE-200 from each device in the board.
 414      */
 415     if (mmc->fpga_type == FPGA_AN521) {
 416         for (i = 0; i < MPS2TZ_NUMIRQ; i++) {
 417             char *name = g_strdup_printf("mps2-irq-splitter%d", i);
 418             SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
 419
 420             object_initialize_child_with_props(OBJECT(machine), name,
 421                                                splitter, sizeof(*splitter),
 422                                                TYPE_SPLIT_IRQ, &error_fatal,
 423                                                NULL);
 424             g_free(name);
 425
 426             object_property_set_int(OBJECT(splitter), "num-lines", 2,
 427                                     &error_fatal);
 428             qdev_realize(DEVICE(splitter), NULL, &error_fatal);
 429             qdev_connect_gpio_out(DEVICE(splitter), 0,
 430                                   qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 431                                                          "EXP_IRQ", i));
 432             qdev_connect_gpio_out(DEVICE(splitter), 1,
 433                                   qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 434                                                          "EXP_CPU1_IRQ", i));
 435         }
 436     }
 437
 438     /* The sec_resp_cfg output from the IoTKit must be split into multiple
 439      * lines, one for each of the PPCs we create here, plus one per MSC.
 440      */
 441     object_initialize_child(OBJECT(machine), "sec-resp-splitter",
 442                             &mms->sec_resp_splitter, TYPE_SPLIT_IRQ);
 443     object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines",
 444                             ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
 445                             &error_fatal);
 446     qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
 447     dev_splitter = DEVICE(&mms->sec_resp_splitter);
 448     qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
 449                                 qdev_get_gpio_in(dev_splitter, 0));
 450
 451     /* The IoTKit sets up much of the memory layout, including
 452      * the aliases between secure and non-secure regions in the
 453      * address space. The FPGA itself contains:
 454      *
 455      * 0x00000000..0x003fffff  SSRAM1
 456      * 0x00400000..0x007fffff  alias of SSRAM1
 457      * 0x28000000..0x283fffff  4MB SSRAM2 + SSRAM3
 458      * 0x40100000..0x4fffffff  AHB Master Expansion 1 interface devices
 459      * 0x80000000..0x80ffffff  16MB PSRAM
 460      */
 461
 462     /* The FPGA images have an odd combination of different RAMs,
 463      * because in hardware they are different implementations and
 464      * connected to different buses, giving varying performance/size
 465      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 466      * call the 16MB our "system memory", as it's the largest lump.
 467      */
 468     memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
 469
 470     /* The overflow IRQs for all UARTs are ORed together.
 471      * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
 472      * Create the OR gate for this.
 473      */
 474     object_initialize_child(OBJECT(mms), "uart-irq-orgate",
 475                             &mms->uart_irq_orgate, TYPE_OR_IRQ);
 476     object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10,
 477                             &error_fatal);
 478     qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
 479     qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
 480                           get_sse_irq_in(mms, 15));
 481
 482     /* Most of the devices in the FPGA are behind Peripheral Protection
 483      * Controllers. The required order for initializing things is:
 484      *  + initialize the PPC
 485      *  + initialize, configure and realize downstream devices
 486      *  + connect downstream device MemoryRegions to the PPC
 487      *  + realize the PPC
 488      *  + map the PPC's MemoryRegions to the places in the address map
 489      *    where the downstream devices should appear
 490      *  + wire up the PPC's control lines to the IoTKit object
 491      */
 492
 493     const PPCInfo ppcs[] = { {
 494             .name = "apb_ppcexp0",
 495             .ports = {
 496                 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
 497                 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },
 498                 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },
 499             },
 500         }, {
 501             .name = "apb_ppcexp1",
 502             .ports = {
 503                 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 },
 504                 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 },
 505                 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 },
 506                 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 },
 507                 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 },
 508                 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
 509                 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
 510                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
 511                 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
 512                 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
 513                 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
 514                 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
 515                 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
 516                 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 },
 517             },
 518         }, {
 519             .name = "apb_ppcexp2",
 520             .ports = {
 521                 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
 522                 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
 523                   0x40301000, 0x1000 },
 524                 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
 525             },
 526         }, {
 527             .name = "ahb_ppcexp0",
 528             .ports = {
 529                 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
 530                 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
 531                 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
 532                 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
 533                 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
 534                 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 },
 535             },
 536         }, {
 537             .name = "ahb_ppcexp1",
 538             .ports = {
 539                 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 },
 540                 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 },
 541                 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 },
 542                 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 },
 543             },
 544         },
 545     };
 546
 547     for (i = 0; i < ARRAY_SIZE(ppcs); i++) {
 548         const PPCInfo *ppcinfo = &ppcs[i];
 549         TZPPC *ppc = &mms->ppc[i];
 550         DeviceState *ppcdev;
 551         int port;
 552         char *gpioname;
 553
 554         object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
 555                                 TYPE_TZ_PPC);
 556         ppcdev = DEVICE(ppc);
 557
 558         for (port = 0; port < TZ_NUM_PORTS; port++) {
 559             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 560             MemoryRegion *mr;
 561             char *portname;
 562
 563             if (!pinfo->devfn) {
 564                 continue;
 565             }
 566
 567             mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
 568             portname = g_strdup_printf("port[%d]", port);
 569             object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
 570                                      &error_fatal);
 571             g_free(portname);
 572         }
 573
 574         sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
 575
 576         for (port = 0; port < TZ_NUM_PORTS; port++) {
 577             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 578
 579             if (!pinfo->devfn) {
 580                 continue;
 581             }
 582             sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
 583
 584             gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
 585             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 586                                         qdev_get_gpio_in_named(ppcdev,
 587                                                                "cfg_nonsec",
 588                                                                port));
 589             g_free(gpioname);
 590             gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
 591             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 592                                         qdev_get_gpio_in_named(ppcdev,
 593                                                                "cfg_ap", port));
 594             g_free(gpioname);
 595         }
 596
 597         gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
 598         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 599                                     qdev_get_gpio_in_named(ppcdev,
 600                                                            "irq_enable", 0));
 601         g_free(gpioname);
 602         gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
 603         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 604                                     qdev_get_gpio_in_named(ppcdev,
 605                                                            "irq_clear", 0));
 606         g_free(gpioname);
 607         gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
 608         qdev_connect_gpio_out_named(ppcdev, "irq", 0,
 609                                     qdev_get_gpio_in_named(iotkitdev,
 610                                                            gpioname, 0));
 611         g_free(gpioname);
 612
 613         qdev_connect_gpio_out(dev_splitter, i,
 614                               qdev_get_gpio_in_named(ppcdev,
 615                                                      "cfg_sec_resp", 0));
 616     }
 617
 618     create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
 619
 620     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
 621 }
 622
 623 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
 624                                int *iregion, bool *exempt, bool *ns, bool *nsc)
 625 {
 626     /*
 627      * The MPS2 TZ FPGA images have IDAUs in them which are connected to
 628      * the Master Security Controllers. Thes have the same logic as
 629      * is used by the IoTKit for the IDAU connected to the CPU, except
 630      * that MSCs don't care about the NSC attribute.
 631      */
 632     int region = extract32(address, 28, 4);
 633
 634     *ns = !(region & 1);
 635     *nsc = false;
 636     /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
 637     *exempt = (address & 0xeff00000) == 0xe0000000;
 638     *iregion = region;
 639 }
 640
 641 static void mps2tz_class_init(ObjectClass *oc, void *data)
 642 {
 643     MachineClass *mc = MACHINE_CLASS(oc);
 644     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 645
 646     mc->init = mps2tz_common_init;
 647     iic->check = mps2_tz_idau_check;
 648     mc->default_ram_size = 16 * MiB;
 649     mc->default_ram_id = "mps.ram";
 650 }
 651
 652 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
 653 {
 654     MachineClass *mc = MACHINE_CLASS(oc);
 655     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 656
 657     mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
 658     mc->default_cpus = 1;
 659     mc->min_cpus = mc->default_cpus;
 660     mc->max_cpus = mc->default_cpus;
 661     mmc->fpga_type = FPGA_AN505;
 662     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 663     mmc->scc_id = 0x41045050;
 664     mmc->armsse_type = TYPE_IOTKIT;
 665 }
 666
 667 static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
 668 {
 669     MachineClass *mc = MACHINE_CLASS(oc);
 670     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 671
 672     mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
 673     mc->default_cpus = 2;
 674     mc->min_cpus = mc->default_cpus;
 675     mc->max_cpus = mc->default_cpus;
 676     mmc->fpga_type = FPGA_AN521;
 677     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 678     mmc->scc_id = 0x41045210;
 679     mmc->armsse_type = TYPE_SSE200;
 680 }
 681
 682 static const TypeInfo mps2tz_info = {
 683     .name = TYPE_MPS2TZ_MACHINE,
 684     .parent = TYPE_MACHINE,
 685     .abstract = true,
 686     .instance_size = sizeof(MPS2TZMachineState),
 687     .class_size = sizeof(MPS2TZMachineClass),
 688     .class_init = mps2tz_class_init,
 689     .interfaces = (InterfaceInfo[]) {
 690         { TYPE_IDAU_INTERFACE },
 691         { }
 692     },
 693 };
 694
 695 static const TypeInfo mps2tz_an505_info = {
 696     .name = TYPE_MPS2TZ_AN505_MACHINE,
 697     .parent = TYPE_MPS2TZ_MACHINE,
 698     .class_init = mps2tz_an505_class_init,
 699 };
 700
 701 static const TypeInfo mps2tz_an521_info = {
 702     .name = TYPE_MPS2TZ_AN521_MACHINE,
 703     .parent = TYPE_MPS2TZ_MACHINE,
 704     .class_init = mps2tz_an521_class_init,
 705 };
 706
 707 static void mps2tz_machine_init(void)
 708 {
 709     type_register_static(&mps2tz_info);
 710     type_register_static(&mps2tz_an505_info);
 711     type_register_static(&mps2tz_an521_info);
 712 }
 713
 714 type_init(mps2tz_machine_init);