1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/range.h"
30 #include "qemu/error-report.h"
31 #include "hw/pci/pci.h"
33 #include "hw/i386/pc.h"
34 #include "target-i386/cpu.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
57 #include "hw/acpi/aml-build.h"
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "exec/ram_addr.h"
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
73 /* Reserve RAM space for tables: add another order of magnitude. */
74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
84 typedef struct AcpiCpuInfo
{
85 DECLARE_BITMAP(found_cpus
, ACPI_CPU_HOTPLUG_ID_LIMIT
);
88 typedef struct AcpiMcfgInfo
{
93 typedef struct AcpiPmInfo
{
99 uint8_t acpi_enable_cmd
;
100 uint8_t acpi_disable_cmd
;
102 uint32_t gpe0_blk_len
;
104 uint16_t cpu_hp_io_base
;
105 uint16_t cpu_hp_io_len
;
106 uint16_t mem_hp_io_base
;
107 uint16_t mem_hp_io_len
;
108 uint16_t pcihp_io_base
;
109 uint16_t pcihp_io_len
;
112 typedef struct AcpiMiscInfo
{
115 DECLARE_BITMAP(slot_hotplug_enable
, PCI_SLOT_MAX
);
116 const unsigned char *dsdt_code
;
118 uint16_t pvpanic_port
;
121 typedef struct AcpiBuildPciBusHotplugState
{
122 GArray
*device_table
;
123 GArray
*notify_table
;
124 struct AcpiBuildPciBusHotplugState
*parent
;
125 bool pcihp_bridge_en
;
126 } AcpiBuildPciBusHotplugState
;
128 static void acpi_get_dsdt(AcpiMiscInfo
*info
)
130 uint16_t *applesmc_sta
;
131 Object
*piix
= piix4_pm_find();
132 Object
*lpc
= ich9_lpc_find();
133 assert(!!piix
!= !!lpc
);
136 info
->dsdt_code
= AcpiDsdtAmlCode
;
137 info
->dsdt_size
= sizeof AcpiDsdtAmlCode
;
138 applesmc_sta
= piix_dsdt_applesmc_sta
;
141 info
->dsdt_code
= Q35AcpiDsdtAmlCode
;
142 info
->dsdt_size
= sizeof Q35AcpiDsdtAmlCode
;
143 applesmc_sta
= q35_dsdt_applesmc_sta
;
146 /* Patch in appropriate value for AppleSMC _STA */
147 *(uint8_t *)(info
->dsdt_code
+ *applesmc_sta
) =
148 applesmc_find() ? 0x0b : 0x00;
152 int acpi_add_cpu_info(Object
*o
, void *opaque
)
154 AcpiCpuInfo
*cpu
= opaque
;
157 if (object_dynamic_cast(o
, TYPE_CPU
)) {
158 apic_id
= object_property_get_int(o
, "apic-id", NULL
);
159 assert(apic_id
< ACPI_CPU_HOTPLUG_ID_LIMIT
);
161 set_bit(apic_id
, cpu
->found_cpus
);
164 object_child_foreach(o
, acpi_add_cpu_info
, opaque
);
168 static void acpi_get_cpu_info(AcpiCpuInfo
*cpu
)
170 Object
*root
= object_get_root();
172 memset(cpu
->found_cpus
, 0, sizeof cpu
->found_cpus
);
173 object_child_foreach(root
, acpi_add_cpu_info
, cpu
);
176 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
178 Object
*piix
= piix4_pm_find();
179 Object
*lpc
= ich9_lpc_find();
183 pm
->pcihp_io_base
= 0;
184 pm
->pcihp_io_len
= 0;
187 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
189 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
191 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
195 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
199 pm
->cpu_hp_io_len
= ACPI_GPE_PROC_LEN
;
200 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
201 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
203 /* Fill in optional s3/s4 related properties */
204 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
206 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
208 pm
->s3_disabled
= false;
211 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
213 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
215 pm
->s4_disabled
= false;
218 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
220 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
226 /* Fill in mandatory properties */
227 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
229 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
230 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
232 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
233 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
235 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
237 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
239 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
241 pm
->pcihp_bridge_en
=
242 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
246 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
248 info
->has_hpet
= hpet_find();
249 info
->has_tpm
= tpm_find();
250 info
->pvpanic_port
= pvpanic_port();
253 static void acpi_get_pci_info(PcPciInfo
*info
)
258 pci_host
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
259 g_assert(!ambiguous
);
262 info
->w32
.begin
= object_property_get_int(pci_host
,
263 PCI_HOST_PROP_PCI_HOLE_START
,
265 info
->w32
.end
= object_property_get_int(pci_host
,
266 PCI_HOST_PROP_PCI_HOLE_END
,
268 info
->w64
.begin
= object_property_get_int(pci_host
,
269 PCI_HOST_PROP_PCI_HOLE64_START
,
271 info
->w64
.end
= object_property_get_int(pci_host
,
272 PCI_HOST_PROP_PCI_HOLE64_END
,
276 #define ACPI_BUILD_APPNAME "Bochs"
277 #define ACPI_BUILD_APPNAME6 "BOCHS "
278 #define ACPI_BUILD_APPNAME4 "BXPC"
280 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
281 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
282 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
285 build_header(GArray
*linker
, GArray
*table_data
,
286 AcpiTableHeader
*h
, const char *sig
, int len
, uint8_t rev
)
288 memcpy(&h
->signature
, sig
, 4);
289 h
->length
= cpu_to_le32(len
);
291 memcpy(h
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
292 memcpy(h
->oem_table_id
, ACPI_BUILD_APPNAME4
, 4);
293 memcpy(h
->oem_table_id
+ 4, sig
, 4);
294 h
->oem_revision
= cpu_to_le32(1);
295 memcpy(h
->asl_compiler_id
, ACPI_BUILD_APPNAME4
, 4);
296 h
->asl_compiler_revision
= cpu_to_le32(1);
298 /* Checksum to be filled in by Guest linker */
299 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_TABLE_FILE
,
300 table_data
->data
, h
, len
, &h
->checksum
);
303 static GArray
*build_alloc_method(const char *name
, uint8_t arg_count
)
305 GArray
*method
= build_alloc_array();
307 build_append_namestring(method
, "%s", name
);
308 build_append_byte(method
, arg_count
); /* MethodFlags: ArgCount */
313 static void build_append_and_cleanup_method(GArray
*device
, GArray
*method
)
315 uint8_t op
= 0x14; /* MethodOp */
317 build_package(method
, op
);
319 build_append_array(device
, method
);
320 build_free_array(method
);
324 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
326 static inline void *acpi_data_push(GArray
*table_data
, unsigned size
)
328 unsigned off
= table_data
->len
;
329 g_array_set_size(table_data
, off
+ size
);
330 return table_data
->data
+ off
;
333 static unsigned acpi_data_len(GArray
*table
)
335 #if GLIB_CHECK_VERSION(2, 22, 0)
336 assert(g_array_get_element_size(table
) == 1);
341 static void acpi_align_size(GArray
*blob
, unsigned align
)
343 /* Align size to multiple of given size. This reduces the chance
344 * we need to change size in the future (breaking cross version migration).
346 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
349 static inline void acpi_add_table(GArray
*table_offsets
, GArray
*table_data
)
351 uint32_t offset
= cpu_to_le32(table_data
->len
);
352 g_array_append_val(table_offsets
, offset
);
357 build_facs(GArray
*table_data
, GArray
*linker
, PcGuestInfo
*guest_info
)
359 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
360 memcpy(&facs
->signature
, "FACS", 4);
361 facs
->length
= cpu_to_le32(sizeof(*facs
));
364 /* Load chipset information in FADT */
365 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
369 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
370 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
371 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
372 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
373 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
374 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
375 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
376 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
377 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
378 /* EVT, CNT, TMR length matches hw/acpi/core.c */
379 fadt
->pm1_evt_len
= 4;
380 fadt
->pm1_cnt_len
= 2;
381 fadt
->pm_tmr_len
= 4;
382 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
383 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
384 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
385 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
386 (1 << ACPI_FADT_F_PROC_C1
) |
387 (1 << ACPI_FADT_F_SLP_BUTTON
) |
388 (1 << ACPI_FADT_F_RTC_S4
));
389 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
390 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
391 * For more than 8 CPUs, "Clustered Logical" mode has to be used
394 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
401 build_fadt(GArray
*table_data
, GArray
*linker
, AcpiPmInfo
*pm
,
402 unsigned facs
, unsigned dsdt
)
404 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
406 fadt
->firmware_ctrl
= cpu_to_le32(facs
);
407 /* FACS address to be filled by Guest linker */
408 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
409 ACPI_BUILD_TABLE_FILE
,
410 table_data
, &fadt
->firmware_ctrl
,
411 sizeof fadt
->firmware_ctrl
);
413 fadt
->dsdt
= cpu_to_le32(dsdt
);
414 /* DSDT address to be filled by Guest linker */
415 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
416 ACPI_BUILD_TABLE_FILE
,
417 table_data
, &fadt
->dsdt
,
420 fadt_setup(fadt
, pm
);
422 build_header(linker
, table_data
,
423 (void *)fadt
, "FACP", sizeof(*fadt
), 1);
427 build_madt(GArray
*table_data
, GArray
*linker
, AcpiCpuInfo
*cpu
,
428 PcGuestInfo
*guest_info
)
430 int madt_start
= table_data
->len
;
432 AcpiMultipleApicTable
*madt
;
433 AcpiMadtIoApic
*io_apic
;
434 AcpiMadtIntsrcovr
*intsrcovr
;
435 AcpiMadtLocalNmi
*local_nmi
;
438 madt
= acpi_data_push(table_data
, sizeof *madt
);
439 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
440 madt
->flags
= cpu_to_le32(1);
442 for (i
= 0; i
< guest_info
->apic_id_limit
; i
++) {
443 AcpiMadtProcessorApic
*apic
= acpi_data_push(table_data
, sizeof *apic
);
444 apic
->type
= ACPI_APIC_PROCESSOR
;
445 apic
->length
= sizeof(*apic
);
446 apic
->processor_id
= i
;
447 apic
->local_apic_id
= i
;
448 if (test_bit(i
, cpu
->found_cpus
)) {
449 apic
->flags
= cpu_to_le32(1);
451 apic
->flags
= cpu_to_le32(0);
454 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
455 io_apic
->type
= ACPI_APIC_IO
;
456 io_apic
->length
= sizeof(*io_apic
);
457 #define ACPI_BUILD_IOAPIC_ID 0x0
458 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
459 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
460 io_apic
->interrupt
= cpu_to_le32(0);
462 if (guest_info
->apic_xrupt_override
) {
463 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
464 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
465 intsrcovr
->length
= sizeof(*intsrcovr
);
466 intsrcovr
->source
= 0;
467 intsrcovr
->gsi
= cpu_to_le32(2);
468 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
470 for (i
= 1; i
< 16; i
++) {
471 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
472 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
473 /* No need for a INT source override structure. */
476 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
477 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
478 intsrcovr
->length
= sizeof(*intsrcovr
);
479 intsrcovr
->source
= i
;
480 intsrcovr
->gsi
= cpu_to_le32(i
);
481 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
484 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
485 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
486 local_nmi
->length
= sizeof(*local_nmi
);
487 local_nmi
->processor_id
= 0xff; /* all processors */
488 local_nmi
->flags
= cpu_to_le16(0);
489 local_nmi
->lint
= 1; /* ACPI_LINT1 */
491 build_header(linker
, table_data
,
492 (void *)(table_data
->data
+ madt_start
), "APIC",
493 table_data
->len
- madt_start
, 1);
496 /* Encode a hex value */
497 static inline char acpi_get_hex(uint32_t val
)
500 return (val
<= 9) ? ('0' + val
) : ('A' + val
- 10);
503 /* 0x5B 0x82 DeviceOp PkgLength NameString */
504 #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
505 #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
506 #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
507 #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
508 #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
509 #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
511 #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1)
512 #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start)
513 #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start)
514 #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start)
516 #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1)
517 #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start)
518 #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start)
519 #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start)
521 #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1)
522 #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start)
523 #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start)
524 #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start)
526 #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
527 #define ACPI_SSDT_HEADER_LENGTH 36
529 #include "hw/i386/ssdt-misc.hex"
530 #include "hw/i386/ssdt-pcihp.hex"
531 #include "hw/i386/ssdt-tpm.hex"
533 static void patch_pcihp(int slot
, uint8_t *ssdt_ptr
)
535 unsigned devfn
= PCI_DEVFN(slot
, 0);
537 ssdt_ptr
[ACPI_PCIHP_OFFSET_HEX
] = acpi_get_hex(devfn
>> 4);
538 ssdt_ptr
[ACPI_PCIHP_OFFSET_HEX
+ 1] = acpi_get_hex(devfn
);
539 ssdt_ptr
[ACPI_PCIHP_OFFSET_ID
] = slot
;
540 ssdt_ptr
[ACPI_PCIHP_OFFSET_ADR
+ 2] = slot
;
543 static void patch_pcinohp(int slot
, uint8_t *ssdt_ptr
)
545 unsigned devfn
= PCI_DEVFN(slot
, 0);
547 ssdt_ptr
[ACPI_PCINOHP_OFFSET_HEX
] = acpi_get_hex(devfn
>> 4);
548 ssdt_ptr
[ACPI_PCINOHP_OFFSET_HEX
+ 1] = acpi_get_hex(devfn
);
549 ssdt_ptr
[ACPI_PCINOHP_OFFSET_ADR
+ 2] = slot
;
552 static void patch_pcivga(int slot
, uint8_t *ssdt_ptr
)
554 unsigned devfn
= PCI_DEVFN(slot
, 0);
556 ssdt_ptr
[ACPI_PCIVGA_OFFSET_HEX
] = acpi_get_hex(devfn
>> 4);
557 ssdt_ptr
[ACPI_PCIVGA_OFFSET_HEX
+ 1] = acpi_get_hex(devfn
);
558 ssdt_ptr
[ACPI_PCIVGA_OFFSET_ADR
+ 2] = slot
;
561 static void patch_pciqxl(int slot
, uint8_t *ssdt_ptr
)
563 unsigned devfn
= PCI_DEVFN(slot
, 0);
565 ssdt_ptr
[ACPI_PCIQXL_OFFSET_HEX
] = acpi_get_hex(devfn
>> 4);
566 ssdt_ptr
[ACPI_PCIQXL_OFFSET_HEX
+ 1] = acpi_get_hex(devfn
);
567 ssdt_ptr
[ACPI_PCIQXL_OFFSET_ADR
+ 2] = slot
;
570 /* Assign BSEL property to all buses. In the future, this can be changed
571 * to only assign to buses that support hotplug.
573 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
575 unsigned *bsel_alloc
= opaque
;
578 if (qbus_is_hotpluggable(BUS(bus
))) {
579 bus_bsel
= g_malloc(sizeof *bus_bsel
);
581 *bus_bsel
= (*bsel_alloc
)++;
582 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
589 static void acpi_set_pci_info(void)
591 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
592 unsigned bsel_alloc
= 0;
595 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
596 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
600 static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState
*state
,
601 AcpiBuildPciBusHotplugState
*parent
,
602 bool pcihp_bridge_en
)
604 state
->parent
= parent
;
605 state
->device_table
= build_alloc_array();
606 state
->notify_table
= build_alloc_array();
607 state
->pcihp_bridge_en
= pcihp_bridge_en
;
610 static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState
*state
)
612 build_free_array(state
->device_table
);
613 build_free_array(state
->notify_table
);
616 static void *build_pci_bus_begin(PCIBus
*bus
, void *parent_state
)
618 AcpiBuildPciBusHotplugState
*parent
= parent_state
;
619 AcpiBuildPciBusHotplugState
*child
= g_malloc(sizeof *child
);
621 build_pci_bus_state_init(child
, parent
, parent
->pcihp_bridge_en
);
626 static void build_pci_bus_end(PCIBus
*bus
, void *bus_state
)
628 AcpiBuildPciBusHotplugState
*child
= bus_state
;
629 AcpiBuildPciBusHotplugState
*parent
= child
->parent
;
630 GArray
*bus_table
= build_alloc_array();
631 DECLARE_BITMAP(slot_hotplug_enable
, PCI_SLOT_MAX
);
632 DECLARE_BITMAP(slot_device_present
, PCI_SLOT_MAX
);
633 DECLARE_BITMAP(slot_device_system
, PCI_SLOT_MAX
);
634 DECLARE_BITMAP(slot_device_vga
, PCI_SLOT_MAX
);
635 DECLARE_BITMAP(slot_device_qxl
, PCI_SLOT_MAX
);
640 bool bus_hotplug_support
= false;
643 * Skip bridge subtree creation if bridge hotplug is disabled
644 * to make acpi tables compatible with legacy machine types.
645 * Skip creation for hotplugged bridges as well.
647 if (bus
->parent_dev
&& (!child
->pcihp_bridge_en
||
648 DEVICE(bus
->parent_dev
)->hotplugged
)) {
649 build_free_array(bus_table
);
650 build_pci_bus_state_cleanup(child
);
655 if (bus
->parent_dev
) {
656 op
= 0x82; /* DeviceOp */
657 build_append_namestring(bus_table
, "S%.02X",
658 bus
->parent_dev
->devfn
);
659 build_append_byte(bus_table
, 0x08); /* NameOp */
660 build_append_namestring(bus_table
, "_SUN");
661 build_append_int(bus_table
, PCI_SLOT(bus
->parent_dev
->devfn
));
662 build_append_byte(bus_table
, 0x08); /* NameOp */
663 build_append_namestring(bus_table
, "_ADR");
664 build_append_int(bus_table
, (PCI_SLOT(bus
->parent_dev
->devfn
) << 16) |
665 PCI_FUNC(bus
->parent_dev
->devfn
));
667 op
= 0x10; /* ScopeOp */;
668 build_append_namestring(bus_table
, "PCI0");
671 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
673 build_append_byte(bus_table
, 0x08); /* NameOp */
674 build_append_namestring(bus_table
, "BSEL");
675 build_append_int(bus_table
, qint_get_int(qobject_to_qint(bsel
)));
676 memset(slot_hotplug_enable
, 0xff, sizeof slot_hotplug_enable
);
678 /* No bsel - no slots are hot-pluggable */
679 memset(slot_hotplug_enable
, 0x00, sizeof slot_hotplug_enable
);
682 memset(slot_device_present
, 0x00, sizeof slot_device_present
);
683 memset(slot_device_system
, 0x00, sizeof slot_device_present
);
684 memset(slot_device_vga
, 0x00, sizeof slot_device_vga
);
685 memset(slot_device_qxl
, 0x00, sizeof slot_device_qxl
);
687 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
690 PCIDevice
*pdev
= bus
->devices
[i
];
691 int slot
= PCI_SLOT(i
);
698 set_bit(slot
, slot_device_present
);
699 pc
= PCI_DEVICE_GET_CLASS(pdev
);
700 dc
= DEVICE_GET_CLASS(pdev
);
702 /* When hotplug for bridges is enabled, bridges are
703 * described in ACPI separately (see build_pci_bus_end).
704 * In this case they aren't themselves hot-pluggable.
705 * Hotplugged bridges *are* hot-pluggable.
707 bridge_in_acpi
= pc
->is_bridge
&& child
->pcihp_bridge_en
&&
708 !DEVICE(pdev
)->hotplugged
;
710 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
|| bridge_in_acpi
) {
711 set_bit(slot
, slot_device_system
);
714 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
715 set_bit(slot
, slot_device_vga
);
717 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
718 set_bit(slot
, slot_device_qxl
);
722 if (!dc
->hotpluggable
|| bridge_in_acpi
) {
723 clear_bit(slot
, slot_hotplug_enable
);
727 /* Append Device object for each slot */
728 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
729 bool can_eject
= test_bit(i
, slot_hotplug_enable
);
730 bool present
= test_bit(i
, slot_device_present
);
731 bool vga
= test_bit(i
, slot_device_vga
);
732 bool qxl
= test_bit(i
, slot_device_qxl
);
733 bool system
= test_bit(i
, slot_device_system
);
735 void *pcihp
= acpi_data_push(bus_table
,
737 memcpy(pcihp
, ACPI_PCIHP_AML
, ACPI_PCIHP_SIZEOF
);
738 patch_pcihp(i
, pcihp
);
739 bus_hotplug_support
= true;
741 void *pcihp
= acpi_data_push(bus_table
,
743 memcpy(pcihp
, ACPI_PCIQXL_AML
, ACPI_PCIQXL_SIZEOF
);
744 patch_pciqxl(i
, pcihp
);
746 void *pcihp
= acpi_data_push(bus_table
,
748 memcpy(pcihp
, ACPI_PCIVGA_AML
, ACPI_PCIVGA_SIZEOF
);
749 patch_pcivga(i
, pcihp
);
751 /* Nothing to do: system devices are in DSDT or in SSDT above. */
752 } else if (present
) {
753 void *pcihp
= acpi_data_push(bus_table
,
754 ACPI_PCINOHP_SIZEOF
);
755 memcpy(pcihp
, ACPI_PCINOHP_AML
, ACPI_PCINOHP_SIZEOF
);
756 patch_pcinohp(i
, pcihp
);
761 method
= build_alloc_method("DVNT", 2);
763 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
767 if (!test_bit(i
, slot_hotplug_enable
)) {
771 notify
= build_alloc_array();
772 op
= 0xA0; /* IfOp */
774 build_append_byte(notify
, 0x7B); /* AndOp */
775 build_append_byte(notify
, 0x68); /* Arg0Op */
776 build_append_int(notify
, 0x1U
<< i
);
777 build_append_byte(notify
, 0x00); /* NullName */
778 build_append_byte(notify
, 0x86); /* NotifyOp */
779 build_append_namestring(notify
, "S%.02X", PCI_DEVFN(i
, 0));
780 build_append_byte(notify
, 0x69); /* Arg1Op */
783 build_package(notify
, op
);
785 build_append_array(method
, notify
);
787 build_free_array(notify
);
790 build_append_and_cleanup_method(bus_table
, method
);
793 /* Append PCNT method to notify about events on local and child buses.
794 * Add unconditionally for root since DSDT expects it.
796 if (bus_hotplug_support
|| child
->notify_table
->len
|| !bus
->parent_dev
) {
797 method
= build_alloc_method("PCNT", 0);
799 /* If bus supports hotplug select it and notify about local events */
801 build_append_byte(method
, 0x70); /* StoreOp */
802 build_append_int(method
, qint_get_int(qobject_to_qint(bsel
)));
803 build_append_namestring(method
, "BNUM");
804 build_append_namestring(method
, "DVNT");
805 build_append_namestring(method
, "PCIU");
806 build_append_int(method
, 1); /* Device Check */
807 build_append_namestring(method
, "DVNT");
808 build_append_namestring(method
, "PCID");
809 build_append_int(method
, 3); /* Eject Request */
812 /* Notify about child bus events in any case */
813 build_append_array(method
, child
->notify_table
);
815 build_append_and_cleanup_method(bus_table
, method
);
817 /* Append description of child buses */
818 build_append_array(bus_table
, child
->device_table
);
821 if (bus
->parent_dev
) {
822 build_extop_package(bus_table
, op
);
824 build_package(bus_table
, op
);
827 /* Append our bus description to parent table */
828 build_append_array(parent
->device_table
, bus_table
);
830 /* Also tell parent how to notify us, invoking PCNT method.
831 * At the moment this is not needed for root as we have a single root.
833 if (bus
->parent_dev
) {
834 build_append_namestring(parent
->notify_table
, "^PCNT.S%.02X",
835 bus
->parent_dev
->devfn
);
839 qobject_decref(bsel
);
840 build_free_array(bus_table
);
841 build_pci_bus_state_cleanup(child
);
846 build_ssdt(GArray
*table_data
, GArray
*linker
,
847 AcpiCpuInfo
*cpu
, AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
848 PcPciInfo
*pci
, PcGuestInfo
*guest_info
)
850 MachineState
*machine
= MACHINE(qdev_get_machine());
851 uint32_t nr_mem
= machine
->ram_slots
;
852 unsigned acpi_cpus
= guest_info
->apic_id_limit
;
854 Aml
*ssdt
, *sb_scope
, *scope
, *pkg
, *dev
, *method
, *crs
, *field
, *ifctx
;
857 ssdt
= init_aml_allocator();
858 /* The current AML generator can cover the APIC ID range [0..255],
859 * inclusive, for VCPU hotplug. */
860 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT
> 256);
861 g_assert(acpi_cpus
<= ACPI_CPU_HOTPLUG_ID_LIMIT
);
863 /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
864 ssdt_ptr
= acpi_data_push(ssdt
->buf
, sizeof(ssdp_misc_aml
));
865 memcpy(ssdt_ptr
, ssdp_misc_aml
, sizeof(ssdp_misc_aml
));
867 scope
= aml_scope("\\_SB.PCI0");
868 /* build PCI0._CRS */
869 crs
= aml_resource_template();
871 aml_word_bus_number(aml_min_fixed
, aml_max_fixed
, aml_pos_decode
,
872 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
873 aml_append(crs
, aml_io(aml_decode16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
876 aml_word_io(aml_min_fixed
, aml_max_fixed
,
877 aml_pos_decode
, aml_entire_range
,
878 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
879 if (ich9_lpc_find()) { /* Q35 */
881 aml_word_io(aml_min_fixed
, aml_max_fixed
,
882 aml_pos_decode
, aml_entire_range
,
883 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
886 aml_word_io(aml_min_fixed
, aml_max_fixed
,
887 aml_pos_decode
, aml_entire_range
,
888 0x0000, 0x0D00, 0xADFF, 0x0000, 0xA100));
890 aml_word_io(aml_min_fixed
, aml_max_fixed
,
891 aml_pos_decode
, aml_entire_range
,
892 0x0000, 0xAE0F, 0xAEFF, 0x0000, 0x00F1));
894 aml_word_io(aml_min_fixed
, aml_max_fixed
,
895 aml_pos_decode
, aml_entire_range
,
896 0x0000, 0xAF20, 0xAFDF, 0x0000, 0x00C0));
898 aml_word_io(aml_min_fixed
, aml_max_fixed
,
899 aml_pos_decode
, aml_entire_range
,
900 0x0000, 0xAFE4, 0xFFFF, 0x0000, 0x501C));
903 aml_dword_memory(aml_pos_decode
, aml_min_fixed
, aml_max_fixed
,
904 aml_cacheable
, aml_ReadWrite
,
905 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
907 aml_dword_memory(aml_pos_decode
, aml_min_fixed
, aml_max_fixed
,
908 aml_non_cacheable
, aml_ReadWrite
,
909 0, pci
->w32
.begin
, pci
->w32
.end
- 1, 0,
910 pci
->w32
.end
- pci
->w32
.begin
));
911 if (pci
->w64
.begin
) {
913 aml_qword_memory(aml_pos_decode
, aml_min_fixed
, aml_max_fixed
,
914 aml_cacheable
, aml_ReadWrite
,
915 0, pci
->w64
.begin
, pci
->w64
.end
- 1, 0,
916 pci
->w64
.end
- pci
->w64
.begin
));
918 aml_append(scope
, aml_name_decl("_CRS", crs
));
920 /* reserve PCIHP resources */
921 if (pm
->pcihp_io_len
) {
922 dev
= aml_device("PHPR");
923 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
925 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
926 /* device present, functioning, decoding, not shown in UI */
927 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
928 crs
= aml_resource_template();
930 aml_io(aml_decode16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
933 aml_append(dev
, aml_name_decl("_CRS", crs
));
934 aml_append(scope
, dev
);
936 aml_append(ssdt
, scope
);
938 /* create S3_ / S4_ / S5_ packages if necessary */
939 scope
= aml_scope("\\");
940 if (!pm
->s3_disabled
) {
941 pkg
= aml_package(4);
942 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
943 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
944 aml_append(pkg
, aml_int(0)); /* reserved */
945 aml_append(pkg
, aml_int(0)); /* reserved */
946 aml_append(scope
, aml_name_decl("_S3", pkg
));
949 if (!pm
->s4_disabled
) {
950 pkg
= aml_package(4);
951 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
952 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
953 aml_append(pkg
, aml_int(pm
->s4_val
));
954 aml_append(pkg
, aml_int(0)); /* reserved */
955 aml_append(pkg
, aml_int(0)); /* reserved */
956 aml_append(scope
, aml_name_decl("_S4", pkg
));
959 pkg
= aml_package(4);
960 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
961 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
962 aml_append(pkg
, aml_int(0)); /* reserved */
963 aml_append(pkg
, aml_int(0)); /* reserved */
964 aml_append(scope
, aml_name_decl("_S5", pkg
));
965 aml_append(ssdt
, scope
);
967 if (misc
->pvpanic_port
) {
968 scope
= aml_scope("\\_SB.PCI0.ISA");
970 dev
= aml_device("PEVR");
971 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
973 crs
= aml_resource_template();
975 aml_io(aml_decode16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
977 aml_append(dev
, aml_name_decl("_CRS", crs
));
979 aml_append(dev
, aml_operation_region("PEOR", aml_system_io
,
980 misc
->pvpanic_port
, 1));
981 field
= aml_field("PEOR", aml_byte_acc
);
982 aml_append(field
, aml_named_field("PEPT", 8));
983 aml_append(dev
, field
);
985 method
= aml_method("RDPT", 0);
986 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
987 aml_append(method
, aml_return(aml_local(0)));
988 aml_append(dev
, method
);
990 method
= aml_method("WRPT", 1);
991 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
992 aml_append(dev
, method
);
994 aml_append(scope
, dev
);
995 aml_append(ssdt
, scope
);
998 sb_scope
= aml_scope("_SB");
1000 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1001 dev
= aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE
));
1002 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1004 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1006 /* device present, functioning, decoding, not shown in UI */
1007 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1008 crs
= aml_resource_template();
1010 aml_io(aml_decode16
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_base
, 1,
1013 aml_append(dev
, aml_name_decl("_CRS", crs
));
1014 aml_append(sb_scope
, dev
);
1015 /* declare CPU hotplug MMIO region and PRS field to access it */
1016 aml_append(sb_scope
, aml_operation_region(
1017 "PRST", aml_system_io
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_len
));
1018 field
= aml_field("PRST", aml_byte_acc
);
1019 aml_append(field
, aml_named_field("PRS", 256));
1020 aml_append(sb_scope
, field
);
1022 /* build Processor object for each processor */
1023 for (i
= 0; i
< acpi_cpus
; i
++) {
1024 dev
= aml_processor(i
, 0, 0, "CP%.02X", i
);
1026 method
= aml_method("_MAT", 0);
1027 aml_append(method
, aml_return(aml_call1("CPMA", aml_int(i
))));
1028 aml_append(dev
, method
);
1030 method
= aml_method("_STA", 0);
1031 aml_append(method
, aml_return(aml_call1("CPST", aml_int(i
))));
1032 aml_append(dev
, method
);
1034 method
= aml_method("_EJ0", 1);
1036 aml_return(aml_call2("CPEJ", aml_int(i
), aml_arg(0)))
1038 aml_append(dev
, method
);
1040 aml_append(sb_scope
, dev
);
1044 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1046 /* Arg0 = Processor ID = APIC ID */
1047 method
= aml_method("NTFY", 2);
1048 for (i
= 0; i
< acpi_cpus
; i
++) {
1049 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1051 aml_notify(aml_name("CP%.02X", i
), aml_arg(1))
1053 aml_append(method
, ifctx
);
1055 aml_append(sb_scope
, method
);
1057 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1059 * Note: The ability to create variable-sized packages was first
1060 * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1061 * ith up to 255 elements. Windows guests up to win2k8 fail when
1062 * VarPackageOp is used.
1064 pkg
= acpi_cpus
<= 255 ? aml_package(acpi_cpus
) :
1065 aml_varpackage(acpi_cpus
);
1067 for (i
= 0; i
< acpi_cpus
; i
++) {
1068 uint8_t b
= test_bit(i
, cpu
->found_cpus
) ? 0x01 : 0x00;
1069 aml_append(pkg
, aml_int(b
));
1071 aml_append(sb_scope
, aml_name_decl("CPON", pkg
));
1073 /* build memory devices */
1074 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
1075 scope
= aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE
));
1077 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER
), aml_int(nr_mem
))
1080 crs
= aml_resource_template();
1082 aml_io(aml_decode16
, pm
->mem_hp_io_base
, pm
->mem_hp_io_base
, 0,
1085 aml_append(scope
, aml_name_decl("_CRS", crs
));
1087 aml_append(scope
, aml_operation_region(
1088 stringify(MEMORY_HOTPLUG_IO_REGION
), aml_system_io
,
1089 pm
->mem_hp_io_base
, pm
->mem_hp_io_len
)
1092 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), aml_dword_acc
);
1093 aml_append(field
, /* read only */
1094 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW
), 32));
1095 aml_append(field
, /* read only */
1096 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH
), 32));
1097 aml_append(field
, /* read only */
1098 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW
), 32));
1099 aml_append(field
, /* read only */
1100 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH
), 32));
1101 aml_append(field
, /* read only */
1102 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY
), 32));
1103 aml_append(scope
, field
);
1105 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), aml_byte_acc
);
1106 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
1107 aml_append(field
, /* 1 if enabled, read only */
1108 aml_named_field(stringify(MEMORY_SLOT_ENABLED
), 1));
1110 /*(read) 1 if has a insert event. (write) 1 to clear event */
1111 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT
), 1));
1112 aml_append(scope
, field
);
1114 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), aml_dword_acc
);
1115 aml_append(field
, /* DIMM selector, write only */
1116 aml_named_field(stringify(MEMORY_SLOT_SLECTOR
), 32));
1117 aml_append(field
, /* _OST event code, write only */
1118 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT
), 32));
1119 aml_append(field
, /* _OST status code, write only */
1120 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS
), 32));
1121 aml_append(scope
, field
);
1123 aml_append(sb_scope
, scope
);
1125 for (i
= 0; i
< nr_mem
; i
++) {
1126 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1129 dev
= aml_device("MP%02X", i
);
1130 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1131 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1133 method
= aml_method("_CRS", 0);
1134 s
= BASEPATH
stringify(MEMORY_SLOT_CRS_METHOD
);
1135 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1136 aml_append(dev
, method
);
1138 method
= aml_method("_STA", 0);
1139 s
= BASEPATH
stringify(MEMORY_SLOT_STATUS_METHOD
);
1140 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1141 aml_append(dev
, method
);
1143 method
= aml_method("_PXM", 0);
1144 s
= BASEPATH
stringify(MEMORY_SLOT_PROXIMITY_METHOD
);
1145 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1146 aml_append(dev
, method
);
1148 method
= aml_method("_OST", 3);
1149 s
= BASEPATH
stringify(MEMORY_SLOT_OST_METHOD
);
1150 aml_append(method
, aml_return(aml_call4(
1151 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1153 aml_append(dev
, method
);
1155 aml_append(sb_scope
, dev
);
1158 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1159 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ...
1161 method
= aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD
), 2);
1162 for (i
= 0; i
< nr_mem
; i
++) {
1163 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1165 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1167 aml_append(method
, ifctx
);
1169 aml_append(sb_scope
, method
);
1172 AcpiBuildPciBusHotplugState hotplug_state
;
1177 pci_host
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
1178 if (!ambiguous
&& pci_host
) {
1179 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
1182 build_pci_bus_state_init(&hotplug_state
, NULL
, pm
->pcihp_bridge_en
);
1185 /* Scan all PCI buses. Generate tables to support hotplug. */
1186 pci_for_each_bus_depth_first(bus
, build_pci_bus_begin
,
1187 build_pci_bus_end
, &hotplug_state
);
1190 build_append_array(sb_scope
->buf
, hotplug_state
.device_table
);
1191 build_pci_bus_state_cleanup(&hotplug_state
);
1193 aml_append(ssdt
, sb_scope
);
1196 /* copy AML table into ACPI tables blob and patch header there */
1197 g_array_append_vals(table_data
, ssdt
->buf
->data
, ssdt
->buf
->len
);
1198 build_header(linker
, table_data
,
1199 (void *)(table_data
->data
+ table_data
->len
- ssdt
->buf
->len
),
1200 "SSDT", ssdt
->buf
->len
, 1);
1201 free_aml_allocator();
1205 build_hpet(GArray
*table_data
, GArray
*linker
)
1209 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
1210 /* Note timer_block_id value must be kept in sync with value advertised by
1213 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
1214 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
1215 build_header(linker
, table_data
,
1216 (void *)hpet
, "HPET", sizeof(*hpet
), 1);
1220 build_tpm_tcpa(GArray
*table_data
, GArray
*linker
, GArray
*tcpalog
)
1222 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
1223 uint64_t log_area_start_address
= acpi_data_len(tcpalog
);
1225 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
1226 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
1227 tcpa
->log_area_start_address
= cpu_to_le64(log_area_start_address
);
1229 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, 1,
1230 false /* high memory */);
1232 /* log area start address to be filled by Guest linker */
1233 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
1234 ACPI_BUILD_TPMLOG_FILE
,
1235 table_data
, &tcpa
->log_area_start_address
,
1236 sizeof(tcpa
->log_area_start_address
));
1238 build_header(linker
, table_data
,
1239 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2);
1241 acpi_data_push(tcpalog
, TPM_LOG_AREA_MINIMUM_SIZE
);
1245 build_tpm_ssdt(GArray
*table_data
, GArray
*linker
)
1249 tpm_ptr
= acpi_data_push(table_data
, sizeof(ssdt_tpm_aml
));
1250 memcpy(tpm_ptr
, ssdt_tpm_aml
, sizeof(ssdt_tpm_aml
));
1254 MEM_AFFINITY_NOFLAGS
= 0,
1255 MEM_AFFINITY_ENABLED
= (1 << 0),
1256 MEM_AFFINITY_HOTPLUGGABLE
= (1 << 1),
1257 MEM_AFFINITY_NON_VOLATILE
= (1 << 2),
1258 } MemoryAffinityFlags
;
1261 acpi_build_srat_memory(AcpiSratMemoryAffinity
*numamem
, uint64_t base
,
1262 uint64_t len
, int node
, MemoryAffinityFlags flags
)
1264 numamem
->type
= ACPI_SRAT_MEMORY
;
1265 numamem
->length
= sizeof(*numamem
);
1266 memset(numamem
->proximity
, 0, 4);
1267 numamem
->proximity
[0] = node
;
1268 numamem
->flags
= cpu_to_le32(flags
);
1269 numamem
->base_addr
= cpu_to_le64(base
);
1270 numamem
->range_length
= cpu_to_le64(len
);
1274 build_srat(GArray
*table_data
, GArray
*linker
, PcGuestInfo
*guest_info
)
1276 AcpiSystemResourceAffinityTable
*srat
;
1277 AcpiSratProcessorAffinity
*core
;
1278 AcpiSratMemoryAffinity
*numamem
;
1282 int srat_start
, numa_start
, slots
;
1283 uint64_t mem_len
, mem_base
, next_base
;
1284 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1285 ram_addr_t hotplugabble_address_space_size
=
1286 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
1289 srat_start
= table_data
->len
;
1291 srat
= acpi_data_push(table_data
, sizeof *srat
);
1292 srat
->reserved1
= cpu_to_le32(1);
1293 core
= (void *)(srat
+ 1);
1295 for (i
= 0; i
< guest_info
->apic_id_limit
; ++i
) {
1296 core
= acpi_data_push(table_data
, sizeof *core
);
1297 core
->type
= ACPI_SRAT_PROCESSOR
;
1298 core
->length
= sizeof(*core
);
1299 core
->local_apic_id
= i
;
1300 curnode
= guest_info
->node_cpu
[i
];
1301 core
->proximity_lo
= curnode
;
1302 memset(core
->proximity_hi
, 0, 3);
1303 core
->local_sapic_eid
= 0;
1304 core
->flags
= cpu_to_le32(1);
1308 /* the memory map is a bit tricky, it contains at least one hole
1309 * from 640k-1M and possibly another one from 3.5G-4G.
1312 numa_start
= table_data
->len
;
1314 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1315 acpi_build_srat_memory(numamem
, 0, 640*1024, 0, MEM_AFFINITY_ENABLED
);
1316 next_base
= 1024 * 1024;
1317 for (i
= 1; i
< guest_info
->numa_nodes
+ 1; ++i
) {
1318 mem_base
= next_base
;
1319 mem_len
= guest_info
->node_mem
[i
- 1];
1321 mem_len
-= 1024 * 1024;
1323 next_base
= mem_base
+ mem_len
;
1325 /* Cut out the ACPI_PCI hole */
1326 if (mem_base
<= guest_info
->ram_size_below_4g
&&
1327 next_base
> guest_info
->ram_size_below_4g
) {
1328 mem_len
-= next_base
- guest_info
->ram_size_below_4g
;
1330 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1331 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1332 MEM_AFFINITY_ENABLED
);
1334 mem_base
= 1ULL << 32;
1335 mem_len
= next_base
- guest_info
->ram_size_below_4g
;
1336 next_base
+= (1ULL << 32) - guest_info
->ram_size_below_4g
;
1338 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1339 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1340 MEM_AFFINITY_ENABLED
);
1342 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
1343 for (; slots
< guest_info
->numa_nodes
+ 2; slots
++) {
1344 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1345 acpi_build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
1349 * Entry is required for Windows to enable memory hotplug in OS.
1350 * Memory devices may override proximity set by this entry,
1351 * providing _PXM method if necessary.
1353 if (hotplugabble_address_space_size
) {
1354 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1355 acpi_build_srat_memory(numamem
, pcms
->hotplug_memory_base
,
1356 hotplugabble_address_space_size
, 0,
1357 MEM_AFFINITY_HOTPLUGGABLE
|
1358 MEM_AFFINITY_ENABLED
);
1361 build_header(linker
, table_data
,
1362 (void *)(table_data
->data
+ srat_start
),
1364 table_data
->len
- srat_start
, 1);
1368 build_mcfg_q35(GArray
*table_data
, GArray
*linker
, AcpiMcfgInfo
*info
)
1370 AcpiTableMcfg
*mcfg
;
1372 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
1374 mcfg
= acpi_data_push(table_data
, len
);
1375 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
1376 /* Only a single allocation so no need to play with segments */
1377 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
1378 mcfg
->allocation
[0].start_bus_number
= 0;
1379 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
1381 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1382 * To avoid table size changes (which create migration issues),
1383 * always create the table even if there are no allocations,
1384 * but set the signature to a reserved value in this case.
1385 * ACPI spec requires OSPMs to ignore such tables.
1387 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
1388 /* Reserved signature: ignored by OSPM */
1393 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1);
1397 build_dmar_q35(GArray
*table_data
, GArray
*linker
)
1399 int dmar_start
= table_data
->len
;
1401 AcpiTableDmar
*dmar
;
1402 AcpiDmarHardwareUnit
*drhd
;
1404 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
1405 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
1406 dmar
->flags
= 0; /* No intr_remap for now */
1408 /* DMAR Remapping Hardware Unit Definition structure */
1409 drhd
= acpi_data_push(table_data
, sizeof(*drhd
));
1410 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
1411 drhd
->length
= cpu_to_le16(sizeof(*drhd
)); /* No device scope now */
1412 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
1413 drhd
->pci_segment
= cpu_to_le16(0);
1414 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
1416 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
1417 "DMAR", table_data
->len
- dmar_start
, 1);
1421 build_dsdt(GArray
*table_data
, GArray
*linker
, AcpiMiscInfo
*misc
)
1423 AcpiTableHeader
*dsdt
;
1425 assert(misc
->dsdt_code
&& misc
->dsdt_size
);
1427 dsdt
= acpi_data_push(table_data
, misc
->dsdt_size
);
1428 memcpy(dsdt
, misc
->dsdt_code
, misc
->dsdt_size
);
1430 memset(dsdt
, 0, sizeof *dsdt
);
1431 build_header(linker
, table_data
, dsdt
, "DSDT",
1432 misc
->dsdt_size
, 1);
1435 /* Build final rsdt table */
1437 build_rsdt(GArray
*table_data
, GArray
*linker
, GArray
*table_offsets
)
1439 AcpiRsdtDescriptorRev1
*rsdt
;
1443 rsdt_len
= sizeof(*rsdt
) + sizeof(uint32_t) * table_offsets
->len
;
1444 rsdt
= acpi_data_push(table_data
, rsdt_len
);
1445 memcpy(rsdt
->table_offset_entry
, table_offsets
->data
,
1446 sizeof(uint32_t) * table_offsets
->len
);
1447 for (i
= 0; i
< table_offsets
->len
; ++i
) {
1448 /* rsdt->table_offset_entry to be filled by Guest linker */
1449 bios_linker_loader_add_pointer(linker
,
1450 ACPI_BUILD_TABLE_FILE
,
1451 ACPI_BUILD_TABLE_FILE
,
1452 table_data
, &rsdt
->table_offset_entry
[i
],
1455 build_header(linker
, table_data
,
1456 (void *)rsdt
, "RSDT", rsdt_len
, 1);
1460 build_rsdp(GArray
*rsdp_table
, GArray
*linker
, unsigned rsdt
)
1462 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
1464 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, 16,
1465 true /* fseg memory */);
1467 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
1468 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
1469 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt
);
1470 /* Address to be filled by Guest linker */
1471 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_RSDP_FILE
,
1472 ACPI_BUILD_TABLE_FILE
,
1473 rsdp_table
, &rsdp
->rsdt_physical_address
,
1474 sizeof rsdp
->rsdt_physical_address
);
1476 /* Checksum to be filled by Guest linker */
1477 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
1478 rsdp
, rsdp
, sizeof *rsdp
, &rsdp
->checksum
);
1484 struct AcpiBuildTables
{
1491 static inline void acpi_build_tables_init(AcpiBuildTables
*tables
)
1493 tables
->rsdp
= g_array_new(false, true /* clear */, 1);
1494 tables
->table_data
= g_array_new(false, true /* clear */, 1);
1495 tables
->tcpalog
= g_array_new(false, true /* clear */, 1);
1496 tables
->linker
= bios_linker_loader_init();
1499 static inline void acpi_build_tables_cleanup(AcpiBuildTables
*tables
, bool mfre
)
1501 void *linker_data
= bios_linker_loader_cleanup(tables
->linker
);
1502 g_free(linker_data
);
1503 g_array_free(tables
->rsdp
, true);
1504 g_array_free(tables
->table_data
, true);
1505 g_array_free(tables
->tcpalog
, mfre
);
1509 struct AcpiBuildState
{
1510 /* Copy of table in RAM (for patching). */
1511 ram_addr_t table_ram
;
1512 /* Is table patched? */
1514 PcGuestInfo
*guest_info
;
1516 ram_addr_t rsdp_ram
;
1517 ram_addr_t linker_ram
;
1520 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
1526 pci_host
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
1527 g_assert(!ambiguous
);
1530 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
1534 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
1537 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
1539 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
1544 static bool acpi_has_iommu(void)
1547 Object
*intel_iommu
;
1549 intel_iommu
= object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE
,
1551 return intel_iommu
&& !ambiguous
;
1555 void acpi_build(PcGuestInfo
*guest_info
, AcpiBuildTables
*tables
)
1557 GArray
*table_offsets
;
1558 unsigned facs
, ssdt
, dsdt
, rsdt
;
1566 GArray
*tables_blob
= tables
->table_data
;
1568 acpi_get_cpu_info(&cpu
);
1569 acpi_get_pm_info(&pm
);
1570 acpi_get_dsdt(&misc
);
1571 acpi_get_misc_info(&misc
);
1572 acpi_get_pci_info(&pci
);
1574 table_offsets
= g_array_new(false, true /* clear */,
1576 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1578 bios_linker_loader_alloc(tables
->linker
, ACPI_BUILD_TABLE_FILE
,
1579 64 /* Ensure FACS is aligned */,
1580 false /* high memory */);
1583 * FACS is pointed to by FADT.
1584 * We place it first since it's the only table that has alignment
1587 facs
= tables_blob
->len
;
1588 build_facs(tables_blob
, tables
->linker
, guest_info
);
1590 /* DSDT is pointed to by FADT */
1591 dsdt
= tables_blob
->len
;
1592 build_dsdt(tables_blob
, tables
->linker
, &misc
);
1594 /* Count the size of the DSDT and SSDT, we will need it for legacy
1595 * sizing of ACPI tables.
1597 aml_len
+= tables_blob
->len
- dsdt
;
1599 /* ACPI tables pointed to by RSDT */
1600 acpi_add_table(table_offsets
, tables_blob
);
1601 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
);
1603 ssdt
= tables_blob
->len
;
1604 acpi_add_table(table_offsets
, tables_blob
);
1605 build_ssdt(tables_blob
, tables
->linker
, &cpu
, &pm
, &misc
, &pci
,
1607 aml_len
+= tables_blob
->len
- ssdt
;
1609 acpi_add_table(table_offsets
, tables_blob
);
1610 build_madt(tables_blob
, tables
->linker
, &cpu
, guest_info
);
1612 if (misc
.has_hpet
) {
1613 acpi_add_table(table_offsets
, tables_blob
);
1614 build_hpet(tables_blob
, tables
->linker
);
1617 acpi_add_table(table_offsets
, tables_blob
);
1618 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
1620 acpi_add_table(table_offsets
, tables_blob
);
1621 build_tpm_ssdt(tables_blob
, tables
->linker
);
1623 if (guest_info
->numa_nodes
) {
1624 acpi_add_table(table_offsets
, tables_blob
);
1625 build_srat(tables_blob
, tables
->linker
, guest_info
);
1627 if (acpi_get_mcfg(&mcfg
)) {
1628 acpi_add_table(table_offsets
, tables_blob
);
1629 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
1631 if (acpi_has_iommu()) {
1632 acpi_add_table(table_offsets
, tables_blob
);
1633 build_dmar_q35(tables_blob
, tables
->linker
);
1636 /* Add tables supplied by user (if any) */
1637 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
1638 unsigned len
= acpi_table_len(u
);
1640 acpi_add_table(table_offsets
, tables_blob
);
1641 g_array_append_vals(tables_blob
, u
, len
);
1644 /* RSDT is pointed to by RSDP */
1645 rsdt
= tables_blob
->len
;
1646 build_rsdt(tables_blob
, tables
->linker
, table_offsets
);
1648 /* RSDP is in FSEG memory, so allocate it separately */
1649 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
1651 /* We'll expose it all to Guest so we want to reduce
1652 * chance of size changes.
1654 * We used to align the tables to 4k, but of course this would
1655 * too simple to be enough. 4k turned out to be too small an
1656 * alignment very soon, and in fact it is almost impossible to
1657 * keep the table size stable for all (max_cpus, max_memory_slots)
1658 * combinations. So the table size is always 64k for pc-i440fx-2.1
1659 * and we give an error if the table grows beyond that limit.
1661 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1662 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1663 * than 2.0 and we can always pad the smaller tables with zeros. We can
1664 * then use the exact size of the 2.0 tables.
1666 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1668 if (guest_info
->legacy_acpi_table_size
) {
1669 /* Subtracting aml_len gives the size of fixed tables. Then add the
1670 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1672 int legacy_aml_len
=
1673 guest_info
->legacy_acpi_table_size
+
1674 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
1675 int legacy_table_size
=
1676 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
1677 ACPI_BUILD_ALIGN_SIZE
);
1678 if (tables_blob
->len
> legacy_table_size
) {
1679 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1680 error_report("Warning: migration may not work.");
1682 g_array_set_size(tables_blob
, legacy_table_size
);
1684 /* Make sure we have a buffer in case we need to resize the tables. */
1685 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
1686 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1687 error_report("Warning: ACPI tables are larger than 64k.");
1688 error_report("Warning: migration may not work.");
1689 error_report("Warning: please remove CPUs, NUMA nodes, "
1690 "memory slots or PCI bridges.");
1692 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
1695 acpi_align_size(tables
->linker
, ACPI_BUILD_ALIGN_SIZE
);
1697 /* Cleanup memory that's no longer used. */
1698 g_array_free(table_offsets
, true);
1701 static void acpi_ram_update(ram_addr_t ram
, GArray
*data
)
1703 uint32_t size
= acpi_data_len(data
);
1705 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1706 qemu_ram_resize(ram
, size
, &error_abort
);
1708 memcpy(qemu_get_ram_ptr(ram
), data
->data
, size
);
1709 cpu_physical_memory_set_dirty_range_nocode(ram
, size
);
1712 static void acpi_build_update(void *build_opaque
, uint32_t offset
)
1714 AcpiBuildState
*build_state
= build_opaque
;
1715 AcpiBuildTables tables
;
1717 /* No state to update or already patched? Nothing to do. */
1718 if (!build_state
|| build_state
->patched
) {
1721 build_state
->patched
= 1;
1723 acpi_build_tables_init(&tables
);
1725 acpi_build(build_state
->guest_info
, &tables
);
1727 acpi_ram_update(build_state
->table_ram
, tables
.table_data
);
1729 if (build_state
->rsdp
) {
1730 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
1732 acpi_ram_update(build_state
->rsdp_ram
, tables
.rsdp
);
1735 acpi_ram_update(build_state
->linker_ram
, tables
.linker
);
1736 acpi_build_tables_cleanup(&tables
, true);
1739 static void acpi_build_reset(void *build_opaque
)
1741 AcpiBuildState
*build_state
= build_opaque
;
1742 build_state
->patched
= 0;
1745 static ram_addr_t
acpi_add_rom_blob(AcpiBuildState
*build_state
, GArray
*blob
,
1746 const char *name
, uint64_t max_size
)
1748 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
1749 name
, acpi_build_update
, build_state
);
1752 static const VMStateDescription vmstate_acpi_build
= {
1753 .name
= "acpi_build",
1755 .minimum_version_id
= 1,
1756 .fields
= (VMStateField
[]) {
1757 VMSTATE_UINT8(patched
, AcpiBuildState
),
1758 VMSTATE_END_OF_LIST()
1762 void acpi_setup(PcGuestInfo
*guest_info
)
1764 AcpiBuildTables tables
;
1765 AcpiBuildState
*build_state
;
1767 if (!guest_info
->fw_cfg
) {
1768 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1772 if (!guest_info
->has_acpi_build
) {
1773 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1777 if (!acpi_enabled
) {
1778 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1782 build_state
= g_malloc0(sizeof *build_state
);
1784 build_state
->guest_info
= guest_info
;
1786 acpi_set_pci_info();
1788 acpi_build_tables_init(&tables
);
1789 acpi_build(build_state
->guest_info
, &tables
);
1791 /* Now expose it all to Guest */
1792 build_state
->table_ram
= acpi_add_rom_blob(build_state
, tables
.table_data
,
1793 ACPI_BUILD_TABLE_FILE
,
1794 ACPI_BUILD_TABLE_MAX_SIZE
);
1795 assert(build_state
->table_ram
!= RAM_ADDR_MAX
);
1797 build_state
->linker_ram
=
1798 acpi_add_rom_blob(build_state
, tables
.linker
, "etc/table-loader", 0);
1800 fw_cfg_add_file(guest_info
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
1801 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
1803 if (!guest_info
->rsdp_in_ram
) {
1805 * Keep for compatibility with old machine types.
1806 * Though RSDP is small, its contents isn't immutable, so
1807 * we'll update it along with the rest of tables on guest access.
1809 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
1811 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
1812 fw_cfg_add_file_callback(guest_info
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
1813 acpi_build_update
, build_state
,
1814 build_state
->rsdp
, rsdp_size
);
1815 build_state
->rsdp_ram
= (ram_addr_t
)-1;
1817 build_state
->rsdp
= NULL
;
1818 build_state
->rsdp_ram
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
1819 ACPI_BUILD_RSDP_FILE
, 0);
1822 qemu_register_reset(acpi_build_reset
, build_state
);
1823 acpi_build_reset(build_state
);
1824 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
1826 /* Cleanup tables but don't free the memory: we track it
1829 acpi_build_tables_cleanup(&tables
, false);