4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "exec/cpu_ldst.h"
25 #ifndef CONFIG_USER_ONLY
27 void superh_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
28 MMUAccessType access_type
,
29 int mmu_idx
, uintptr_t retaddr
)
31 switch (access_type
) {
34 cs
->exception_index
= 0x0e0;
37 cs
->exception_index
= 0x100;
40 cpu_loop_exit_restore(cs
, retaddr
);
43 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
44 int mmu_idx
, uintptr_t retaddr
)
48 ret
= superh_cpu_handle_mmu_fault(cs
, addr
, access_type
, mmu_idx
);
50 /* now we have a real cpu fault */
51 cpu_loop_exit_restore(cs
, retaddr
);
57 void helper_ldtlb(CPUSH4State
*env
)
59 #ifdef CONFIG_USER_ONLY
60 SuperHCPU
*cpu
= sh_env_get_cpu(env
);
63 cpu_abort(CPU(cpu
), "Unhandled ldtlb");
69 static inline void QEMU_NORETURN
raise_exception(CPUSH4State
*env
, int index
,
72 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
74 cs
->exception_index
= index
;
75 cpu_loop_exit_restore(cs
, retaddr
);
78 void helper_raise_illegal_instruction(CPUSH4State
*env
)
80 raise_exception(env
, 0x180, 0);
83 void helper_raise_slot_illegal_instruction(CPUSH4State
*env
)
85 raise_exception(env
, 0x1a0, 0);
88 void helper_raise_fpu_disable(CPUSH4State
*env
)
90 raise_exception(env
, 0x800, 0);
93 void helper_raise_slot_fpu_disable(CPUSH4State
*env
)
95 raise_exception(env
, 0x820, 0);
98 void helper_debug(CPUSH4State
*env
)
100 raise_exception(env
, EXCP_DEBUG
, 0);
103 void helper_sleep(CPUSH4State
*env
)
105 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
109 raise_exception(env
, EXCP_HLT
, 0);
112 void helper_trapa(CPUSH4State
*env
, uint32_t tra
)
115 raise_exception(env
, 0x160, 0);
118 void helper_movcal(CPUSH4State
*env
, uint32_t address
, uint32_t value
)
120 if (cpu_sh4_is_cached (env
, address
))
122 memory_content
*r
= g_new(memory_content
, 1);
124 r
->address
= address
;
128 *(env
->movcal_backup_tail
) = r
;
129 env
->movcal_backup_tail
= &(r
->next
);
133 void helper_discard_movcal_backup(CPUSH4State
*env
)
135 memory_content
*current
= env
->movcal_backup
;
139 memory_content
*next
= current
->next
;
141 env
->movcal_backup
= current
= next
;
143 env
->movcal_backup_tail
= &(env
->movcal_backup
);
147 void helper_ocbi(CPUSH4State
*env
, uint32_t address
)
149 memory_content
**current
= &(env
->movcal_backup
);
152 uint32_t a
= (*current
)->address
;
153 if ((a
& ~0x1F) == (address
& ~0x1F))
155 memory_content
*next
= (*current
)->next
;
156 cpu_stl_data(env
, a
, (*current
)->value
);
160 env
->movcal_backup_tail
= current
;
170 void helper_macl(CPUSH4State
*env
, uint32_t arg0
, uint32_t arg1
)
174 res
= ((uint64_t) env
->mach
<< 32) | env
->macl
;
175 res
+= (int64_t) (int32_t) arg0
*(int64_t) (int32_t) arg1
;
176 env
->mach
= (res
>> 32) & 0xffffffff;
177 env
->macl
= res
& 0xffffffff;
178 if (env
->sr
& (1u << SR_S
)) {
180 env
->mach
|= 0xffff0000;
182 env
->mach
&= 0x00007fff;
186 void helper_macw(CPUSH4State
*env
, uint32_t arg0
, uint32_t arg1
)
190 res
= ((uint64_t) env
->mach
<< 32) | env
->macl
;
191 res
+= (int64_t) (int16_t) arg0
*(int64_t) (int16_t) arg1
;
192 env
->mach
= (res
>> 32) & 0xffffffff;
193 env
->macl
= res
& 0xffffffff;
194 if (env
->sr
& (1u << SR_S
)) {
195 if (res
< -0x80000000) {
197 env
->macl
= 0x80000000;
198 } else if (res
> 0x000000007fffffff) {
200 env
->macl
= 0x7fffffff;
205 void helper_ld_fpscr(CPUSH4State
*env
, uint32_t val
)
207 env
->fpscr
= val
& FPSCR_MASK
;
208 if ((val
& FPSCR_RM_MASK
) == FPSCR_RM_ZERO
) {
209 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
211 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
213 set_flush_to_zero((val
& FPSCR_DN
) != 0, &env
->fp_status
);
216 static void update_fpscr(CPUSH4State
*env
, uintptr_t retaddr
)
218 int xcpt
, cause
, enable
;
220 xcpt
= get_float_exception_flags(&env
->fp_status
);
222 /* Clear the flag entries */
223 env
->fpscr
&= ~FPSCR_FLAG_MASK
;
225 if (unlikely(xcpt
)) {
226 if (xcpt
& float_flag_invalid
) {
227 env
->fpscr
|= FPSCR_FLAG_V
;
229 if (xcpt
& float_flag_divbyzero
) {
230 env
->fpscr
|= FPSCR_FLAG_Z
;
232 if (xcpt
& float_flag_overflow
) {
233 env
->fpscr
|= FPSCR_FLAG_O
;
235 if (xcpt
& float_flag_underflow
) {
236 env
->fpscr
|= FPSCR_FLAG_U
;
238 if (xcpt
& float_flag_inexact
) {
239 env
->fpscr
|= FPSCR_FLAG_I
;
242 /* Accumulate in cause entries */
243 env
->fpscr
|= (env
->fpscr
& FPSCR_FLAG_MASK
)
244 << (FPSCR_CAUSE_SHIFT
- FPSCR_FLAG_SHIFT
);
246 /* Generate an exception if enabled */
247 cause
= (env
->fpscr
& FPSCR_CAUSE_MASK
) >> FPSCR_CAUSE_SHIFT
;
248 enable
= (env
->fpscr
& FPSCR_ENABLE_MASK
) >> FPSCR_ENABLE_SHIFT
;
249 if (cause
& enable
) {
250 raise_exception(env
, 0x120, retaddr
);
255 float32
helper_fabs_FT(float32 t0
)
257 return float32_abs(t0
);
260 float64
helper_fabs_DT(float64 t0
)
262 return float64_abs(t0
);
265 float32
helper_fadd_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
267 set_float_exception_flags(0, &env
->fp_status
);
268 t0
= float32_add(t0
, t1
, &env
->fp_status
);
269 update_fpscr(env
, GETPC());
273 float64
helper_fadd_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
275 set_float_exception_flags(0, &env
->fp_status
);
276 t0
= float64_add(t0
, t1
, &env
->fp_status
);
277 update_fpscr(env
, GETPC());
281 void helper_fcmp_eq_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
285 set_float_exception_flags(0, &env
->fp_status
);
286 relation
= float32_compare(t0
, t1
, &env
->fp_status
);
287 if (unlikely(relation
== float_relation_unordered
)) {
288 update_fpscr(env
, GETPC());
290 env
->sr_t
= (relation
== float_relation_equal
);
294 void helper_fcmp_eq_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
298 set_float_exception_flags(0, &env
->fp_status
);
299 relation
= float64_compare(t0
, t1
, &env
->fp_status
);
300 if (unlikely(relation
== float_relation_unordered
)) {
301 update_fpscr(env
, GETPC());
303 env
->sr_t
= (relation
== float_relation_equal
);
307 void helper_fcmp_gt_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
311 set_float_exception_flags(0, &env
->fp_status
);
312 relation
= float32_compare(t0
, t1
, &env
->fp_status
);
313 if (unlikely(relation
== float_relation_unordered
)) {
314 update_fpscr(env
, GETPC());
316 env
->sr_t
= (relation
== float_relation_greater
);
320 void helper_fcmp_gt_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
324 set_float_exception_flags(0, &env
->fp_status
);
325 relation
= float64_compare(t0
, t1
, &env
->fp_status
);
326 if (unlikely(relation
== float_relation_unordered
)) {
327 update_fpscr(env
, GETPC());
329 env
->sr_t
= (relation
== float_relation_greater
);
333 float64
helper_fcnvsd_FT_DT(CPUSH4State
*env
, float32 t0
)
336 set_float_exception_flags(0, &env
->fp_status
);
337 ret
= float32_to_float64(t0
, &env
->fp_status
);
338 update_fpscr(env
, GETPC());
342 float32
helper_fcnvds_DT_FT(CPUSH4State
*env
, float64 t0
)
345 set_float_exception_flags(0, &env
->fp_status
);
346 ret
= float64_to_float32(t0
, &env
->fp_status
);
347 update_fpscr(env
, GETPC());
351 float32
helper_fdiv_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
353 set_float_exception_flags(0, &env
->fp_status
);
354 t0
= float32_div(t0
, t1
, &env
->fp_status
);
355 update_fpscr(env
, GETPC());
359 float64
helper_fdiv_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
361 set_float_exception_flags(0, &env
->fp_status
);
362 t0
= float64_div(t0
, t1
, &env
->fp_status
);
363 update_fpscr(env
, GETPC());
367 float32
helper_float_FT(CPUSH4State
*env
, uint32_t t0
)
370 set_float_exception_flags(0, &env
->fp_status
);
371 ret
= int32_to_float32(t0
, &env
->fp_status
);
372 update_fpscr(env
, GETPC());
376 float64
helper_float_DT(CPUSH4State
*env
, uint32_t t0
)
379 set_float_exception_flags(0, &env
->fp_status
);
380 ret
= int32_to_float64(t0
, &env
->fp_status
);
381 update_fpscr(env
, GETPC());
385 float32
helper_fmac_FT(CPUSH4State
*env
, float32 t0
, float32 t1
, float32 t2
)
387 set_float_exception_flags(0, &env
->fp_status
);
388 t0
= float32_muladd(t0
, t1
, t2
, 0, &env
->fp_status
);
389 update_fpscr(env
, GETPC());
393 float32
helper_fmul_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
395 set_float_exception_flags(0, &env
->fp_status
);
396 t0
= float32_mul(t0
, t1
, &env
->fp_status
);
397 update_fpscr(env
, GETPC());
401 float64
helper_fmul_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
403 set_float_exception_flags(0, &env
->fp_status
);
404 t0
= float64_mul(t0
, t1
, &env
->fp_status
);
405 update_fpscr(env
, GETPC());
409 float32
helper_fneg_T(float32 t0
)
411 return float32_chs(t0
);
414 float32
helper_fsqrt_FT(CPUSH4State
*env
, float32 t0
)
416 set_float_exception_flags(0, &env
->fp_status
);
417 t0
= float32_sqrt(t0
, &env
->fp_status
);
418 update_fpscr(env
, GETPC());
422 float64
helper_fsqrt_DT(CPUSH4State
*env
, float64 t0
)
424 set_float_exception_flags(0, &env
->fp_status
);
425 t0
= float64_sqrt(t0
, &env
->fp_status
);
426 update_fpscr(env
, GETPC());
430 float32
helper_fsub_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
432 set_float_exception_flags(0, &env
->fp_status
);
433 t0
= float32_sub(t0
, t1
, &env
->fp_status
);
434 update_fpscr(env
, GETPC());
438 float64
helper_fsub_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
440 set_float_exception_flags(0, &env
->fp_status
);
441 t0
= float64_sub(t0
, t1
, &env
->fp_status
);
442 update_fpscr(env
, GETPC());
446 uint32_t helper_ftrc_FT(CPUSH4State
*env
, float32 t0
)
449 set_float_exception_flags(0, &env
->fp_status
);
450 ret
= float32_to_int32_round_to_zero(t0
, &env
->fp_status
);
451 update_fpscr(env
, GETPC());
455 uint32_t helper_ftrc_DT(CPUSH4State
*env
, float64 t0
)
458 set_float_exception_flags(0, &env
->fp_status
);
459 ret
= float64_to_int32_round_to_zero(t0
, &env
->fp_status
);
460 update_fpscr(env
, GETPC());
464 void helper_fipr(CPUSH4State
*env
, uint32_t m
, uint32_t n
)
469 bank
= (env
->sr
& FPSCR_FR
) ? 16 : 0;
471 set_float_exception_flags(0, &env
->fp_status
);
473 for (i
= 0 ; i
< 4 ; i
++) {
474 p
= float32_mul(env
->fregs
[bank
+ m
+ i
],
475 env
->fregs
[bank
+ n
+ i
],
477 r
= float32_add(r
, p
, &env
->fp_status
);
479 update_fpscr(env
, GETPC());
481 env
->fregs
[bank
+ n
+ 3] = r
;
484 void helper_ftrv(CPUSH4State
*env
, uint32_t n
)
486 int bank_matrix
, bank_vector
;
491 bank_matrix
= (env
->sr
& FPSCR_FR
) ? 0 : 16;
492 bank_vector
= (env
->sr
& FPSCR_FR
) ? 16 : 0;
493 set_float_exception_flags(0, &env
->fp_status
);
494 for (i
= 0 ; i
< 4 ; i
++) {
496 for (j
= 0 ; j
< 4 ; j
++) {
497 p
= float32_mul(env
->fregs
[bank_matrix
+ 4 * j
+ i
],
498 env
->fregs
[bank_vector
+ j
],
500 r
[i
] = float32_add(r
[i
], p
, &env
->fp_status
);
503 update_fpscr(env
, GETPC());
505 for (i
= 0 ; i
< 4 ; i
++) {
506 env
->fregs
[bank_vector
+ i
] = r
[i
];