hw/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on piix_pci.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/q35.h"
  32
  33 /****************************************************************************
  34  * Q35 host
  35  */
  36
  37 static int q35_host_init(SysBusDevice *dev)
  38 {
  39     PCIBus *b;
  40     PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
  41     Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
  42
  43     memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
  44                           "pci-conf-idx", 4);
  45     sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  46     sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  47
  48     memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
  49                           "pci-conf-data", 4);
  50     sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  51     sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  52
  53     if (pcie_host_init(&s->host) < 0) {
  54         return -1;
  55     }
  56     b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
  57                     s->mch.pci_address_space, s->mch.address_space_io,
  58                     0, TYPE_PCI_BUS);
  59     s->host.pci.bus = b;
  60     qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
  61     qdev_init_nofail(DEVICE(&s->mch));
  62
  63     return 0;
  64 }
  65
  66 static Property mch_props[] = {
  67     DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
  68                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
  69     DEFINE_PROP_END_OF_LIST(),
  70 };
  71
  72 static void q35_host_class_init(ObjectClass *klass, void *data)
  73 {
  74     DeviceClass *dc = DEVICE_CLASS(klass);
  75     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  76
  77     k->init = q35_host_init;
  78     dc->props = mch_props;
  79 }
  80
  81 static void q35_host_initfn(Object *obj)
  82 {
  83     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  84
  85     object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
  86     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
  87     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
  88     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
  89 }
  90
  91 static const TypeInfo q35_host_info = {
  92     .name       = TYPE_Q35_HOST_DEVICE,
  93     .parent     = TYPE_PCIE_HOST_BRIDGE,
  94     .instance_size = sizeof(Q35PCIHost),
  95     .instance_init = q35_host_initfn,
  96     .class_init = q35_host_class_init,
  97 };
  98
  99 /****************************************************************************
 100  * MCH D0:F0
 101  */
 102
 103 /* PCIe MMCFG */
 104 static void mch_update_pciexbar(MCHPCIState *mch)
 105 {
 106     PCIDevice *pci_dev = &mch->d;
 107     BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
 108     DeviceState *qdev = bus->parent;
 109     Q35PCIHost *s = Q35_HOST_DEVICE(qdev);
 110
 111     uint64_t pciexbar;
 112     int enable;
 113     uint64_t addr;
 114     uint64_t addr_mask;
 115     uint32_t length;
 116
 117     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 118     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 119     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 120     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 121     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 122         length = 256 * 1024 * 1024;
 123         break;
 124     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 125         length = 128 * 1024 * 1024;
 126         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 127             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 128         break;
 129     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 130         length = 64 * 1024 * 1024;
 131         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 132         break;
 133     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 134     default:
 135         enable = 0;
 136         length = 0;
 137         abort();
 138         break;
 139     }
 140     addr = pciexbar & addr_mask;
 141     pcie_host_mmcfg_update(&s->host, enable, addr, length);
 142 }
 143
 144 /* PAM */
 145 static void mch_update_pam(MCHPCIState *mch)
 146 {
 147     int i;
 148
 149     memory_region_transaction_begin();
 150     for (i = 0; i < 13; i++) {
 151         pam_update(&mch->pam_regions[i], i,
 152                    mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
 153     }
 154     memory_region_transaction_commit();
 155 }
 156
 157 /* SMRAM */
 158 static void mch_update_smram(MCHPCIState *mch)
 159 {
 160     memory_region_transaction_begin();
 161     smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
 162                     mch->smm_enabled);
 163     memory_region_transaction_commit();
 164 }
 165
 166 static void mch_set_smm(int smm, void *arg)
 167 {
 168     MCHPCIState *mch = arg;
 169
 170     memory_region_transaction_begin();
 171     smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
 172                     &mch->smram_region);
 173     memory_region_transaction_commit();
 174 }
 175
 176 static void mch_write_config(PCIDevice *d,
 177                               uint32_t address, uint32_t val, int len)
 178 {
 179     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 180
 181     /* XXX: implement SMRAM.D_LOCK */
 182     pci_default_write_config(d, address, val, len);
 183
 184     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 185                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 186         mch_update_pam(mch);
 187     }
 188
 189     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 190                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 191         mch_update_pciexbar(mch);
 192     }
 193
 194     if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
 195                        MCH_HOST_BRDIGE_SMRAM_SIZE)) {
 196         mch_update_smram(mch);
 197     }
 198 }
 199
 200 static void mch_update(MCHPCIState *mch)
 201 {
 202     mch_update_pciexbar(mch);
 203     mch_update_pam(mch);
 204     mch_update_smram(mch);
 205 }
 206
 207 static int mch_post_load(void *opaque, int version_id)
 208 {
 209     MCHPCIState *mch = opaque;
 210     mch_update(mch);
 211     return 0;
 212 }
 213
 214 static const VMStateDescription vmstate_mch = {
 215     .name = "mch",
 216     .version_id = 1,
 217     .minimum_version_id = 1,
 218     .minimum_version_id_old = 1,
 219     .post_load = mch_post_load,
 220     .fields = (VMStateField []) {
 221         VMSTATE_PCI_DEVICE(d, MCHPCIState),
 222         VMSTATE_UINT8(smm_enabled, MCHPCIState),
 223         VMSTATE_END_OF_LIST()
 224     }
 225 };
 226
 227 static void mch_reset(DeviceState *qdev)
 228 {
 229     PCIDevice *d = PCI_DEVICE(qdev);
 230     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 231
 232     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 233                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 234
 235     d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 236
 237     mch_update(mch);
 238 }
 239
 240 static int mch_init(PCIDevice *d)
 241 {
 242     int i;
 243     hwaddr pci_hole64_size;
 244     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 245
 246     /* setup pci memory regions */
 247     memory_region_init_alias(&mch->pci_hole, "pci-hole",
 248                              mch->pci_address_space,
 249                              mch->below_4g_mem_size,
 250                              0x100000000ULL - mch->below_4g_mem_size);
 251     memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
 252                                 &mch->pci_hole);
 253     pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
 254                        ((uint64_t)1 << 62));
 255     memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64",
 256                              mch->pci_address_space,
 257                              0x100000000ULL + mch->above_4g_mem_size,
 258                              pci_hole64_size);
 259     if (pci_hole64_size) {
 260         memory_region_add_subregion(mch->system_memory,
 261                                     0x100000000ULL + mch->above_4g_mem_size,
 262                                     &mch->pci_hole_64bit);
 263     }
 264     /* smram */
 265     cpu_smm_register(&mch_set_smm, mch);
 266     memory_region_init_alias(&mch->smram_region, "smram-region",
 267                              mch->pci_address_space, 0xa0000, 0x20000);
 268     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 269                                         &mch->smram_region, 1);
 270     memory_region_set_enabled(&mch->smram_region, false);
 271     init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space,
 272              &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 273     for (i = 0; i < 12; ++i) {
 274         init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space,
 275                  &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 276                  PAM_EXPAN_SIZE);
 277     }
 278     return 0;
 279 }
 280
 281 static void mch_class_init(ObjectClass *klass, void *data)
 282 {
 283     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 284     DeviceClass *dc = DEVICE_CLASS(klass);
 285
 286     k->init = mch_init;
 287     k->config_write = mch_write_config;
 288     dc->reset = mch_reset;
 289     dc->desc = "Host bridge";
 290     dc->vmsd = &vmstate_mch;
 291     k->vendor_id = PCI_VENDOR_ID_INTEL;
 292     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 293     k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
 294     k->class_id = PCI_CLASS_BRIDGE_HOST;
 295 }
 296
 297 static const TypeInfo mch_info = {
 298     .name = TYPE_MCH_PCI_DEVICE,
 299     .parent = TYPE_PCI_DEVICE,
 300     .instance_size = sizeof(MCHPCIState),
 301     .class_init = mch_class_init,
 302 };
 303
 304 static void q35_register(void)
 305 {
 306     type_register_static(&mch_info);
 307     type_register_static(&q35_host_info);
 308 }
 309
 310 type_init(q35_register);