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hyperv: qom-ify SynIC
[qemu/ar7.git] / target / i386 / kvm.c
blobcf6270ae396e481145819247848ab2803f40b708
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci/msix.h"
46 #include "migration/blocker.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72 };
73
74 static bool has_msr_star;
75 static bool has_msr_hsave_pa;
76 static bool has_msr_tsc_aux;
77 static bool has_msr_tsc_adjust;
78 static bool has_msr_tsc_deadline;
79 static bool has_msr_feature_control;
80 static bool has_msr_misc_enable;
81 static bool has_msr_smbase;
82 static bool has_msr_bndcfgs;
83 static int lm_capable_kernel;
84 static bool has_msr_hv_hypercall;
85 static bool has_msr_hv_crash;
86 static bool has_msr_hv_reset;
87 static bool has_msr_hv_vpindex;
88 static bool hv_vpindex_settable;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_hv_reenlightenment;
94 static bool has_msr_xss;
95 static bool has_msr_spec_ctrl;
96 static bool has_msr_virt_ssbd;
97 static bool has_msr_smi_count;
98
99 static uint32_t has_architectural_pmu_version;
100 static uint32_t num_architectural_pmu_gp_counters;
101 static uint32_t num_architectural_pmu_fixed_counters;
102
103 static int has_xsave;
104 static int has_xcrs;
105 static int has_pit_state2;
106
107 static bool has_msr_mcg_ext_ctl;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110
111 int kvm_has_pit_state2(void)
112 {
113 return has_pit_state2;
114 }
115
116 bool kvm_has_smm(void)
117 {
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119 }
120
121 bool kvm_has_adjust_clock_stable(void)
122 {
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126 }
127
128 bool kvm_allows_irq0_override(void)
129 {
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131 }
132
133 static bool kvm_x2apic_api_set_flags(uint64_t flags)
134 {
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138 }
139
140 #define MEMORIZE(fn, _result) \
141 ({ \
142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
151 static bool has_x2apic_api;
152
153 bool kvm_has_x2apic_api(void)
154 {
155 return has_x2apic_api;
156 }
157
158 bool kvm_enable_x2apic(void)
159 {
160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
164 }
165
166 bool kvm_hv_vpindex_settable(void)
167 {
168 return hv_vpindex_settable;
169 }
170
171 static int kvm_get_tsc(CPUState *cs)
172 {
173 X86CPU *cpu = X86_CPU(cs);
174 CPUX86State *env = &cpu->env;
175 struct {
176 struct kvm_msrs info;
177 struct kvm_msr_entry entries[1];
178 } msr_data;
179 int ret;
180
181 if (env->tsc_valid) {
182 return 0;
183 }
184
185 msr_data.info.nmsrs = 1;
186 msr_data.entries[0].index = MSR_IA32_TSC;
187 env->tsc_valid = !runstate_is_running();
188
189 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
190 if (ret < 0) {
191 return ret;
192 }
193
194 assert(ret == 1);
195 env->tsc = msr_data.entries[0].data;
196 return 0;
197 }
198
199 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
200 {
201 kvm_get_tsc(cpu);
202 }
203
204 void kvm_synchronize_all_tsc(void)
205 {
206 CPUState *cpu;
207
208 if (kvm_enabled()) {
209 CPU_FOREACH(cpu) {
210 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
211 }
212 }
213 }
214
215 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
216 {
217 struct kvm_cpuid2 *cpuid;
218 int r, size;
219
220 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
221 cpuid = g_malloc0(size);
222 cpuid->nent = max;
223 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
224 if (r == 0 && cpuid->nent >= max) {
225 r = -E2BIG;
226 }
227 if (r < 0) {
228 if (r == -E2BIG) {
229 g_free(cpuid);
230 return NULL;
231 } else {
232 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
233 strerror(-r));
234 exit(1);
235 }
236 }
237 return cpuid;
238 }
239
240 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
241 * for all entries.
242 */
243 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
244 {
245 struct kvm_cpuid2 *cpuid;
246 int max = 1;
247
248 if (cpuid_cache != NULL) {
249 return cpuid_cache;
250 }
251 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
252 max *= 2;
253 }
254 cpuid_cache = cpuid;
255 return cpuid;
256 }
257
258 static const struct kvm_para_features {
259 int cap;
260 int feature;
261 } para_features[] = {
262 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
263 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
264 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
265 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
266 };
267
268 static int get_para_features(KVMState *s)
269 {
270 int i, features = 0;
271
272 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
273 if (kvm_check_extension(s, para_features[i].cap)) {
274 features |= (1 << para_features[i].feature);
275 }
276 }
277
278 return features;
279 }
280
281 static bool host_tsx_blacklisted(void)
282 {
283 int family, model, stepping;\
284 char vendor[CPUID_VENDOR_SZ + 1];
285
286 host_vendor_fms(vendor, &family, &model, &stepping);
287
288 /* Check if we are running on a Haswell host known to have broken TSX */
289 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
290 (family == 6) &&
291 ((model == 63 && stepping < 4) ||
292 model == 60 || model == 69 || model == 70);
293 }
294
295 /* Returns the value for a specific register on the cpuid entry
296 */
297 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
298 {
299 uint32_t ret = 0;
300 switch (reg) {
301 case R_EAX:
302 ret = entry->eax;
303 break;
304 case R_EBX:
305 ret = entry->ebx;
306 break;
307 case R_ECX:
308 ret = entry->ecx;
309 break;
310 case R_EDX:
311 ret = entry->edx;
312 break;
313 }
314 return ret;
315 }
316
317 /* Find matching entry for function/index on kvm_cpuid2 struct
318 */
319 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
320 uint32_t function,
321 uint32_t index)
322 {
323 int i;
324 for (i = 0; i < cpuid->nent; ++i) {
325 if (cpuid->entries[i].function == function &&
326 cpuid->entries[i].index == index) {
327 return &cpuid->entries[i];
328 }
329 }
330 /* not found: */
331 return NULL;
332 }
333
334 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
335 uint32_t index, int reg)
336 {
337 struct kvm_cpuid2 *cpuid;
338 uint32_t ret = 0;
339 uint32_t cpuid_1_edx;
340 bool found = false;
341
342 cpuid = get_supported_cpuid(s);
343
344 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
345 if (entry) {
346 found = true;
347 ret = cpuid_entry_get_reg(entry, reg);
348 }
349
350 /* Fixups for the data returned by KVM, below */
351
352 if (function == 1 && reg == R_EDX) {
353 /* KVM before 2.6.30 misreports the following features */
354 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
355 } else if (function == 1 && reg == R_ECX) {
356 /* We can set the hypervisor flag, even if KVM does not return it on
357 * GET_SUPPORTED_CPUID
358 */
359 ret |= CPUID_EXT_HYPERVISOR;
360 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
361 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
362 * and the irqchip is in the kernel.
363 */
364 if (kvm_irqchip_in_kernel() &&
365 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
366 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
367 }
368
369 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
370 * without the in-kernel irqchip
371 */
372 if (!kvm_irqchip_in_kernel()) {
373 ret &= ~CPUID_EXT_X2APIC;
374 }
375
376 if (enable_cpu_pm) {
377 int disable_exits = kvm_check_extension(s,
378 KVM_CAP_X86_DISABLE_EXITS);
379
380 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
381 ret |= CPUID_EXT_MONITOR;
382 }
383 }
384 } else if (function == 6 && reg == R_EAX) {
385 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
386 } else if (function == 7 && index == 0 && reg == R_EBX) {
387 if (host_tsx_blacklisted()) {
388 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
389 }
390 } else if (function == 0x80000001 && reg == R_ECX) {
391 /*
392 * It's safe to enable TOPOEXT even if it's not returned by
393 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
394 * us to keep CPU models including TOPOEXT runnable on older kernels.
395 */
396 ret |= CPUID_EXT3_TOPOEXT;
397 } else if (function == 0x80000001 && reg == R_EDX) {
398 /* On Intel, kvm returns cpuid according to the Intel spec,
399 * so add missing bits according to the AMD spec:
400 */
401 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
402 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
403 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
404 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
405 * be enabled without the in-kernel irqchip
406 */
407 if (!kvm_irqchip_in_kernel()) {
408 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
409 }
410 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
411 ret |= 1U << KVM_HINTS_REALTIME;
412 found = 1;
413 }
414
415 /* fallback for older kernels */
416 if ((function == KVM_CPUID_FEATURES) && !found) {
417 ret = get_para_features(s);
418 }
419
420 return ret;
421 }
422
423 typedef struct HWPoisonPage {
424 ram_addr_t ram_addr;
425 QLIST_ENTRY(HWPoisonPage) list;
426 } HWPoisonPage;
427
428 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
429 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
430
431 static void kvm_unpoison_all(void *param)
432 {
433 HWPoisonPage *page, *next_page;
434
435 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
436 QLIST_REMOVE(page, list);
437 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
438 g_free(page);
439 }
440 }
441
442 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
443 {
444 HWPoisonPage *page;
445
446 QLIST_FOREACH(page, &hwpoison_page_list, list) {
447 if (page->ram_addr == ram_addr) {
448 return;
449 }
450 }
451 page = g_new(HWPoisonPage, 1);
452 page->ram_addr = ram_addr;
453 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
454 }
455
456 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
457 int *max_banks)
458 {
459 int r;
460
461 r = kvm_check_extension(s, KVM_CAP_MCE);
462 if (r > 0) {
463 *max_banks = r;
464 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
465 }
466 return -ENOSYS;
467 }
468
469 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
470 {
471 CPUState *cs = CPU(cpu);
472 CPUX86State *env = &cpu->env;
473 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
474 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
475 uint64_t mcg_status = MCG_STATUS_MCIP;
476 int flags = 0;
477
478 if (code == BUS_MCEERR_AR) {
479 status |= MCI_STATUS_AR | 0x134;
480 mcg_status |= MCG_STATUS_EIPV;
481 } else {
482 status |= 0xc0;
483 mcg_status |= MCG_STATUS_RIPV;
484 }
485
486 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
487 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
488 * guest kernel back into env->mcg_ext_ctl.
489 */
490 cpu_synchronize_state(cs);
491 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
492 mcg_status |= MCG_STATUS_LMCE;
493 flags = 0;
494 }
495
496 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
497 (MCM_ADDR_PHYS << 6) | 0xc, flags);
498 }
499
500 static void hardware_memory_error(void)
501 {
502 fprintf(stderr, "Hardware memory error!\n");
503 exit(1);
504 }
505
506 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
507 {
508 X86CPU *cpu = X86_CPU(c);
509 CPUX86State *env = &cpu->env;
510 ram_addr_t ram_addr;
511 hwaddr paddr;
512
513 /* If we get an action required MCE, it has been injected by KVM
514 * while the VM was running. An action optional MCE instead should
515 * be coming from the main thread, which qemu_init_sigbus identifies
516 * as the "early kill" thread.
517 */
518 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
519
520 if ((env->mcg_cap & MCG_SER_P) && addr) {
521 ram_addr = qemu_ram_addr_from_host(addr);
522 if (ram_addr != RAM_ADDR_INVALID &&
523 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
524 kvm_hwpoison_page_add(ram_addr);
525 kvm_mce_inject(cpu, paddr, code);
526 return;
527 }
528
529 fprintf(stderr, "Hardware memory error for memory used by "
530 "QEMU itself instead of guest system!\n");
531 }
532
533 if (code == BUS_MCEERR_AR) {
534 hardware_memory_error();
535 }
536
537 /* Hope we are lucky for AO MCE */
538 }
539
540 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
541 {
542 CPUX86State *env = &cpu->env;
543
544 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
545 unsigned int bank, bank_num = env->mcg_cap & 0xff;
546 struct kvm_x86_mce mce;
547
548 env->exception_injected = -1;
549
550 /*
551 * There must be at least one bank in use if an MCE is pending.
552 * Find it and use its values for the event injection.
553 */
554 for (bank = 0; bank < bank_num; bank++) {
555 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
556 break;
557 }
558 }
559 assert(bank < bank_num);
560
561 mce.bank = bank;
562 mce.status = env->mce_banks[bank * 4 + 1];
563 mce.mcg_status = env->mcg_status;
564 mce.addr = env->mce_banks[bank * 4 + 2];
565 mce.misc = env->mce_banks[bank * 4 + 3];
566
567 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
568 }
569 return 0;
570 }
571
572 static void cpu_update_state(void *opaque, int running, RunState state)
573 {
574 CPUX86State *env = opaque;
575
576 if (running) {
577 env->tsc_valid = false;
578 }
579 }
580
581 unsigned long kvm_arch_vcpu_id(CPUState *cs)
582 {
583 X86CPU *cpu = X86_CPU(cs);
584 return cpu->apic_id;
585 }
586
587 #ifndef KVM_CPUID_SIGNATURE_NEXT
588 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
589 #endif
590
591 static bool hyperv_hypercall_available(X86CPU *cpu)
592 {
593 return cpu->hyperv_vapic ||
594 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
595 }
596
597 static bool hyperv_enabled(X86CPU *cpu)
598 {
599 CPUState *cs = CPU(cpu);
600 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
601 (hyperv_hypercall_available(cpu) ||
602 cpu->hyperv_time ||
603 cpu->hyperv_relaxed_timing ||
604 cpu->hyperv_crash ||
605 cpu->hyperv_reset ||
606 cpu->hyperv_vpindex ||
607 cpu->hyperv_runtime ||
608 cpu->hyperv_synic ||
609 cpu->hyperv_stimer ||
610 cpu->hyperv_reenlightenment ||
611 cpu->hyperv_tlbflush ||
612 cpu->hyperv_ipi);
613 }
614
615 static int kvm_arch_set_tsc_khz(CPUState *cs)
616 {
617 X86CPU *cpu = X86_CPU(cs);
618 CPUX86State *env = &cpu->env;
619 int r;
620
621 if (!env->tsc_khz) {
622 return 0;
623 }
624
625 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
626 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
627 -ENOTSUP;
628 if (r < 0) {
629 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
630 * TSC frequency doesn't match the one we want.
631 */
632 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
633 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
634 -ENOTSUP;
635 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
636 warn_report("TSC frequency mismatch between "
637 "VM (%" PRId64 " kHz) and host (%d kHz), "
638 "and TSC scaling unavailable",
639 env->tsc_khz, cur_freq);
640 return r;
641 }
642 }
643
644 return 0;
645 }
646
647 static bool tsc_is_stable_and_known(CPUX86State *env)
648 {
649 if (!env->tsc_khz) {
650 return false;
651 }
652 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
653 || env->user_tsc_khz;
654 }
655
656 static int hyperv_handle_properties(CPUState *cs)
657 {
658 X86CPU *cpu = X86_CPU(cs);
659 CPUX86State *env = &cpu->env;
660
661 if (cpu->hyperv_relaxed_timing) {
662 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
663 }
664 if (cpu->hyperv_vapic) {
665 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
666 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
667 }
668 if (cpu->hyperv_time) {
669 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
670 fprintf(stderr, "Hyper-V clocksources "
671 "(requested by 'hv-time' cpu flag) "
672 "are not supported by kernel\n");
673 return -ENOSYS;
674 }
675 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
676 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
677 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
678 }
679 if (cpu->hyperv_frequencies) {
680 if (!has_msr_hv_frequencies) {
681 fprintf(stderr, "Hyper-V frequency MSRs "
682 "(requested by 'hv-frequencies' cpu flag) "
683 "are not supported by kernel\n");
684 return -ENOSYS;
685 }
686 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
687 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
688 }
689 if (cpu->hyperv_crash) {
690 if (!has_msr_hv_crash) {
691 fprintf(stderr, "Hyper-V crash MSRs "
692 "(requested by 'hv-crash' cpu flag) "
693 "are not supported by kernel\n");
694 return -ENOSYS;
695 }
696 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
697 }
698 if (cpu->hyperv_reenlightenment) {
699 if (!has_msr_hv_reenlightenment) {
700 fprintf(stderr,
701 "Hyper-V Reenlightenment MSRs "
702 "(requested by 'hv-reenlightenment' cpu flag) "
703 "are not supported by kernel\n");
704 return -ENOSYS;
705 }
706 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
707 }
708 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
709 if (cpu->hyperv_reset) {
710 if (!has_msr_hv_reset) {
711 fprintf(stderr, "Hyper-V reset MSR "
712 "(requested by 'hv-reset' cpu flag) "
713 "is not supported by kernel\n");
714 return -ENOSYS;
715 }
716 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
717 }
718 if (cpu->hyperv_vpindex) {
719 if (!has_msr_hv_vpindex) {
720 fprintf(stderr, "Hyper-V VP_INDEX MSR "
721 "(requested by 'hv-vpindex' cpu flag) "
722 "is not supported by kernel\n");
723 return -ENOSYS;
724 }
725 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
726 }
727 if (cpu->hyperv_runtime) {
728 if (!has_msr_hv_runtime) {
729 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
730 "(requested by 'hv-runtime' cpu flag) "
731 "is not supported by kernel\n");
732 return -ENOSYS;
733 }
734 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
735 }
736 if (cpu->hyperv_synic) {
737 if (!has_msr_hv_synic ||
738 !kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_SYNIC)) {
739 fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
740 "is not supported by kernel\n");
741 return -ENOSYS;
742 }
743
744 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
745 }
746 if (cpu->hyperv_stimer) {
747 if (!has_msr_hv_stimer) {
748 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
749 return -ENOSYS;
750 }
751 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
752 }
753 return 0;
754 }
755
756 static int hyperv_init_vcpu(X86CPU *cpu)
757 {
758 CPUState *cs = CPU(cpu);
759 int ret;
760
761 if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
762 /*
763 * the kernel doesn't support setting vp_index; assert that its value
764 * is in sync
765 */
766 struct {
767 struct kvm_msrs info;
768 struct kvm_msr_entry entries[1];
769 } msr_data = {
770 .info.nmsrs = 1,
771 .entries[0].index = HV_X64_MSR_VP_INDEX,
772 };
773
774 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
775 if (ret < 0) {
776 return ret;
777 }
778 assert(ret == 1);
779
780 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
781 error_report("kernel's vp_index != QEMU's vp_index");
782 return -ENXIO;
783 }
784 }
785
786 if (cpu->hyperv_synic) {
787 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0);
788 if (ret < 0) {
789 error_report("failed to turn on HyperV SynIC in KVM: %s",
790 strerror(-ret));
791 return ret;
792 }
793
794 ret = hyperv_x86_synic_add(cpu);
795 if (ret < 0) {
796 error_report("failed to create HyperV SynIC: %s",
797 strerror(-ret));
798 return ret;
799 }
800 }
801
802 return 0;
803 }
804
805 static Error *invtsc_mig_blocker;
806
807 #define KVM_MAX_CPUID_ENTRIES 100
808
809 int kvm_arch_init_vcpu(CPUState *cs)
810 {
811 struct {
812 struct kvm_cpuid2 cpuid;
813 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
814 } QEMU_PACKED cpuid_data;
815 X86CPU *cpu = X86_CPU(cs);
816 CPUX86State *env = &cpu->env;
817 uint32_t limit, i, j, cpuid_i;
818 uint32_t unused;
819 struct kvm_cpuid_entry2 *c;
820 uint32_t signature[3];
821 int kvm_base = KVM_CPUID_SIGNATURE;
822 int r;
823 Error *local_err = NULL;
824
825 memset(&cpuid_data, 0, sizeof(cpuid_data));
826
827 cpuid_i = 0;
828
829 r = kvm_arch_set_tsc_khz(cs);
830 if (r < 0) {
831 goto fail;
832 }
833
834 /* vcpu's TSC frequency is either specified by user, or following
835 * the value used by KVM if the former is not present. In the
836 * latter case, we query it from KVM and record in env->tsc_khz,
837 * so that vcpu's TSC frequency can be migrated later via this field.
838 */
839 if (!env->tsc_khz) {
840 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
841 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
842 -ENOTSUP;
843 if (r > 0) {
844 env->tsc_khz = r;
845 }
846 }
847
848 /* Paravirtualization CPUIDs */
849 if (hyperv_enabled(cpu)) {
850 c = &cpuid_data.entries[cpuid_i++];
851 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
852 if (!cpu->hyperv_vendor_id) {
853 memcpy(signature, "Microsoft Hv", 12);
854 } else {
855 size_t len = strlen(cpu->hyperv_vendor_id);
856
857 if (len > 12) {
858 error_report("hv-vendor-id truncated to 12 characters");
859 len = 12;
860 }
861 memset(signature, 0, 12);
862 memcpy(signature, cpu->hyperv_vendor_id, len);
863 }
864 c->eax = HV_CPUID_MIN;
865 c->ebx = signature[0];
866 c->ecx = signature[1];
867 c->edx = signature[2];
868
869 c = &cpuid_data.entries[cpuid_i++];
870 c->function = HV_CPUID_INTERFACE;
871 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
872 c->eax = signature[0];
873 c->ebx = 0;
874 c->ecx = 0;
875 c->edx = 0;
876
877 c = &cpuid_data.entries[cpuid_i++];
878 c->function = HV_CPUID_VERSION;
879 c->eax = 0x00001bbc;
880 c->ebx = 0x00060001;
881
882 c = &cpuid_data.entries[cpuid_i++];
883 c->function = HV_CPUID_FEATURES;
884 r = hyperv_handle_properties(cs);
885 if (r) {
886 return r;
887 }
888 c->eax = env->features[FEAT_HYPERV_EAX];
889 c->ebx = env->features[FEAT_HYPERV_EBX];
890 c->edx = env->features[FEAT_HYPERV_EDX];
891
892 c = &cpuid_data.entries[cpuid_i++];
893 c->function = HV_CPUID_ENLIGHTMENT_INFO;
894 if (cpu->hyperv_relaxed_timing) {
895 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
896 }
897 if (cpu->hyperv_vapic) {
898 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
899 }
900 if (cpu->hyperv_tlbflush) {
901 if (kvm_check_extension(cs->kvm_state,
902 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
903 fprintf(stderr, "Hyper-V TLB flush support "
904 "(requested by 'hv-tlbflush' cpu flag) "
905 " is not supported by kernel\n");
906 return -ENOSYS;
907 }
908 c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
909 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
910 }
911 if (cpu->hyperv_ipi) {
912 if (kvm_check_extension(cs->kvm_state,
913 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
914 fprintf(stderr, "Hyper-V IPI send support "
915 "(requested by 'hv-ipi' cpu flag) "
916 " is not supported by kernel\n");
917 return -ENOSYS;
918 }
919 c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
920 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
921 }
922
923 c->ebx = cpu->hyperv_spinlock_attempts;
924
925 c = &cpuid_data.entries[cpuid_i++];
926 c->function = HV_CPUID_IMPLEMENT_LIMITS;
927
928 c->eax = cpu->hv_max_vps;
929 c->ebx = 0x40;
930
931 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
932 has_msr_hv_hypercall = true;
933 }
934
935 if (cpu->expose_kvm) {
936 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
937 c = &cpuid_data.entries[cpuid_i++];
938 c->function = KVM_CPUID_SIGNATURE | kvm_base;
939 c->eax = KVM_CPUID_FEATURES | kvm_base;
940 c->ebx = signature[0];
941 c->ecx = signature[1];
942 c->edx = signature[2];
943
944 c = &cpuid_data.entries[cpuid_i++];
945 c->function = KVM_CPUID_FEATURES | kvm_base;
946 c->eax = env->features[FEAT_KVM];
947 c->edx = env->features[FEAT_KVM_HINTS];
948 }
949
950 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
951
952 for (i = 0; i <= limit; i++) {
953 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
954 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
955 abort();
956 }
957 c = &cpuid_data.entries[cpuid_i++];
958
959 switch (i) {
960 case 2: {
961 /* Keep reading function 2 till all the input is received */
962 int times;
963
964 c->function = i;
965 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
966 KVM_CPUID_FLAG_STATE_READ_NEXT;
967 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
968 times = c->eax & 0xff;
969
970 for (j = 1; j < times; ++j) {
971 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
972 fprintf(stderr, "cpuid_data is full, no space for "
973 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
974 abort();
975 }
976 c = &cpuid_data.entries[cpuid_i++];
977 c->function = i;
978 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
979 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
980 }
981 break;
982 }
983 case 4:
984 case 0xb:
985 case 0xd:
986 for (j = 0; ; j++) {
987 if (i == 0xd && j == 64) {
988 break;
989 }
990 c->function = i;
991 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
992 c->index = j;
993 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
994
995 if (i == 4 && c->eax == 0) {
996 break;
997 }
998 if (i == 0xb && !(c->ecx & 0xff00)) {
999 break;
1000 }
1001 if (i == 0xd && c->eax == 0) {
1002 continue;
1003 }
1004 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1005 fprintf(stderr, "cpuid_data is full, no space for "
1006 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1007 abort();
1008 }
1009 c = &cpuid_data.entries[cpuid_i++];
1010 }
1011 break;
1012 case 0x14: {
1013 uint32_t times;
1014
1015 c->function = i;
1016 c->index = 0;
1017 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1018 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1019 times = c->eax;
1020
1021 for (j = 1; j <= times; ++j) {
1022 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1023 fprintf(stderr, "cpuid_data is full, no space for "
1024 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1025 abort();
1026 }
1027 c = &cpuid_data.entries[cpuid_i++];
1028 c->function = i;
1029 c->index = j;
1030 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1031 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1032 }
1033 break;
1034 }
1035 default:
1036 c->function = i;
1037 c->flags = 0;
1038 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1039 break;
1040 }
1041 }
1042
1043 if (limit >= 0x0a) {
1044 uint32_t eax, edx;
1045
1046 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1047
1048 has_architectural_pmu_version = eax & 0xff;
1049 if (has_architectural_pmu_version > 0) {
1050 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1051
1052 /* Shouldn't be more than 32, since that's the number of bits
1053 * available in EBX to tell us _which_ counters are available.
1054 * Play it safe.
1055 */
1056 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1057 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1058 }
1059
1060 if (has_architectural_pmu_version > 1) {
1061 num_architectural_pmu_fixed_counters = edx & 0x1f;
1062
1063 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1064 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1065 }
1066 }
1067 }
1068 }
1069
1070 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1071
1072 for (i = 0x80000000; i <= limit; i++) {
1073 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1074 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1075 abort();
1076 }
1077 c = &cpuid_data.entries[cpuid_i++];
1078
1079 switch (i) {
1080 case 0x8000001d:
1081 /* Query for all AMD cache information leaves */
1082 for (j = 0; ; j++) {
1083 c->function = i;
1084 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1085 c->index = j;
1086 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1087
1088 if (c->eax == 0) {
1089 break;
1090 }
1091 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1092 fprintf(stderr, "cpuid_data is full, no space for "
1093 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1094 abort();
1095 }
1096 c = &cpuid_data.entries[cpuid_i++];
1097 }
1098 break;
1099 default:
1100 c->function = i;
1101 c->flags = 0;
1102 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1103 break;
1104 }
1105 }
1106
1107 /* Call Centaur's CPUID instructions they are supported. */
1108 if (env->cpuid_xlevel2 > 0) {
1109 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1110
1111 for (i = 0xC0000000; i <= limit; i++) {
1112 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1113 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1114 abort();
1115 }
1116 c = &cpuid_data.entries[cpuid_i++];
1117
1118 c->function = i;
1119 c->flags = 0;
1120 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1121 }
1122 }
1123
1124 cpuid_data.cpuid.nent = cpuid_i;
1125
1126 if (((env->cpuid_version >> 8)&0xF) >= 6
1127 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1128 (CPUID_MCE | CPUID_MCA)
1129 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1130 uint64_t mcg_cap, unsupported_caps;
1131 int banks;
1132 int ret;
1133
1134 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1135 if (ret < 0) {
1136 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1137 return ret;
1138 }
1139
1140 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1141 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1142 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1143 return -ENOTSUP;
1144 }
1145
1146 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1147 if (unsupported_caps) {
1148 if (unsupported_caps & MCG_LMCE_P) {
1149 error_report("kvm: LMCE not supported");
1150 return -ENOTSUP;
1151 }
1152 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1153 unsupported_caps);
1154 }
1155
1156 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1157 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1158 if (ret < 0) {
1159 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1160 return ret;
1161 }
1162 }
1163
1164 qemu_add_vm_change_state_handler(cpu_update_state, env);
1165
1166 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1167 if (c) {
1168 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1169 !!(c->ecx & CPUID_EXT_SMX);
1170 }
1171
1172 if (env->mcg_cap & MCG_LMCE_P) {
1173 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1174 }
1175
1176 if (!env->user_tsc_khz) {
1177 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1178 invtsc_mig_blocker == NULL) {
1179 /* for migration */
1180 error_setg(&invtsc_mig_blocker,
1181 "State blocked by non-migratable CPU device"
1182 " (invtsc flag)");
1183 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1184 if (local_err) {
1185 error_report_err(local_err);
1186 error_free(invtsc_mig_blocker);
1187 goto fail;
1188 }
1189 /* for savevm */
1190 vmstate_x86_cpu.unmigratable = 1;
1191 }
1192 }
1193
1194 if (cpu->vmware_cpuid_freq
1195 /* Guests depend on 0x40000000 to detect this feature, so only expose
1196 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1197 && cpu->expose_kvm
1198 && kvm_base == KVM_CPUID_SIGNATURE
1199 /* TSC clock must be stable and known for this feature. */
1200 && tsc_is_stable_and_known(env)) {
1201
1202 c = &cpuid_data.entries[cpuid_i++];
1203 c->function = KVM_CPUID_SIGNATURE | 0x10;
1204 c->eax = env->tsc_khz;
1205 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1206 * APIC_BUS_CYCLE_NS */
1207 c->ebx = 1000000;
1208 c->ecx = c->edx = 0;
1209
1210 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1211 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1212 }
1213
1214 cpuid_data.cpuid.nent = cpuid_i;
1215
1216 cpuid_data.cpuid.padding = 0;
1217 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1218 if (r) {
1219 goto fail;
1220 }
1221
1222 if (has_xsave) {
1223 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1224 }
1225 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1226
1227 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1228 has_msr_tsc_aux = false;
1229 }
1230
1231 r = hyperv_init_vcpu(cpu);
1232 if (r) {
1233 goto fail;
1234 }
1235
1236 return 0;
1237
1238 fail:
1239 migrate_del_blocker(invtsc_mig_blocker);
1240 return r;
1241 }
1242
1243 void kvm_arch_reset_vcpu(X86CPU *cpu)
1244 {
1245 CPUX86State *env = &cpu->env;
1246
1247 env->xcr0 = 1;
1248 if (kvm_irqchip_in_kernel()) {
1249 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1250 KVM_MP_STATE_UNINITIALIZED;
1251 } else {
1252 env->mp_state = KVM_MP_STATE_RUNNABLE;
1253 }
1254
1255 if (cpu->hyperv_synic) {
1256 int i;
1257 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1258 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1259 }
1260
1261 hyperv_x86_synic_reset(cpu);
1262 }
1263 }
1264
1265 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1266 {
1267 CPUX86State *env = &cpu->env;
1268
1269 /* APs get directly into wait-for-SIPI state. */
1270 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1271 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1272 }
1273 }
1274
1275 static int kvm_get_supported_msrs(KVMState *s)
1276 {
1277 static int kvm_supported_msrs;
1278 int ret = 0;
1279
1280 /* first time */
1281 if (kvm_supported_msrs == 0) {
1282 struct kvm_msr_list msr_list, *kvm_msr_list;
1283
1284 kvm_supported_msrs = -1;
1285
1286 /* Obtain MSR list from KVM. These are the MSRs that we must
1287 * save/restore */
1288 msr_list.nmsrs = 0;
1289 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1290 if (ret < 0 && ret != -E2BIG) {
1291 return ret;
1292 }
1293 /* Old kernel modules had a bug and could write beyond the provided
1294 memory. Allocate at least a safe amount of 1K. */
1295 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1296 msr_list.nmsrs *
1297 sizeof(msr_list.indices[0])));
1298
1299 kvm_msr_list->nmsrs = msr_list.nmsrs;
1300 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1301 if (ret >= 0) {
1302 int i;
1303
1304 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1305 switch (kvm_msr_list->indices[i]) {
1306 case MSR_STAR:
1307 has_msr_star = true;
1308 break;
1309 case MSR_VM_HSAVE_PA:
1310 has_msr_hsave_pa = true;
1311 break;
1312 case MSR_TSC_AUX:
1313 has_msr_tsc_aux = true;
1314 break;
1315 case MSR_TSC_ADJUST:
1316 has_msr_tsc_adjust = true;
1317 break;
1318 case MSR_IA32_TSCDEADLINE:
1319 has_msr_tsc_deadline = true;
1320 break;
1321 case MSR_IA32_SMBASE:
1322 has_msr_smbase = true;
1323 break;
1324 case MSR_SMI_COUNT:
1325 has_msr_smi_count = true;
1326 break;
1327 case MSR_IA32_MISC_ENABLE:
1328 has_msr_misc_enable = true;
1329 break;
1330 case MSR_IA32_BNDCFGS:
1331 has_msr_bndcfgs = true;
1332 break;
1333 case MSR_IA32_XSS:
1334 has_msr_xss = true;
1335 break;
1336 case HV_X64_MSR_CRASH_CTL:
1337 has_msr_hv_crash = true;
1338 break;
1339 case HV_X64_MSR_RESET:
1340 has_msr_hv_reset = true;
1341 break;
1342 case HV_X64_MSR_VP_INDEX:
1343 has_msr_hv_vpindex = true;
1344 break;
1345 case HV_X64_MSR_VP_RUNTIME:
1346 has_msr_hv_runtime = true;
1347 break;
1348 case HV_X64_MSR_SCONTROL:
1349 has_msr_hv_synic = true;
1350 break;
1351 case HV_X64_MSR_STIMER0_CONFIG:
1352 has_msr_hv_stimer = true;
1353 break;
1354 case HV_X64_MSR_TSC_FREQUENCY:
1355 has_msr_hv_frequencies = true;
1356 break;
1357 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1358 has_msr_hv_reenlightenment = true;
1359 break;
1360 case MSR_IA32_SPEC_CTRL:
1361 has_msr_spec_ctrl = true;
1362 break;
1363 case MSR_VIRT_SSBD:
1364 has_msr_virt_ssbd = true;
1365 break;
1366 }
1367 }
1368 }
1369
1370 g_free(kvm_msr_list);
1371 }
1372
1373 return ret;
1374 }
1375
1376 static Notifier smram_machine_done;
1377 static KVMMemoryListener smram_listener;
1378 static AddressSpace smram_address_space;
1379 static MemoryRegion smram_as_root;
1380 static MemoryRegion smram_as_mem;
1381
1382 static void register_smram_listener(Notifier *n, void *unused)
1383 {
1384 MemoryRegion *smram =
1385 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1386
1387 /* Outer container... */
1388 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1389 memory_region_set_enabled(&smram_as_root, true);
1390
1391 /* ... with two regions inside: normal system memory with low
1392 * priority, and...
1393 */
1394 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1395 get_system_memory(), 0, ~0ull);
1396 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1397 memory_region_set_enabled(&smram_as_mem, true);
1398
1399 if (smram) {
1400 /* ... SMRAM with higher priority */
1401 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1402 memory_region_set_enabled(smram, true);
1403 }
1404
1405 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1406 kvm_memory_listener_register(kvm_state, &smram_listener,
1407 &smram_address_space, 1);
1408 }
1409
1410 int kvm_arch_init(MachineState *ms, KVMState *s)
1411 {
1412 uint64_t identity_base = 0xfffbc000;
1413 uint64_t shadow_mem;
1414 int ret;
1415 struct utsname utsname;
1416
1417 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1418 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1419 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1420
1421 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1422
1423 ret = kvm_get_supported_msrs(s);
1424 if (ret < 0) {
1425 return ret;
1426 }
1427
1428 uname(&utsname);
1429 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1430
1431 /*
1432 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1433 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1434 * Since these must be part of guest physical memory, we need to allocate
1435 * them, both by setting their start addresses in the kernel and by
1436 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1437 *
1438 * Older KVM versions may not support setting the identity map base. In
1439 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1440 * size.
1441 */
1442 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1443 /* Allows up to 16M BIOSes. */
1444 identity_base = 0xfeffc000;
1445
1446 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1447 if (ret < 0) {
1448 return ret;
1449 }
1450 }
1451
1452 /* Set TSS base one page after EPT identity map. */
1453 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1454 if (ret < 0) {
1455 return ret;
1456 }
1457
1458 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1459 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1460 if (ret < 0) {
1461 fprintf(stderr, "e820_add_entry() table is full\n");
1462 return ret;
1463 }
1464 qemu_register_reset(kvm_unpoison_all, NULL);
1465
1466 shadow_mem = machine_kvm_shadow_mem(ms);
1467 if (shadow_mem != -1) {
1468 shadow_mem /= 4096;
1469 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1470 if (ret < 0) {
1471 return ret;
1472 }
1473 }
1474
1475 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1476 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1477 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1478 smram_machine_done.notify = register_smram_listener;
1479 qemu_add_machine_init_done_notifier(&smram_machine_done);
1480 }
1481
1482 if (enable_cpu_pm) {
1483 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1484 int ret;
1485
1486 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1487 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1488 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1489 #endif
1490 if (disable_exits) {
1491 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1492 KVM_X86_DISABLE_EXITS_HLT |
1493 KVM_X86_DISABLE_EXITS_PAUSE);
1494 }
1495
1496 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1497 disable_exits);
1498 if (ret < 0) {
1499 error_report("kvm: guest stopping CPU not supported: %s",
1500 strerror(-ret));
1501 }
1502 }
1503
1504 return 0;
1505 }
1506
1507 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1508 {
1509 lhs->selector = rhs->selector;
1510 lhs->base = rhs->base;
1511 lhs->limit = rhs->limit;
1512 lhs->type = 3;
1513 lhs->present = 1;
1514 lhs->dpl = 3;
1515 lhs->db = 0;
1516 lhs->s = 1;
1517 lhs->l = 0;
1518 lhs->g = 0;
1519 lhs->avl = 0;
1520 lhs->unusable = 0;
1521 }
1522
1523 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1524 {
1525 unsigned flags = rhs->flags;
1526 lhs->selector = rhs->selector;
1527 lhs->base = rhs->base;
1528 lhs->limit = rhs->limit;
1529 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1530 lhs->present = (flags & DESC_P_MASK) != 0;
1531 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1532 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1533 lhs->s = (flags & DESC_S_MASK) != 0;
1534 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1535 lhs->g = (flags & DESC_G_MASK) != 0;
1536 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1537 lhs->unusable = !lhs->present;
1538 lhs->padding = 0;
1539 }
1540
1541 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1542 {
1543 lhs->selector = rhs->selector;
1544 lhs->base = rhs->base;
1545 lhs->limit = rhs->limit;
1546 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1547 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1548 (rhs->dpl << DESC_DPL_SHIFT) |
1549 (rhs->db << DESC_B_SHIFT) |
1550 (rhs->s * DESC_S_MASK) |
1551 (rhs->l << DESC_L_SHIFT) |
1552 (rhs->g * DESC_G_MASK) |
1553 (rhs->avl * DESC_AVL_MASK);
1554 }
1555
1556 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1557 {
1558 if (set) {
1559 *kvm_reg = *qemu_reg;
1560 } else {
1561 *qemu_reg = *kvm_reg;
1562 }
1563 }
1564
1565 static int kvm_getput_regs(X86CPU *cpu, int set)
1566 {
1567 CPUX86State *env = &cpu->env;
1568 struct kvm_regs regs;
1569 int ret = 0;
1570
1571 if (!set) {
1572 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1573 if (ret < 0) {
1574 return ret;
1575 }
1576 }
1577
1578 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1579 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1580 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1581 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1582 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1583 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1584 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1585 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1586 #ifdef TARGET_X86_64
1587 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1588 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1589 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1590 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1591 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1592 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1593 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1594 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1595 #endif
1596
1597 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1598 kvm_getput_reg(&regs.rip, &env->eip, set);
1599
1600 if (set) {
1601 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1602 }
1603
1604 return ret;
1605 }
1606
1607 static int kvm_put_fpu(X86CPU *cpu)
1608 {
1609 CPUX86State *env = &cpu->env;
1610 struct kvm_fpu fpu;
1611 int i;
1612
1613 memset(&fpu, 0, sizeof fpu);
1614 fpu.fsw = env->fpus & ~(7 << 11);
1615 fpu.fsw |= (env->fpstt & 7) << 11;
1616 fpu.fcw = env->fpuc;
1617 fpu.last_opcode = env->fpop;
1618 fpu.last_ip = env->fpip;
1619 fpu.last_dp = env->fpdp;
1620 for (i = 0; i < 8; ++i) {
1621 fpu.ftwx |= (!env->fptags[i]) << i;
1622 }
1623 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1624 for (i = 0; i < CPU_NB_REGS; i++) {
1625 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1626 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1627 }
1628 fpu.mxcsr = env->mxcsr;
1629
1630 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1631 }
1632
1633 #define XSAVE_FCW_FSW 0
1634 #define XSAVE_FTW_FOP 1
1635 #define XSAVE_CWD_RIP 2
1636 #define XSAVE_CWD_RDP 4
1637 #define XSAVE_MXCSR 6
1638 #define XSAVE_ST_SPACE 8
1639 #define XSAVE_XMM_SPACE 40
1640 #define XSAVE_XSTATE_BV 128
1641 #define XSAVE_YMMH_SPACE 144
1642 #define XSAVE_BNDREGS 240
1643 #define XSAVE_BNDCSR 256
1644 #define XSAVE_OPMASK 272
1645 #define XSAVE_ZMM_Hi256 288
1646 #define XSAVE_Hi16_ZMM 416
1647 #define XSAVE_PKRU 672
1648
1649 #define XSAVE_BYTE_OFFSET(word_offset) \
1650 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1651
1652 #define ASSERT_OFFSET(word_offset, field) \
1653 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1654 offsetof(X86XSaveArea, field))
1655
1656 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1657 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1658 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1659 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1660 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1661 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1662 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1663 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1664 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1665 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1666 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1667 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1668 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1669 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1670 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1671
1672 static int kvm_put_xsave(X86CPU *cpu)
1673 {
1674 CPUX86State *env = &cpu->env;
1675 X86XSaveArea *xsave = env->xsave_buf;
1676
1677 if (!has_xsave) {
1678 return kvm_put_fpu(cpu);
1679 }
1680 x86_cpu_xsave_all_areas(cpu, xsave);
1681
1682 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1683 }
1684
1685 static int kvm_put_xcrs(X86CPU *cpu)
1686 {
1687 CPUX86State *env = &cpu->env;
1688 struct kvm_xcrs xcrs = {};
1689
1690 if (!has_xcrs) {
1691 return 0;
1692 }
1693
1694 xcrs.nr_xcrs = 1;
1695 xcrs.flags = 0;
1696 xcrs.xcrs[0].xcr = 0;
1697 xcrs.xcrs[0].value = env->xcr0;
1698 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1699 }
1700
1701 static int kvm_put_sregs(X86CPU *cpu)
1702 {
1703 CPUX86State *env = &cpu->env;
1704 struct kvm_sregs sregs;
1705
1706 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1707 if (env->interrupt_injected >= 0) {
1708 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1709 (uint64_t)1 << (env->interrupt_injected % 64);
1710 }
1711
1712 if ((env->eflags & VM_MASK)) {
1713 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1714 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1715 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1716 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1717 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1718 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1719 } else {
1720 set_seg(&sregs.cs, &env->segs[R_CS]);
1721 set_seg(&sregs.ds, &env->segs[R_DS]);
1722 set_seg(&sregs.es, &env->segs[R_ES]);
1723 set_seg(&sregs.fs, &env->segs[R_FS]);
1724 set_seg(&sregs.gs, &env->segs[R_GS]);
1725 set_seg(&sregs.ss, &env->segs[R_SS]);
1726 }
1727
1728 set_seg(&sregs.tr, &env->tr);
1729 set_seg(&sregs.ldt, &env->ldt);
1730
1731 sregs.idt.limit = env->idt.limit;
1732 sregs.idt.base = env->idt.base;
1733 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1734 sregs.gdt.limit = env->gdt.limit;
1735 sregs.gdt.base = env->gdt.base;
1736 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1737
1738 sregs.cr0 = env->cr[0];
1739 sregs.cr2 = env->cr[2];
1740 sregs.cr3 = env->cr[3];
1741 sregs.cr4 = env->cr[4];
1742
1743 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1744 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1745
1746 sregs.efer = env->efer;
1747
1748 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1749 }
1750
1751 static void kvm_msr_buf_reset(X86CPU *cpu)
1752 {
1753 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1754 }
1755
1756 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1757 {
1758 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1759 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1760 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1761
1762 assert((void *)(entry + 1) <= limit);
1763
1764 entry->index = index;
1765 entry->reserved = 0;
1766 entry->data = value;
1767 msrs->nmsrs++;
1768 }
1769
1770 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1771 {
1772 kvm_msr_buf_reset(cpu);
1773 kvm_msr_entry_add(cpu, index, value);
1774
1775 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1776 }
1777
1778 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1779 {
1780 int ret;
1781
1782 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1783 assert(ret == 1);
1784 }
1785
1786 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1787 {
1788 CPUX86State *env = &cpu->env;
1789 int ret;
1790
1791 if (!has_msr_tsc_deadline) {
1792 return 0;
1793 }
1794
1795 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1796 if (ret < 0) {
1797 return ret;
1798 }
1799
1800 assert(ret == 1);
1801 return 0;
1802 }
1803
1804 /*
1805 * Provide a separate write service for the feature control MSR in order to
1806 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1807 * before writing any other state because forcibly leaving nested mode
1808 * invalidates the VCPU state.
1809 */
1810 static int kvm_put_msr_feature_control(X86CPU *cpu)
1811 {
1812 int ret;
1813
1814 if (!has_msr_feature_control) {
1815 return 0;
1816 }
1817
1818 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1819 cpu->env.msr_ia32_feature_control);
1820 if (ret < 0) {
1821 return ret;
1822 }
1823
1824 assert(ret == 1);
1825 return 0;
1826 }
1827
1828 static int kvm_put_msrs(X86CPU *cpu, int level)
1829 {
1830 CPUX86State *env = &cpu->env;
1831 int i;
1832 int ret;
1833
1834 kvm_msr_buf_reset(cpu);
1835
1836 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1837 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1838 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1839 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1840 if (has_msr_star) {
1841 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1842 }
1843 if (has_msr_hsave_pa) {
1844 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1845 }
1846 if (has_msr_tsc_aux) {
1847 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1848 }
1849 if (has_msr_tsc_adjust) {
1850 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1851 }
1852 if (has_msr_misc_enable) {
1853 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1854 env->msr_ia32_misc_enable);
1855 }
1856 if (has_msr_smbase) {
1857 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1858 }
1859 if (has_msr_smi_count) {
1860 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1861 }
1862 if (has_msr_bndcfgs) {
1863 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1864 }
1865 if (has_msr_xss) {
1866 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1867 }
1868 if (has_msr_spec_ctrl) {
1869 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1870 }
1871 if (has_msr_virt_ssbd) {
1872 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1873 }
1874
1875 #ifdef TARGET_X86_64
1876 if (lm_capable_kernel) {
1877 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1878 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1879 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1880 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1881 }
1882 #endif
1883
1884 /*
1885 * The following MSRs have side effects on the guest or are too heavy
1886 * for normal writeback. Limit them to reset or full state updates.
1887 */
1888 if (level >= KVM_PUT_RESET_STATE) {
1889 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1890 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1891 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1892 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1893 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1894 }
1895 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1896 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1897 }
1898 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1899 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1900 }
1901 if (has_architectural_pmu_version > 0) {
1902 if (has_architectural_pmu_version > 1) {
1903 /* Stop the counter. */
1904 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1905 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1906 }
1907
1908 /* Set the counter values. */
1909 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1910 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1911 env->msr_fixed_counters[i]);
1912 }
1913 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1914 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1915 env->msr_gp_counters[i]);
1916 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1917 env->msr_gp_evtsel[i]);
1918 }
1919 if (has_architectural_pmu_version > 1) {
1920 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1921 env->msr_global_status);
1922 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1923 env->msr_global_ovf_ctrl);
1924
1925 /* Now start the PMU. */
1926 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1927 env->msr_fixed_ctr_ctrl);
1928 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1929 env->msr_global_ctrl);
1930 }
1931 }
1932 /*
1933 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1934 * only sync them to KVM on the first cpu
1935 */
1936 if (current_cpu == first_cpu) {
1937 if (has_msr_hv_hypercall) {
1938 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1939 env->msr_hv_guest_os_id);
1940 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1941 env->msr_hv_hypercall);
1942 }
1943 if (cpu->hyperv_time) {
1944 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1945 env->msr_hv_tsc);
1946 }
1947 if (cpu->hyperv_reenlightenment) {
1948 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1949 env->msr_hv_reenlightenment_control);
1950 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1951 env->msr_hv_tsc_emulation_control);
1952 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1953 env->msr_hv_tsc_emulation_status);
1954 }
1955 }
1956 if (cpu->hyperv_vapic) {
1957 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1958 env->msr_hv_vapic);
1959 }
1960 if (has_msr_hv_crash) {
1961 int j;
1962
1963 for (j = 0; j < HV_CRASH_PARAMS; j++)
1964 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1965 env->msr_hv_crash_params[j]);
1966
1967 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1968 }
1969 if (has_msr_hv_runtime) {
1970 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1971 }
1972 if (cpu->hyperv_vpindex && hv_vpindex_settable) {
1973 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
1974 hyperv_vp_index(CPU(cpu)));
1975 }
1976 if (cpu->hyperv_synic) {
1977 int j;
1978
1979 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1980
1981 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1982 env->msr_hv_synic_control);
1983 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1984 env->msr_hv_synic_evt_page);
1985 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1986 env->msr_hv_synic_msg_page);
1987
1988 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1989 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1990 env->msr_hv_synic_sint[j]);
1991 }
1992 }
1993 if (has_msr_hv_stimer) {
1994 int j;
1995
1996 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1997 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1998 env->msr_hv_stimer_config[j]);
1999 }
2000
2001 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2002 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2003 env->msr_hv_stimer_count[j]);
2004 }
2005 }
2006 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2007 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2008
2009 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2010 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2011 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2012 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2013 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2014 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2015 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2016 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2017 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2018 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2019 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2020 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2021 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2022 /* The CPU GPs if we write to a bit above the physical limit of
2023 * the host CPU (and KVM emulates that)
2024 */
2025 uint64_t mask = env->mtrr_var[i].mask;
2026 mask &= phys_mask;
2027
2028 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2029 env->mtrr_var[i].base);
2030 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2031 }
2032 }
2033 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2034 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2035 0x14, 1, R_EAX) & 0x7;
2036
2037 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2038 env->msr_rtit_ctrl);
2039 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2040 env->msr_rtit_status);
2041 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2042 env->msr_rtit_output_base);
2043 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2044 env->msr_rtit_output_mask);
2045 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2046 env->msr_rtit_cr3_match);
2047 for (i = 0; i < addr_num; i++) {
2048 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2049 env->msr_rtit_addrs[i]);
2050 }
2051 }
2052
2053 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2054 * kvm_put_msr_feature_control. */
2055 }
2056 if (env->mcg_cap) {
2057 int i;
2058
2059 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2060 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2061 if (has_msr_mcg_ext_ctl) {
2062 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2063 }
2064 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2065 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2066 }
2067 }
2068
2069 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2070 if (ret < 0) {
2071 return ret;
2072 }
2073
2074 if (ret < cpu->kvm_msr_buf->nmsrs) {
2075 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2076 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2077 (uint32_t)e->index, (uint64_t)e->data);
2078 }
2079
2080 assert(ret == cpu->kvm_msr_buf->nmsrs);
2081 return 0;
2082 }
2083
2084
2085 static int kvm_get_fpu(X86CPU *cpu)
2086 {
2087 CPUX86State *env = &cpu->env;
2088 struct kvm_fpu fpu;
2089 int i, ret;
2090
2091 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2092 if (ret < 0) {
2093 return ret;
2094 }
2095
2096 env->fpstt = (fpu.fsw >> 11) & 7;
2097 env->fpus = fpu.fsw;
2098 env->fpuc = fpu.fcw;
2099 env->fpop = fpu.last_opcode;
2100 env->fpip = fpu.last_ip;
2101 env->fpdp = fpu.last_dp;
2102 for (i = 0; i < 8; ++i) {
2103 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2104 }
2105 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2106 for (i = 0; i < CPU_NB_REGS; i++) {
2107 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2108 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2109 }
2110 env->mxcsr = fpu.mxcsr;
2111
2112 return 0;
2113 }
2114
2115 static int kvm_get_xsave(X86CPU *cpu)
2116 {
2117 CPUX86State *env = &cpu->env;
2118 X86XSaveArea *xsave = env->xsave_buf;
2119 int ret;
2120
2121 if (!has_xsave) {
2122 return kvm_get_fpu(cpu);
2123 }
2124
2125 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2126 if (ret < 0) {
2127 return ret;
2128 }
2129 x86_cpu_xrstor_all_areas(cpu, xsave);
2130
2131 return 0;
2132 }
2133
2134 static int kvm_get_xcrs(X86CPU *cpu)
2135 {
2136 CPUX86State *env = &cpu->env;
2137 int i, ret;
2138 struct kvm_xcrs xcrs;
2139
2140 if (!has_xcrs) {
2141 return 0;
2142 }
2143
2144 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2145 if (ret < 0) {
2146 return ret;
2147 }
2148
2149 for (i = 0; i < xcrs.nr_xcrs; i++) {
2150 /* Only support xcr0 now */
2151 if (xcrs.xcrs[i].xcr == 0) {
2152 env->xcr0 = xcrs.xcrs[i].value;
2153 break;
2154 }
2155 }
2156 return 0;
2157 }
2158
2159 static int kvm_get_sregs(X86CPU *cpu)
2160 {
2161 CPUX86State *env = &cpu->env;
2162 struct kvm_sregs sregs;
2163 int bit, i, ret;
2164
2165 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2166 if (ret < 0) {
2167 return ret;
2168 }
2169
2170 /* There can only be one pending IRQ set in the bitmap at a time, so try
2171 to find it and save its number instead (-1 for none). */
2172 env->interrupt_injected = -1;
2173 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2174 if (sregs.interrupt_bitmap[i]) {
2175 bit = ctz64(sregs.interrupt_bitmap[i]);
2176 env->interrupt_injected = i * 64 + bit;
2177 break;
2178 }
2179 }
2180
2181 get_seg(&env->segs[R_CS], &sregs.cs);
2182 get_seg(&env->segs[R_DS], &sregs.ds);
2183 get_seg(&env->segs[R_ES], &sregs.es);
2184 get_seg(&env->segs[R_FS], &sregs.fs);
2185 get_seg(&env->segs[R_GS], &sregs.gs);
2186 get_seg(&env->segs[R_SS], &sregs.ss);
2187
2188 get_seg(&env->tr, &sregs.tr);
2189 get_seg(&env->ldt, &sregs.ldt);
2190
2191 env->idt.limit = sregs.idt.limit;
2192 env->idt.base = sregs.idt.base;
2193 env->gdt.limit = sregs.gdt.limit;
2194 env->gdt.base = sregs.gdt.base;
2195
2196 env->cr[0] = sregs.cr0;
2197 env->cr[2] = sregs.cr2;
2198 env->cr[3] = sregs.cr3;
2199 env->cr[4] = sregs.cr4;
2200
2201 env->efer = sregs.efer;
2202
2203 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2204 x86_update_hflags(env);
2205
2206 return 0;
2207 }
2208
2209 static int kvm_get_msrs(X86CPU *cpu)
2210 {
2211 CPUX86State *env = &cpu->env;
2212 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2213 int ret, i;
2214 uint64_t mtrr_top_bits;
2215
2216 kvm_msr_buf_reset(cpu);
2217
2218 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2219 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2220 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2221 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2222 if (has_msr_star) {
2223 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2224 }
2225 if (has_msr_hsave_pa) {
2226 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2227 }
2228 if (has_msr_tsc_aux) {
2229 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2230 }
2231 if (has_msr_tsc_adjust) {
2232 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2233 }
2234 if (has_msr_tsc_deadline) {
2235 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2236 }
2237 if (has_msr_misc_enable) {
2238 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2239 }
2240 if (has_msr_smbase) {
2241 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2242 }
2243 if (has_msr_smi_count) {
2244 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2245 }
2246 if (has_msr_feature_control) {
2247 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2248 }
2249 if (has_msr_bndcfgs) {
2250 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2251 }
2252 if (has_msr_xss) {
2253 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2254 }
2255 if (has_msr_spec_ctrl) {
2256 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2257 }
2258 if (has_msr_virt_ssbd) {
2259 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2260 }
2261 if (!env->tsc_valid) {
2262 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2263 env->tsc_valid = !runstate_is_running();
2264 }
2265
2266 #ifdef TARGET_X86_64
2267 if (lm_capable_kernel) {
2268 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2269 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2270 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2271 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2272 }
2273 #endif
2274 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2275 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2276 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2277 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2278 }
2279 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2280 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2281 }
2282 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2283 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2284 }
2285 if (has_architectural_pmu_version > 0) {
2286 if (has_architectural_pmu_version > 1) {
2287 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2288 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2289 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2290 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2291 }
2292 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2293 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2294 }
2295 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2296 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2297 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2298 }
2299 }
2300
2301 if (env->mcg_cap) {
2302 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2303 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2304 if (has_msr_mcg_ext_ctl) {
2305 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2306 }
2307 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2308 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2309 }
2310 }
2311
2312 if (has_msr_hv_hypercall) {
2313 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2314 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2315 }
2316 if (cpu->hyperv_vapic) {
2317 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2318 }
2319 if (cpu->hyperv_time) {
2320 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2321 }
2322 if (cpu->hyperv_reenlightenment) {
2323 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2324 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2325 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2326 }
2327 if (has_msr_hv_crash) {
2328 int j;
2329
2330 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2331 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2332 }
2333 }
2334 if (has_msr_hv_runtime) {
2335 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2336 }
2337 if (cpu->hyperv_synic) {
2338 uint32_t msr;
2339
2340 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2341 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2342 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2343 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2344 kvm_msr_entry_add(cpu, msr, 0);
2345 }
2346 }
2347 if (has_msr_hv_stimer) {
2348 uint32_t msr;
2349
2350 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2351 msr++) {
2352 kvm_msr_entry_add(cpu, msr, 0);
2353 }
2354 }
2355 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2356 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2357 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2358 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2359 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2360 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2361 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2362 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2363 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2364 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2365 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2366 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2367 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2368 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2369 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2370 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2371 }
2372 }
2373
2374 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2375 int addr_num =
2376 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2377
2378 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2379 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2380 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2381 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2382 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2383 for (i = 0; i < addr_num; i++) {
2384 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2385 }
2386 }
2387
2388 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2389 if (ret < 0) {
2390 return ret;
2391 }
2392
2393 if (ret < cpu->kvm_msr_buf->nmsrs) {
2394 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2395 error_report("error: failed to get MSR 0x%" PRIx32,
2396 (uint32_t)e->index);
2397 }
2398
2399 assert(ret == cpu->kvm_msr_buf->nmsrs);
2400 /*
2401 * MTRR masks: Each mask consists of 5 parts
2402 * a 10..0: must be zero
2403 * b 11 : valid bit
2404 * c n-1.12: actual mask bits
2405 * d 51..n: reserved must be zero
2406 * e 63.52: reserved must be zero
2407 *
2408 * 'n' is the number of physical bits supported by the CPU and is
2409 * apparently always <= 52. We know our 'n' but don't know what
2410 * the destinations 'n' is; it might be smaller, in which case
2411 * it masks (c) on loading. It might be larger, in which case
2412 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2413 * we're migrating to.
2414 */
2415
2416 if (cpu->fill_mtrr_mask) {
2417 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2418 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2419 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2420 } else {
2421 mtrr_top_bits = 0;
2422 }
2423
2424 for (i = 0; i < ret; i++) {
2425 uint32_t index = msrs[i].index;
2426 switch (index) {
2427 case MSR_IA32_SYSENTER_CS:
2428 env->sysenter_cs = msrs[i].data;
2429 break;
2430 case MSR_IA32_SYSENTER_ESP:
2431 env->sysenter_esp = msrs[i].data;
2432 break;
2433 case MSR_IA32_SYSENTER_EIP:
2434 env->sysenter_eip = msrs[i].data;
2435 break;
2436 case MSR_PAT:
2437 env->pat = msrs[i].data;
2438 break;
2439 case MSR_STAR:
2440 env->star = msrs[i].data;
2441 break;
2442 #ifdef TARGET_X86_64
2443 case MSR_CSTAR:
2444 env->cstar = msrs[i].data;
2445 break;
2446 case MSR_KERNELGSBASE:
2447 env->kernelgsbase = msrs[i].data;
2448 break;
2449 case MSR_FMASK:
2450 env->fmask = msrs[i].data;
2451 break;
2452 case MSR_LSTAR:
2453 env->lstar = msrs[i].data;
2454 break;
2455 #endif
2456 case MSR_IA32_TSC:
2457 env->tsc = msrs[i].data;
2458 break;
2459 case MSR_TSC_AUX:
2460 env->tsc_aux = msrs[i].data;
2461 break;
2462 case MSR_TSC_ADJUST:
2463 env->tsc_adjust = msrs[i].data;
2464 break;
2465 case MSR_IA32_TSCDEADLINE:
2466 env->tsc_deadline = msrs[i].data;
2467 break;
2468 case MSR_VM_HSAVE_PA:
2469 env->vm_hsave = msrs[i].data;
2470 break;
2471 case MSR_KVM_SYSTEM_TIME:
2472 env->system_time_msr = msrs[i].data;
2473 break;
2474 case MSR_KVM_WALL_CLOCK:
2475 env->wall_clock_msr = msrs[i].data;
2476 break;
2477 case MSR_MCG_STATUS:
2478 env->mcg_status = msrs[i].data;
2479 break;
2480 case MSR_MCG_CTL:
2481 env->mcg_ctl = msrs[i].data;
2482 break;
2483 case MSR_MCG_EXT_CTL:
2484 env->mcg_ext_ctl = msrs[i].data;
2485 break;
2486 case MSR_IA32_MISC_ENABLE:
2487 env->msr_ia32_misc_enable = msrs[i].data;
2488 break;
2489 case MSR_IA32_SMBASE:
2490 env->smbase = msrs[i].data;
2491 break;
2492 case MSR_SMI_COUNT:
2493 env->msr_smi_count = msrs[i].data;
2494 break;
2495 case MSR_IA32_FEATURE_CONTROL:
2496 env->msr_ia32_feature_control = msrs[i].data;
2497 break;
2498 case MSR_IA32_BNDCFGS:
2499 env->msr_bndcfgs = msrs[i].data;
2500 break;
2501 case MSR_IA32_XSS:
2502 env->xss = msrs[i].data;
2503 break;
2504 default:
2505 if (msrs[i].index >= MSR_MC0_CTL &&
2506 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2507 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2508 }
2509 break;
2510 case MSR_KVM_ASYNC_PF_EN:
2511 env->async_pf_en_msr = msrs[i].data;
2512 break;
2513 case MSR_KVM_PV_EOI_EN:
2514 env->pv_eoi_en_msr = msrs[i].data;
2515 break;
2516 case MSR_KVM_STEAL_TIME:
2517 env->steal_time_msr = msrs[i].data;
2518 break;
2519 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2520 env->msr_fixed_ctr_ctrl = msrs[i].data;
2521 break;
2522 case MSR_CORE_PERF_GLOBAL_CTRL:
2523 env->msr_global_ctrl = msrs[i].data;
2524 break;
2525 case MSR_CORE_PERF_GLOBAL_STATUS:
2526 env->msr_global_status = msrs[i].data;
2527 break;
2528 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2529 env->msr_global_ovf_ctrl = msrs[i].data;
2530 break;
2531 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2532 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2533 break;
2534 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2535 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2536 break;
2537 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2538 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2539 break;
2540 case HV_X64_MSR_HYPERCALL:
2541 env->msr_hv_hypercall = msrs[i].data;
2542 break;
2543 case HV_X64_MSR_GUEST_OS_ID:
2544 env->msr_hv_guest_os_id = msrs[i].data;
2545 break;
2546 case HV_X64_MSR_APIC_ASSIST_PAGE:
2547 env->msr_hv_vapic = msrs[i].data;
2548 break;
2549 case HV_X64_MSR_REFERENCE_TSC:
2550 env->msr_hv_tsc = msrs[i].data;
2551 break;
2552 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2553 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2554 break;
2555 case HV_X64_MSR_VP_RUNTIME:
2556 env->msr_hv_runtime = msrs[i].data;
2557 break;
2558 case HV_X64_MSR_SCONTROL:
2559 env->msr_hv_synic_control = msrs[i].data;
2560 break;
2561 case HV_X64_MSR_SIEFP:
2562 env->msr_hv_synic_evt_page = msrs[i].data;
2563 break;
2564 case HV_X64_MSR_SIMP:
2565 env->msr_hv_synic_msg_page = msrs[i].data;
2566 break;
2567 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2568 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2569 break;
2570 case HV_X64_MSR_STIMER0_CONFIG:
2571 case HV_X64_MSR_STIMER1_CONFIG:
2572 case HV_X64_MSR_STIMER2_CONFIG:
2573 case HV_X64_MSR_STIMER3_CONFIG:
2574 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2575 msrs[i].data;
2576 break;
2577 case HV_X64_MSR_STIMER0_COUNT:
2578 case HV_X64_MSR_STIMER1_COUNT:
2579 case HV_X64_MSR_STIMER2_COUNT:
2580 case HV_X64_MSR_STIMER3_COUNT:
2581 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2582 msrs[i].data;
2583 break;
2584 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2585 env->msr_hv_reenlightenment_control = msrs[i].data;
2586 break;
2587 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2588 env->msr_hv_tsc_emulation_control = msrs[i].data;
2589 break;
2590 case HV_X64_MSR_TSC_EMULATION_STATUS:
2591 env->msr_hv_tsc_emulation_status = msrs[i].data;
2592 break;
2593 case MSR_MTRRdefType:
2594 env->mtrr_deftype = msrs[i].data;
2595 break;
2596 case MSR_MTRRfix64K_00000:
2597 env->mtrr_fixed[0] = msrs[i].data;
2598 break;
2599 case MSR_MTRRfix16K_80000:
2600 env->mtrr_fixed[1] = msrs[i].data;
2601 break;
2602 case MSR_MTRRfix16K_A0000:
2603 env->mtrr_fixed[2] = msrs[i].data;
2604 break;
2605 case MSR_MTRRfix4K_C0000:
2606 env->mtrr_fixed[3] = msrs[i].data;
2607 break;
2608 case MSR_MTRRfix4K_C8000:
2609 env->mtrr_fixed[4] = msrs[i].data;
2610 break;
2611 case MSR_MTRRfix4K_D0000:
2612 env->mtrr_fixed[5] = msrs[i].data;
2613 break;
2614 case MSR_MTRRfix4K_D8000:
2615 env->mtrr_fixed[6] = msrs[i].data;
2616 break;
2617 case MSR_MTRRfix4K_E0000:
2618 env->mtrr_fixed[7] = msrs[i].data;
2619 break;
2620 case MSR_MTRRfix4K_E8000:
2621 env->mtrr_fixed[8] = msrs[i].data;
2622 break;
2623 case MSR_MTRRfix4K_F0000:
2624 env->mtrr_fixed[9] = msrs[i].data;
2625 break;
2626 case MSR_MTRRfix4K_F8000:
2627 env->mtrr_fixed[10] = msrs[i].data;
2628 break;
2629 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2630 if (index & 1) {
2631 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2632 mtrr_top_bits;
2633 } else {
2634 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2635 }
2636 break;
2637 case MSR_IA32_SPEC_CTRL:
2638 env->spec_ctrl = msrs[i].data;
2639 break;
2640 case MSR_VIRT_SSBD:
2641 env->virt_ssbd = msrs[i].data;
2642 break;
2643 case MSR_IA32_RTIT_CTL:
2644 env->msr_rtit_ctrl = msrs[i].data;
2645 break;
2646 case MSR_IA32_RTIT_STATUS:
2647 env->msr_rtit_status = msrs[i].data;
2648 break;
2649 case MSR_IA32_RTIT_OUTPUT_BASE:
2650 env->msr_rtit_output_base = msrs[i].data;
2651 break;
2652 case MSR_IA32_RTIT_OUTPUT_MASK:
2653 env->msr_rtit_output_mask = msrs[i].data;
2654 break;
2655 case MSR_IA32_RTIT_CR3_MATCH:
2656 env->msr_rtit_cr3_match = msrs[i].data;
2657 break;
2658 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2659 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2660 break;
2661 }
2662 }
2663
2664 return 0;
2665 }
2666
2667 static int kvm_put_mp_state(X86CPU *cpu)
2668 {
2669 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2670
2671 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2672 }
2673
2674 static int kvm_get_mp_state(X86CPU *cpu)
2675 {
2676 CPUState *cs = CPU(cpu);
2677 CPUX86State *env = &cpu->env;
2678 struct kvm_mp_state mp_state;
2679 int ret;
2680
2681 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2682 if (ret < 0) {
2683 return ret;
2684 }
2685 env->mp_state = mp_state.mp_state;
2686 if (kvm_irqchip_in_kernel()) {
2687 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2688 }
2689 return 0;
2690 }
2691
2692 static int kvm_get_apic(X86CPU *cpu)
2693 {
2694 DeviceState *apic = cpu->apic_state;
2695 struct kvm_lapic_state kapic;
2696 int ret;
2697
2698 if (apic && kvm_irqchip_in_kernel()) {
2699 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2700 if (ret < 0) {
2701 return ret;
2702 }
2703
2704 kvm_get_apic_state(apic, &kapic);
2705 }
2706 return 0;
2707 }
2708
2709 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2710 {
2711 CPUState *cs = CPU(cpu);
2712 CPUX86State *env = &cpu->env;
2713 struct kvm_vcpu_events events = {};
2714
2715 if (!kvm_has_vcpu_events()) {
2716 return 0;
2717 }
2718
2719 events.exception.injected = (env->exception_injected >= 0);
2720 events.exception.nr = env->exception_injected;
2721 events.exception.has_error_code = env->has_error_code;
2722 events.exception.error_code = env->error_code;
2723
2724 events.interrupt.injected = (env->interrupt_injected >= 0);
2725 events.interrupt.nr = env->interrupt_injected;
2726 events.interrupt.soft = env->soft_interrupt;
2727
2728 events.nmi.injected = env->nmi_injected;
2729 events.nmi.pending = env->nmi_pending;
2730 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2731
2732 events.sipi_vector = env->sipi_vector;
2733 events.flags = 0;
2734
2735 if (has_msr_smbase) {
2736 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2737 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2738 if (kvm_irqchip_in_kernel()) {
2739 /* As soon as these are moved to the kernel, remove them
2740 * from cs->interrupt_request.
2741 */
2742 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2743 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2744 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2745 } else {
2746 /* Keep these in cs->interrupt_request. */
2747 events.smi.pending = 0;
2748 events.smi.latched_init = 0;
2749 }
2750 /* Stop SMI delivery on old machine types to avoid a reboot
2751 * on an inward migration of an old VM.
2752 */
2753 if (!cpu->kvm_no_smi_migration) {
2754 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2755 }
2756 }
2757
2758 if (level >= KVM_PUT_RESET_STATE) {
2759 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2760 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2761 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2762 }
2763 }
2764
2765 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2766 }
2767
2768 static int kvm_get_vcpu_events(X86CPU *cpu)
2769 {
2770 CPUX86State *env = &cpu->env;
2771 struct kvm_vcpu_events events;
2772 int ret;
2773
2774 if (!kvm_has_vcpu_events()) {
2775 return 0;
2776 }
2777
2778 memset(&events, 0, sizeof(events));
2779 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2780 if (ret < 0) {
2781 return ret;
2782 }
2783 env->exception_injected =
2784 events.exception.injected ? events.exception.nr : -1;
2785 env->has_error_code = events.exception.has_error_code;
2786 env->error_code = events.exception.error_code;
2787
2788 env->interrupt_injected =
2789 events.interrupt.injected ? events.interrupt.nr : -1;
2790 env->soft_interrupt = events.interrupt.soft;
2791
2792 env->nmi_injected = events.nmi.injected;
2793 env->nmi_pending = events.nmi.pending;
2794 if (events.nmi.masked) {
2795 env->hflags2 |= HF2_NMI_MASK;
2796 } else {
2797 env->hflags2 &= ~HF2_NMI_MASK;
2798 }
2799
2800 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2801 if (events.smi.smm) {
2802 env->hflags |= HF_SMM_MASK;
2803 } else {
2804 env->hflags &= ~HF_SMM_MASK;
2805 }
2806 if (events.smi.pending) {
2807 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2808 } else {
2809 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2810 }
2811 if (events.smi.smm_inside_nmi) {
2812 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2813 } else {
2814 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2815 }
2816 if (events.smi.latched_init) {
2817 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2818 } else {
2819 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2820 }
2821 }
2822
2823 env->sipi_vector = events.sipi_vector;
2824
2825 return 0;
2826 }
2827
2828 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2829 {
2830 CPUState *cs = CPU(cpu);
2831 CPUX86State *env = &cpu->env;
2832 int ret = 0;
2833 unsigned long reinject_trap = 0;
2834
2835 if (!kvm_has_vcpu_events()) {
2836 if (env->exception_injected == 1) {
2837 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2838 } else if (env->exception_injected == 3) {
2839 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2840 }
2841 env->exception_injected = -1;
2842 }
2843
2844 /*
2845 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2846 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2847 * by updating the debug state once again if single-stepping is on.
2848 * Another reason to call kvm_update_guest_debug here is a pending debug
2849 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2850 * reinject them via SET_GUEST_DEBUG.
2851 */
2852 if (reinject_trap ||
2853 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2854 ret = kvm_update_guest_debug(cs, reinject_trap);
2855 }
2856 return ret;
2857 }
2858
2859 static int kvm_put_debugregs(X86CPU *cpu)
2860 {
2861 CPUX86State *env = &cpu->env;
2862 struct kvm_debugregs dbgregs;
2863 int i;
2864
2865 if (!kvm_has_debugregs()) {
2866 return 0;
2867 }
2868
2869 for (i = 0; i < 4; i++) {
2870 dbgregs.db[i] = env->dr[i];
2871 }
2872 dbgregs.dr6 = env->dr[6];
2873 dbgregs.dr7 = env->dr[7];
2874 dbgregs.flags = 0;
2875
2876 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2877 }
2878
2879 static int kvm_get_debugregs(X86CPU *cpu)
2880 {
2881 CPUX86State *env = &cpu->env;
2882 struct kvm_debugregs dbgregs;
2883 int i, ret;
2884
2885 if (!kvm_has_debugregs()) {
2886 return 0;
2887 }
2888
2889 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2890 if (ret < 0) {
2891 return ret;
2892 }
2893 for (i = 0; i < 4; i++) {
2894 env->dr[i] = dbgregs.db[i];
2895 }
2896 env->dr[4] = env->dr[6] = dbgregs.dr6;
2897 env->dr[5] = env->dr[7] = dbgregs.dr7;
2898
2899 return 0;
2900 }
2901
2902 int kvm_arch_put_registers(CPUState *cpu, int level)
2903 {
2904 X86CPU *x86_cpu = X86_CPU(cpu);
2905 int ret;
2906
2907 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2908
2909 if (level >= KVM_PUT_RESET_STATE) {
2910 ret = kvm_put_msr_feature_control(x86_cpu);
2911 if (ret < 0) {
2912 return ret;
2913 }
2914 }
2915
2916 if (level == KVM_PUT_FULL_STATE) {
2917 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2918 * because TSC frequency mismatch shouldn't abort migration,
2919 * unless the user explicitly asked for a more strict TSC
2920 * setting (e.g. using an explicit "tsc-freq" option).
2921 */
2922 kvm_arch_set_tsc_khz(cpu);
2923 }
2924
2925 ret = kvm_getput_regs(x86_cpu, 1);
2926 if (ret < 0) {
2927 return ret;
2928 }
2929 ret = kvm_put_xsave(x86_cpu);
2930 if (ret < 0) {
2931 return ret;
2932 }
2933 ret = kvm_put_xcrs(x86_cpu);
2934 if (ret < 0) {
2935 return ret;
2936 }
2937 ret = kvm_put_sregs(x86_cpu);
2938 if (ret < 0) {
2939 return ret;
2940 }
2941 /* must be before kvm_put_msrs */
2942 ret = kvm_inject_mce_oldstyle(x86_cpu);
2943 if (ret < 0) {
2944 return ret;
2945 }
2946 ret = kvm_put_msrs(x86_cpu, level);
2947 if (ret < 0) {
2948 return ret;
2949 }
2950 ret = kvm_put_vcpu_events(x86_cpu, level);
2951 if (ret < 0) {
2952 return ret;
2953 }
2954 if (level >= KVM_PUT_RESET_STATE) {
2955 ret = kvm_put_mp_state(x86_cpu);
2956 if (ret < 0) {
2957 return ret;
2958 }
2959 }
2960
2961 ret = kvm_put_tscdeadline_msr(x86_cpu);
2962 if (ret < 0) {
2963 return ret;
2964 }
2965 ret = kvm_put_debugregs(x86_cpu);
2966 if (ret < 0) {
2967 return ret;
2968 }
2969 /* must be last */
2970 ret = kvm_guest_debug_workarounds(x86_cpu);
2971 if (ret < 0) {
2972 return ret;
2973 }
2974 return 0;
2975 }
2976
2977 int kvm_arch_get_registers(CPUState *cs)
2978 {
2979 X86CPU *cpu = X86_CPU(cs);
2980 int ret;
2981
2982 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2983
2984 ret = kvm_get_vcpu_events(cpu);
2985 if (ret < 0) {
2986 goto out;
2987 }
2988 /*
2989 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2990 * KVM_GET_REGS and KVM_GET_SREGS.
2991 */
2992 ret = kvm_get_mp_state(cpu);
2993 if (ret < 0) {
2994 goto out;
2995 }
2996 ret = kvm_getput_regs(cpu, 0);
2997 if (ret < 0) {
2998 goto out;
2999 }
3000 ret = kvm_get_xsave(cpu);
3001 if (ret < 0) {
3002 goto out;
3003 }
3004 ret = kvm_get_xcrs(cpu);
3005 if (ret < 0) {
3006 goto out;
3007 }
3008 ret = kvm_get_sregs(cpu);
3009 if (ret < 0) {
3010 goto out;
3011 }
3012 ret = kvm_get_msrs(cpu);
3013 if (ret < 0) {
3014 goto out;
3015 }
3016 ret = kvm_get_apic(cpu);
3017 if (ret < 0) {
3018 goto out;
3019 }
3020 ret = kvm_get_debugregs(cpu);
3021 if (ret < 0) {
3022 goto out;
3023 }
3024 ret = 0;
3025 out:
3026 cpu_sync_bndcs_hflags(&cpu->env);
3027 return ret;
3028 }
3029
3030 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3031 {
3032 X86CPU *x86_cpu = X86_CPU(cpu);
3033 CPUX86State *env = &x86_cpu->env;
3034 int ret;
3035
3036 /* Inject NMI */
3037 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3038 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3039 qemu_mutex_lock_iothread();
3040 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3041 qemu_mutex_unlock_iothread();
3042 DPRINTF("injected NMI\n");
3043 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3044 if (ret < 0) {
3045 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3046 strerror(-ret));
3047 }
3048 }
3049 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3050 qemu_mutex_lock_iothread();
3051 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3052 qemu_mutex_unlock_iothread();
3053 DPRINTF("injected SMI\n");
3054 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3055 if (ret < 0) {
3056 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3057 strerror(-ret));
3058 }
3059 }
3060 }
3061
3062 if (!kvm_pic_in_kernel()) {
3063 qemu_mutex_lock_iothread();
3064 }
3065
3066 /* Force the VCPU out of its inner loop to process any INIT requests
3067 * or (for userspace APIC, but it is cheap to combine the checks here)
3068 * pending TPR access reports.
3069 */
3070 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3071 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3072 !(env->hflags & HF_SMM_MASK)) {
3073 cpu->exit_request = 1;
3074 }
3075 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3076 cpu->exit_request = 1;
3077 }
3078 }
3079
3080 if (!kvm_pic_in_kernel()) {
3081 /* Try to inject an interrupt if the guest can accept it */
3082 if (run->ready_for_interrupt_injection &&
3083 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3084 (env->eflags & IF_MASK)) {
3085 int irq;
3086
3087 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3088 irq = cpu_get_pic_interrupt(env);
3089 if (irq >= 0) {
3090 struct kvm_interrupt intr;
3091
3092 intr.irq = irq;
3093 DPRINTF("injected interrupt %d\n", irq);
3094 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3095 if (ret < 0) {
3096 fprintf(stderr,
3097 "KVM: injection failed, interrupt lost (%s)\n",
3098 strerror(-ret));
3099 }
3100 }
3101 }
3102
3103 /* If we have an interrupt but the guest is not ready to receive an
3104 * interrupt, request an interrupt window exit. This will
3105 * cause a return to userspace as soon as the guest is ready to
3106 * receive interrupts. */
3107 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3108 run->request_interrupt_window = 1;
3109 } else {
3110 run->request_interrupt_window = 0;
3111 }
3112
3113 DPRINTF("setting tpr\n");
3114 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3115
3116 qemu_mutex_unlock_iothread();
3117 }
3118 }
3119
3120 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3121 {
3122 X86CPU *x86_cpu = X86_CPU(cpu);
3123 CPUX86State *env = &x86_cpu->env;
3124
3125 if (run->flags & KVM_RUN_X86_SMM) {
3126 env->hflags |= HF_SMM_MASK;
3127 } else {
3128 env->hflags &= ~HF_SMM_MASK;
3129 }
3130 if (run->if_flag) {
3131 env->eflags |= IF_MASK;
3132 } else {
3133 env->eflags &= ~IF_MASK;
3134 }
3135
3136 /* We need to protect the apic state against concurrent accesses from
3137 * different threads in case the userspace irqchip is used. */
3138 if (!kvm_irqchip_in_kernel()) {
3139 qemu_mutex_lock_iothread();
3140 }
3141 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3142 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3143 if (!kvm_irqchip_in_kernel()) {
3144 qemu_mutex_unlock_iothread();
3145 }
3146 return cpu_get_mem_attrs(env);
3147 }
3148
3149 int kvm_arch_process_async_events(CPUState *cs)
3150 {
3151 X86CPU *cpu = X86_CPU(cs);
3152 CPUX86State *env = &cpu->env;
3153
3154 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3155 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3156 assert(env->mcg_cap);
3157
3158 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3159
3160 kvm_cpu_synchronize_state(cs);
3161
3162 if (env->exception_injected == EXCP08_DBLE) {
3163 /* this means triple fault */
3164 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3165 cs->exit_request = 1;
3166 return 0;
3167 }
3168 env->exception_injected = EXCP12_MCHK;
3169 env->has_error_code = 0;
3170
3171 cs->halted = 0;
3172 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3173 env->mp_state = KVM_MP_STATE_RUNNABLE;
3174 }
3175 }
3176
3177 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3178 !(env->hflags & HF_SMM_MASK)) {
3179 kvm_cpu_synchronize_state(cs);
3180 do_cpu_init(cpu);
3181 }
3182
3183 if (kvm_irqchip_in_kernel()) {
3184 return 0;
3185 }
3186
3187 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3188 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3189 apic_poll_irq(cpu->apic_state);
3190 }
3191 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3192 (env->eflags & IF_MASK)) ||
3193 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3194 cs->halted = 0;
3195 }
3196 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3197 kvm_cpu_synchronize_state(cs);
3198 do_cpu_sipi(cpu);
3199 }
3200 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3201 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3202 kvm_cpu_synchronize_state(cs);
3203 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3204 env->tpr_access_type);
3205 }
3206
3207 return cs->halted;
3208 }
3209
3210 static int kvm_handle_halt(X86CPU *cpu)
3211 {
3212 CPUState *cs = CPU(cpu);
3213 CPUX86State *env = &cpu->env;
3214
3215 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3216 (env->eflags & IF_MASK)) &&
3217 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3218 cs->halted = 1;
3219 return EXCP_HLT;
3220 }
3221
3222 return 0;
3223 }
3224
3225 static int kvm_handle_tpr_access(X86CPU *cpu)
3226 {
3227 CPUState *cs = CPU(cpu);
3228 struct kvm_run *run = cs->kvm_run;
3229
3230 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3231 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3232 : TPR_ACCESS_READ);
3233 return 1;
3234 }
3235
3236 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3237 {
3238 static const uint8_t int3 = 0xcc;
3239
3240 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3241 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3242 return -EINVAL;
3243 }
3244 return 0;
3245 }
3246
3247 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3248 {
3249 uint8_t int3;
3250
3251 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3252 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3253 return -EINVAL;
3254 }
3255 return 0;
3256 }
3257
3258 static struct {
3259 target_ulong addr;
3260 int len;
3261 int type;
3262 } hw_breakpoint[4];
3263
3264 static int nb_hw_breakpoint;
3265
3266 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3267 {
3268 int n;
3269
3270 for (n = 0; n < nb_hw_breakpoint; n++) {
3271 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3272 (hw_breakpoint[n].len == len || len == -1)) {
3273 return n;
3274 }
3275 }
3276 return -1;
3277 }
3278
3279 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3280 target_ulong len, int type)
3281 {
3282 switch (type) {
3283 case GDB_BREAKPOINT_HW:
3284 len = 1;
3285 break;
3286 case GDB_WATCHPOINT_WRITE:
3287 case GDB_WATCHPOINT_ACCESS:
3288 switch (len) {
3289 case 1:
3290 break;
3291 case 2:
3292 case 4:
3293 case 8:
3294 if (addr & (len - 1)) {
3295 return -EINVAL;
3296 }
3297 break;
3298 default:
3299 return -EINVAL;
3300 }
3301 break;
3302 default:
3303 return -ENOSYS;
3304 }
3305
3306 if (nb_hw_breakpoint == 4) {
3307 return -ENOBUFS;
3308 }
3309 if (find_hw_breakpoint(addr, len, type) >= 0) {
3310 return -EEXIST;
3311 }
3312 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3313 hw_breakpoint[nb_hw_breakpoint].len = len;
3314 hw_breakpoint[nb_hw_breakpoint].type = type;
3315 nb_hw_breakpoint++;
3316
3317 return 0;
3318 }
3319
3320 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3321 target_ulong len, int type)
3322 {
3323 int n;
3324
3325 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3326 if (n < 0) {
3327 return -ENOENT;
3328 }
3329 nb_hw_breakpoint--;
3330 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3331
3332 return 0;
3333 }
3334
3335 void kvm_arch_remove_all_hw_breakpoints(void)
3336 {
3337 nb_hw_breakpoint = 0;
3338 }
3339
3340 static CPUWatchpoint hw_watchpoint;
3341
3342 static int kvm_handle_debug(X86CPU *cpu,
3343 struct kvm_debug_exit_arch *arch_info)
3344 {
3345 CPUState *cs = CPU(cpu);
3346 CPUX86State *env = &cpu->env;
3347 int ret = 0;
3348 int n;
3349
3350 if (arch_info->exception == 1) {
3351 if (arch_info->dr6 & (1 << 14)) {
3352 if (cs->singlestep_enabled) {
3353 ret = EXCP_DEBUG;
3354 }
3355 } else {
3356 for (n = 0; n < 4; n++) {
3357 if (arch_info->dr6 & (1 << n)) {
3358 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3359 case 0x0:
3360 ret = EXCP_DEBUG;
3361 break;
3362 case 0x1:
3363 ret = EXCP_DEBUG;
3364 cs->watchpoint_hit = &hw_watchpoint;
3365 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3366 hw_watchpoint.flags = BP_MEM_WRITE;
3367 break;
3368 case 0x3:
3369 ret = EXCP_DEBUG;
3370 cs->watchpoint_hit = &hw_watchpoint;
3371 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3372 hw_watchpoint.flags = BP_MEM_ACCESS;
3373 break;
3374 }
3375 }
3376 }
3377 }
3378 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3379 ret = EXCP_DEBUG;
3380 }
3381 if (ret == 0) {
3382 cpu_synchronize_state(cs);
3383 assert(env->exception_injected == -1);
3384
3385 /* pass to guest */
3386 env->exception_injected = arch_info->exception;
3387 env->has_error_code = 0;
3388 }
3389
3390 return ret;
3391 }
3392
3393 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3394 {
3395 const uint8_t type_code[] = {
3396 [GDB_BREAKPOINT_HW] = 0x0,
3397 [GDB_WATCHPOINT_WRITE] = 0x1,
3398 [GDB_WATCHPOINT_ACCESS] = 0x3
3399 };
3400 const uint8_t len_code[] = {
3401 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3402 };
3403 int n;
3404
3405 if (kvm_sw_breakpoints_active(cpu)) {
3406 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3407 }
3408 if (nb_hw_breakpoint > 0) {
3409 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3410 dbg->arch.debugreg[7] = 0x0600;
3411 for (n = 0; n < nb_hw_breakpoint; n++) {
3412 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3413 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3414 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3415 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3416 }
3417 }
3418 }
3419
3420 static bool host_supports_vmx(void)
3421 {
3422 uint32_t ecx, unused;
3423
3424 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3425 return ecx & CPUID_EXT_VMX;
3426 }
3427
3428 #define VMX_INVALID_GUEST_STATE 0x80000021
3429
3430 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3431 {
3432 X86CPU *cpu = X86_CPU(cs);
3433 uint64_t code;
3434 int ret;
3435
3436 switch (run->exit_reason) {
3437 case KVM_EXIT_HLT:
3438 DPRINTF("handle_hlt\n");
3439 qemu_mutex_lock_iothread();
3440 ret = kvm_handle_halt(cpu);
3441 qemu_mutex_unlock_iothread();
3442 break;
3443 case KVM_EXIT_SET_TPR:
3444 ret = 0;
3445 break;
3446 case KVM_EXIT_TPR_ACCESS:
3447 qemu_mutex_lock_iothread();
3448 ret = kvm_handle_tpr_access(cpu);
3449 qemu_mutex_unlock_iothread();
3450 break;
3451 case KVM_EXIT_FAIL_ENTRY:
3452 code = run->fail_entry.hardware_entry_failure_reason;
3453 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3454 code);
3455 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3456 fprintf(stderr,
3457 "\nIf you're running a guest on an Intel machine without "
3458 "unrestricted mode\n"
3459 "support, the failure can be most likely due to the guest "
3460 "entering an invalid\n"
3461 "state for Intel VT. For example, the guest maybe running "
3462 "in big real mode\n"
3463 "which is not supported on less recent Intel processors."
3464 "\n\n");
3465 }
3466 ret = -1;
3467 break;
3468 case KVM_EXIT_EXCEPTION:
3469 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3470 run->ex.exception, run->ex.error_code);
3471 ret = -1;
3472 break;
3473 case KVM_EXIT_DEBUG:
3474 DPRINTF("kvm_exit_debug\n");
3475 qemu_mutex_lock_iothread();
3476 ret = kvm_handle_debug(cpu, &run->debug.arch);
3477 qemu_mutex_unlock_iothread();
3478 break;
3479 case KVM_EXIT_HYPERV:
3480 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3481 break;
3482 case KVM_EXIT_IOAPIC_EOI:
3483 ioapic_eoi_broadcast(run->eoi.vector);
3484 ret = 0;
3485 break;
3486 default:
3487 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3488 ret = -1;
3489 break;
3490 }
3491
3492 return ret;
3493 }
3494
3495 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3496 {
3497 X86CPU *cpu = X86_CPU(cs);
3498 CPUX86State *env = &cpu->env;
3499
3500 kvm_cpu_synchronize_state(cs);
3501 return !(env->cr[0] & CR0_PE_MASK) ||
3502 ((env->segs[R_CS].selector & 3) != 3);
3503 }
3504
3505 void kvm_arch_init_irq_routing(KVMState *s)
3506 {
3507 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3508 /* If kernel can't do irq routing, interrupt source
3509 * override 0->2 cannot be set up as required by HPET.
3510 * So we have to disable it.
3511 */
3512 no_hpet = 1;
3513 }
3514 /* We know at this point that we're using the in-kernel
3515 * irqchip, so we can use irqfds, and on x86 we know
3516 * we can use msi via irqfd and GSI routing.
3517 */
3518 kvm_msi_via_irqfd_allowed = true;
3519 kvm_gsi_routing_allowed = true;
3520
3521 if (kvm_irqchip_is_split()) {
3522 int i;
3523
3524 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3525 MSI routes for signaling interrupts to the local apics. */
3526 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3527 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3528 error_report("Could not enable split IRQ mode.");
3529 exit(1);
3530 }
3531 }
3532 }
3533 }
3534
3535 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3536 {
3537 int ret;
3538 if (machine_kernel_irqchip_split(ms)) {
3539 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3540 if (ret) {
3541 error_report("Could not enable split irqchip mode: %s",
3542 strerror(-ret));
3543 exit(1);
3544 } else {
3545 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3546 kvm_split_irqchip = true;
3547 return 1;
3548 }
3549 } else {
3550 return 0;
3551 }
3552 }
3553
3554 /* Classic KVM device assignment interface. Will remain x86 only. */
3555 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3556 uint32_t flags, uint32_t *dev_id)
3557 {
3558 struct kvm_assigned_pci_dev dev_data = {
3559 .segnr = dev_addr->domain,
3560 .busnr = dev_addr->bus,
3561 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3562 .flags = flags,
3563 };
3564 int ret;
3565
3566 dev_data.assigned_dev_id =
3567 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3568
3569 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3570 if (ret < 0) {
3571 return ret;
3572 }
3573
3574 *dev_id = dev_data.assigned_dev_id;
3575
3576 return 0;
3577 }
3578
3579 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3580 {
3581 struct kvm_assigned_pci_dev dev_data = {
3582 .assigned_dev_id = dev_id,
3583 };
3584
3585 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3586 }
3587
3588 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3589 uint32_t irq_type, uint32_t guest_irq)
3590 {
3591 struct kvm_assigned_irq assigned_irq = {
3592 .assigned_dev_id = dev_id,
3593 .guest_irq = guest_irq,
3594 .flags = irq_type,
3595 };
3596
3597 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3598 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3599 } else {
3600 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3601 }
3602 }
3603
3604 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3605 uint32_t guest_irq)
3606 {
3607 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3608 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3609
3610 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3611 }
3612
3613 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3614 {
3615 struct kvm_assigned_pci_dev dev_data = {
3616 .assigned_dev_id = dev_id,
3617 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3618 };
3619
3620 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3621 }
3622
3623 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3624 uint32_t type)
3625 {
3626 struct kvm_assigned_irq assigned_irq = {
3627 .assigned_dev_id = dev_id,
3628 .flags = type,
3629 };
3630
3631 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3632 }
3633
3634 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3635 {
3636 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3637 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3638 }
3639
3640 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3641 {
3642 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3643 KVM_DEV_IRQ_GUEST_MSI, virq);
3644 }
3645
3646 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3647 {
3648 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3649 KVM_DEV_IRQ_HOST_MSI);
3650 }
3651
3652 bool kvm_device_msix_supported(KVMState *s)
3653 {
3654 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3655 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3656 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3657 }
3658
3659 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3660 uint32_t nr_vectors)
3661 {
3662 struct kvm_assigned_msix_nr msix_nr = {
3663 .assigned_dev_id = dev_id,
3664 .entry_nr = nr_vectors,
3665 };
3666
3667 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3668 }
3669
3670 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3671 int virq)
3672 {
3673 struct kvm_assigned_msix_entry msix_entry = {
3674 .assigned_dev_id = dev_id,
3675 .gsi = virq,
3676 .entry = vector,
3677 };
3678
3679 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3680 }
3681
3682 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3683 {
3684 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3685 KVM_DEV_IRQ_GUEST_MSIX, 0);
3686 }
3687
3688 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3689 {
3690 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3691 KVM_DEV_IRQ_HOST_MSIX);
3692 }
3693
3694 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3695 uint64_t address, uint32_t data, PCIDevice *dev)
3696 {
3697 X86IOMMUState *iommu = x86_iommu_get_default();
3698
3699 if (iommu) {
3700 int ret;
3701 MSIMessage src, dst;
3702 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3703
3704 if (!class->int_remap) {
3705 return 0;
3706 }
3707
3708 src.address = route->u.msi.address_hi;
3709 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3710 src.address |= route->u.msi.address_lo;
3711 src.data = route->u.msi.data;
3712
3713 ret = class->int_remap(iommu, &src, &dst, dev ? \
3714 pci_requester_id(dev) : \
3715 X86_IOMMU_SID_INVALID);
3716 if (ret) {
3717 trace_kvm_x86_fixup_msi_error(route->gsi);
3718 return 1;
3719 }
3720
3721 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3722 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3723 route->u.msi.data = dst.data;
3724 }
3725
3726 return 0;
3727 }
3728
3729 typedef struct MSIRouteEntry MSIRouteEntry;
3730
3731 struct MSIRouteEntry {
3732 PCIDevice *dev; /* Device pointer */
3733 int vector; /* MSI/MSIX vector index */
3734 int virq; /* Virtual IRQ index */
3735 QLIST_ENTRY(MSIRouteEntry) list;
3736 };
3737
3738 /* List of used GSI routes */
3739 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3740 QLIST_HEAD_INITIALIZER(msi_route_list);
3741
3742 static void kvm_update_msi_routes_all(void *private, bool global,
3743 uint32_t index, uint32_t mask)
3744 {
3745 int cnt = 0;
3746 MSIRouteEntry *entry;
3747 MSIMessage msg;
3748 PCIDevice *dev;
3749
3750 /* TODO: explicit route update */
3751 QLIST_FOREACH(entry, &msi_route_list, list) {
3752 cnt++;
3753 dev = entry->dev;
3754 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3755 continue;
3756 }
3757 msg = pci_get_msi_message(dev, entry->vector);
3758 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3759 }
3760 kvm_irqchip_commit_routes(kvm_state);
3761 trace_kvm_x86_update_msi_routes(cnt);
3762 }
3763
3764 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3765 int vector, PCIDevice *dev)
3766 {
3767 static bool notify_list_inited = false;
3768 MSIRouteEntry *entry;
3769
3770 if (!dev) {
3771 /* These are (possibly) IOAPIC routes only used for split
3772 * kernel irqchip mode, while what we are housekeeping are
3773 * PCI devices only. */
3774 return 0;
3775 }
3776
3777 entry = g_new0(MSIRouteEntry, 1);
3778 entry->dev = dev;
3779 entry->vector = vector;
3780 entry->virq = route->gsi;
3781 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3782
3783 trace_kvm_x86_add_msi_route(route->gsi);
3784
3785 if (!notify_list_inited) {
3786 /* For the first time we do add route, add ourselves into
3787 * IOMMU's IEC notify list if needed. */
3788 X86IOMMUState *iommu = x86_iommu_get_default();
3789 if (iommu) {
3790 x86_iommu_iec_register_notifier(iommu,
3791 kvm_update_msi_routes_all,
3792 NULL);
3793 }
3794 notify_list_inited = true;
3795 }
3796 return 0;
3797 }
3798
3799 int kvm_arch_release_virq_post(int virq)
3800 {
3801 MSIRouteEntry *entry, *next;
3802 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3803 if (entry->virq == virq) {
3804 trace_kvm_x86_remove_msi_route(virq);
3805 QLIST_REMOVE(entry, list);
3806 g_free(entry);
3807 break;
3808 }
3809 }
3810 return 0;
3811 }
3812
3813 int kvm_arch_msi_data_to_gsi(uint32_t data)
3814 {
3815 abort();
3816 }
AR7 emulation for QEMU