2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 static const TypeInfo spapr_intc_info
= {
27 .name
= TYPE_SPAPR_INTC
,
28 .parent
= TYPE_INTERFACE
,
29 .class_size
= sizeof(SpaprInterruptControllerClass
),
32 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
34 spapr
->irq_map_nr
= nr_msis
;
35 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
38 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
44 * The 'align_mask' parameter of bitmap_find_next_zero_area()
45 * should be one less than a power of 2; 0 means no
46 * alignment. Adapt the 'align' value of the former allocator
47 * to fit the requirements of bitmap_find_next_zero_area()
51 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
53 if (irq
== spapr
->irq_map_nr
) {
54 error_setg(errp
, "can't find a free %d-IRQ block", num
);
58 bitmap_set(spapr
->irq_map
, irq
, num
);
60 return irq
+ SPAPR_IRQ_MSI
;
63 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
65 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
68 int spapr_irq_init_kvm(int (*fn
)(SpaprInterruptController
*, Error
**),
69 SpaprInterruptController
*intc
,
72 MachineState
*machine
= MACHINE(qdev_get_machine());
73 Error
*local_err
= NULL
;
75 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
76 if (fn(intc
, &local_err
) < 0) {
77 if (machine_kernel_irqchip_required(machine
)) {
78 error_prepend(&local_err
,
79 "kernel_irqchip requested but unavailable: ");
80 error_propagate(errp
, local_err
);
85 * We failed to initialize the KVM device, fallback to
88 error_prepend(&local_err
,
89 "kernel_irqchip allowed but unavailable: ");
90 error_append_hint(&local_err
,
91 "Falling back to kernel-irqchip=off\n");
92 warn_report_err(local_err
);
103 SpaprIrq spapr_irq_xics
= {
104 .nr_xirqs
= SPAPR_NR_XIRQS
,
105 .nr_msis
= SPAPR_NR_MSIS
,
114 SpaprIrq spapr_irq_xive
= {
115 .nr_xirqs
= SPAPR_NR_XIRQS
,
116 .nr_msis
= SPAPR_NR_MSIS
,
122 * Dual XIVE and XICS IRQ backend.
124 * Both interrupt mode, XIVE and XICS, objects are created but the
125 * machine starts in legacy interrupt mode (XICS). It can be changed
126 * by the CAS negotiation process and, in that case, the new mode is
127 * activated after an extra machine reset.
131 * Define values in sync with the XIVE and XICS backend
133 SpaprIrq spapr_irq_dual
= {
134 .nr_xirqs
= SPAPR_NR_XIRQS
,
135 .nr_msis
= SPAPR_NR_MSIS
,
141 static int spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
143 MachineState
*machine
= MACHINE(spapr
);
146 * Sanity checks on non-P9 machines. On these, XIVE is not
147 * advertised, see spapr_dt_ov5_platform_support()
149 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
150 0, spapr
->max_compat_pvr
)) {
152 * If the 'dual' interrupt mode is selected, force XICS as CAS
153 * negotiation is useless.
155 if (spapr
->irq
== &spapr_irq_dual
) {
156 spapr
->irq
= &spapr_irq_xics
;
161 * Non-P9 machines using only XIVE is a bogus setup. We have two
162 * scenarios to take into account because of the compat mode:
164 * 1. POWER7/8 machines should fail to init later on when creating
165 * the XIVE interrupt presenters because a POWER9 exception
168 * 2. POWER9 machines using the POWER8 compat mode won't fail and
169 * will let the OS boot with a partial XIVE setup : DT
170 * properties but no hcalls.
172 * To cover both and not confuse the OS, add an early failure in
175 if (spapr
->irq
== &spapr_irq_xive
) {
176 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
182 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
183 * re-created. Detect that early to avoid QEMU to exit later when the
187 spapr
->irq
== &spapr_irq_dual
&&
188 machine_kernel_irqchip_required(machine
) &&
189 xics_kvm_has_broken_disconnect(spapr
)) {
190 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
198 * sPAPR IRQ frontend routines for devices
200 #define ALL_INTCS(spapr_) \
201 { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
203 int spapr_irq_cpu_intc_create(SpaprMachineState
*spapr
,
204 PowerPCCPU
*cpu
, Error
**errp
)
206 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
210 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
211 SpaprInterruptController
*intc
= intcs
[i
];
213 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
214 rc
= sicc
->cpu_intc_create(intc
, cpu
, errp
);
224 static void spapr_set_irq(void *opaque
, int irq
, int level
)
226 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
227 SpaprInterruptControllerClass
*sicc
228 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
230 sicc
->set_irq(spapr
->active_intc
, irq
, level
);
233 void spapr_irq_print_info(SpaprMachineState
*spapr
, Monitor
*mon
)
235 SpaprInterruptControllerClass
*sicc
236 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
238 sicc
->print_info(spapr
->active_intc
, mon
);
241 void spapr_irq_dt(SpaprMachineState
*spapr
, uint32_t nr_servers
,
242 void *fdt
, uint32_t phandle
)
244 SpaprInterruptControllerClass
*sicc
245 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
247 sicc
->dt(spapr
->active_intc
, nr_servers
, fdt
, phandle
);
250 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
252 MachineState
*machine
= MACHINE(spapr
);
254 if (machine_kernel_irqchip_split(machine
)) {
255 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
259 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
261 "kernel_irqchip requested but only available with KVM");
265 if (spapr_irq_check(spapr
, errp
) < 0) {
269 /* Initialize the MSI IRQ allocator. */
270 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
271 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
274 if (spapr
->irq
->xics
) {
275 Error
*local_err
= NULL
;
278 obj
= object_new(TYPE_ICS_SPAPR
);
279 object_property_add_child(OBJECT(spapr
), "ics", obj
, &local_err
);
281 error_propagate(errp
, local_err
);
285 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
288 error_propagate(errp
, local_err
);
292 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
, "nr-irqs",
295 error_propagate(errp
, local_err
);
299 object_property_set_bool(obj
, true, "realized", &local_err
);
301 error_propagate(errp
, local_err
);
305 spapr
->ics
= ICS_SPAPR(obj
);
308 if (spapr
->irq
->xive
) {
309 uint32_t nr_servers
= spapr_max_server_number(spapr
);
313 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
314 qdev_prop_set_uint32(dev
, "nr-irqs",
315 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
317 * 8 XIVE END structures per CPU. One for each available
320 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
321 qdev_init_nofail(dev
);
323 spapr
->xive
= SPAPR_XIVE(dev
);
325 /* Enable the CPU IPIs */
326 for (i
= 0; i
< nr_servers
; ++i
) {
327 SpaprInterruptControllerClass
*sicc
328 = SPAPR_INTC_GET_CLASS(spapr
->xive
);
330 if (sicc
->claim_irq(SPAPR_INTC(spapr
->xive
), SPAPR_IRQ_IPI
+ i
,
336 spapr_xive_hcall_init(spapr
);
339 spapr
->qirqs
= qemu_allocate_irqs(spapr_set_irq
, spapr
,
340 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
343 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
345 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
349 assert(irq
>= SPAPR_XIRQ_BASE
);
350 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
352 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
353 SpaprInterruptController
*intc
= intcs
[i
];
355 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
356 rc
= sicc
->claim_irq(intc
, irq
, lsi
, errp
);
366 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
368 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
371 assert(irq
>= SPAPR_XIRQ_BASE
);
372 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
374 for (i
= irq
; i
< (irq
+ num
); i
++) {
375 for (j
= 0; j
< ARRAY_SIZE(intcs
); j
++) {
376 SpaprInterruptController
*intc
= intcs
[j
];
379 SpaprInterruptControllerClass
*sicc
380 = SPAPR_INTC_GET_CLASS(intc
);
381 sicc
->free_irq(intc
, i
);
387 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
390 * This interface is basically for VIO and PHB devices to find the
391 * right qemu_irq to manipulate, so we only allow access to the
392 * external irqs for now. Currently anything which needs to
393 * access the IPIs most naturally gets there via the guest side
394 * interfaces, we can change this if we need to in future.
396 assert(irq
>= SPAPR_XIRQ_BASE
);
397 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
400 assert(ics_valid_irq(spapr
->ics
, irq
));
403 assert(irq
< spapr
->xive
->nr_irqs
);
404 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
407 return spapr
->qirqs
[irq
];
410 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
412 SpaprInterruptControllerClass
*sicc
;
414 spapr_irq_update_active_intc(spapr
);
415 sicc
= SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
416 return sicc
->post_load(spapr
->active_intc
, version_id
);
419 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
421 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
423 spapr_irq_update_active_intc(spapr
);
426 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
428 const char *nodename
= "interrupt-controller";
431 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
433 error_setg(errp
, "Can't find node \"%s\": %s",
434 nodename
, fdt_strerror(offset
));
438 phandle
= fdt_get_phandle(fdt
, offset
);
440 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
447 static void set_active_intc(SpaprMachineState
*spapr
,
448 SpaprInterruptController
*new_intc
)
450 SpaprInterruptControllerClass
*sicc
;
454 if (new_intc
== spapr
->active_intc
) {
459 if (spapr
->active_intc
) {
460 sicc
= SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
461 if (sicc
->deactivate
) {
462 sicc
->deactivate(spapr
->active_intc
);
466 sicc
= SPAPR_INTC_GET_CLASS(new_intc
);
467 if (sicc
->activate
) {
468 sicc
->activate(new_intc
, &error_fatal
);
471 spapr
->active_intc
= new_intc
;
474 void spapr_irq_update_active_intc(SpaprMachineState
*spapr
)
476 SpaprInterruptController
*new_intc
;
480 * XXX before we run CAS, ov5_cas is initialized empty, which
481 * indicates XICS, even if we have ic-mode=xive. TODO: clean
482 * up the CAS path so that we have a clearer way of handling
485 new_intc
= SPAPR_INTC(spapr
->xive
);
486 } else if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
487 new_intc
= SPAPR_INTC(spapr
->xive
);
489 new_intc
= SPAPR_INTC(spapr
->ics
);
492 set_active_intc(spapr
, new_intc
);
496 * XICS legacy routines - to deprecate one day
499 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
503 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
504 if (num
> (ics
->nr_irqs
- first
)) {
507 for (i
= first
; i
< first
+ num
; ++i
) {
508 if (!ics_irq_free(ics
, i
)) {
512 if (i
== (first
+ num
)) {
520 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
522 ICSState
*ics
= spapr
->ics
;
528 * MSIMesage::data is used for storing VIRQ so
529 * it has to be aligned to num to support multiple
530 * MSI vectors. MSI-X is not affected by this.
531 * The hint is used for the first IRQ, the rest should
532 * be allocated continuously.
535 assert((num
== 1) || (num
== 2) || (num
== 4) ||
536 (num
== 8) || (num
== 16) || (num
== 32));
537 first
= ics_find_free_block(ics
, num
, num
);
539 first
= ics_find_free_block(ics
, num
, 1);
543 error_setg(errp
, "can't find a free %d-IRQ block", num
);
547 return first
+ ics
->offset
;
550 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
552 SpaprIrq spapr_irq_xics_legacy
= {
553 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
554 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
559 static void spapr_irq_register_types(void)
561 type_register_static(&spapr_intc_info
);
564 type_init(spapr_irq_register_types
)