2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_LIVENESS_ANALYSIS
27 #define USE_TCG_OPTIMIZATIONS
31 /* Define to jump the ELF file used to communicate with GDB. */
34 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
35 /* define it to suppress various consistency checks (faster) */
39 #include "qemu-common.h"
40 #include "qemu/host-utils.h"
41 #include "qemu/timer.h"
43 /* Note: the long term plan is to reduce the dependencies on the QEMU
44 CPU definitions. Currently they are used for qemu_ld/st
46 #define NO_CPU_IO_DEFS
51 #if UINTPTR_MAX == UINT32_MAX
52 # define ELF_CLASS ELFCLASS32
54 # define ELF_CLASS ELFCLASS64
56 #ifdef HOST_WORDS_BIGENDIAN
57 # define ELF_DATA ELFDATA2MSB
59 # define ELF_DATA ELFDATA2LSB
64 /* Forward declarations for functions declared in tcg-target.c and used here. */
65 static void tcg_target_init(TCGContext
*s
);
66 static void tcg_target_qemu_prologue(TCGContext
*s
);
67 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
68 intptr_t value
, intptr_t addend
);
70 /* The CIE and FDE header definitions will be common to all hosts. */
72 uint32_t len
__attribute__((aligned((sizeof(void *)))));
78 uint8_t return_column
;
81 typedef struct QEMU_PACKED
{
82 uint32_t len
__attribute__((aligned((sizeof(void *)))));
86 } DebugFrameFDEHeader
;
88 typedef struct QEMU_PACKED
{
90 DebugFrameFDEHeader fde
;
93 static void tcg_register_jit_int(void *buf
, size_t size
,
94 const void *debug_frame
,
95 size_t debug_frame_size
)
96 __attribute__((unused
));
98 /* Forward declarations for functions declared and used in tcg-target.c. */
99 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
);
100 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
102 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
103 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
104 TCGReg ret
, tcg_target_long arg
);
105 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
106 const int *const_args
);
107 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
109 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
);
110 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
111 const TCGArgConstraint
*arg_ct
);
112 static void tcg_out_tb_init(TCGContext
*s
);
113 static void tcg_out_tb_finalize(TCGContext
*s
);
117 static TCGRegSet tcg_target_available_regs
[2];
118 static TCGRegSet tcg_target_call_clobber_regs
;
120 #if TCG_TARGET_INSN_UNIT_SIZE == 1
121 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
126 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
133 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
134 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
136 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
139 tcg_insn_unit
*p
= s
->code_ptr
;
140 memcpy(p
, &v
, sizeof(v
));
141 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
145 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
148 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
151 memcpy(p
, &v
, sizeof(v
));
156 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
157 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
159 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
162 tcg_insn_unit
*p
= s
->code_ptr
;
163 memcpy(p
, &v
, sizeof(v
));
164 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
168 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
171 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
174 memcpy(p
, &v
, sizeof(v
));
179 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
180 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
182 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
185 tcg_insn_unit
*p
= s
->code_ptr
;
186 memcpy(p
, &v
, sizeof(v
));
187 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
191 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
194 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
197 memcpy(p
, &v
, sizeof(v
));
202 /* label relocation processing */
204 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
205 TCGLabel
*l
, intptr_t addend
)
210 /* FIXME: This may break relocations on RISC targets that
211 modify instruction fields in place. The caller may not have
212 written the initial value. */
213 patch_reloc(code_ptr
, type
, l
->u
.value
, addend
);
215 /* add a new relocation entry */
216 r
= tcg_malloc(sizeof(TCGRelocation
));
220 r
->next
= l
->u
.first_reloc
;
221 l
->u
.first_reloc
= r
;
225 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
, tcg_insn_unit
*ptr
)
227 intptr_t value
= (intptr_t)ptr
;
230 assert(!l
->has_value
);
232 for (r
= l
->u
.first_reloc
; r
!= NULL
; r
= r
->next
) {
233 patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
);
237 l
->u
.value_ptr
= ptr
;
240 TCGLabel
*gen_new_label(void)
242 TCGContext
*s
= &tcg_ctx
;
243 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
252 #include "tcg-target.c"
254 /* pool based memory allocation */
255 void *tcg_malloc_internal(TCGContext
*s
, int size
)
260 if (size
> TCG_POOL_CHUNK_SIZE
) {
261 /* big malloc: insert a new pool (XXX: could optimize) */
262 p
= g_malloc(sizeof(TCGPool
) + size
);
264 p
->next
= s
->pool_first_large
;
265 s
->pool_first_large
= p
;
276 pool_size
= TCG_POOL_CHUNK_SIZE
;
277 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
281 s
->pool_current
->next
= p
;
290 s
->pool_cur
= p
->data
+ size
;
291 s
->pool_end
= p
->data
+ p
->size
;
295 void tcg_pool_reset(TCGContext
*s
)
298 for (p
= s
->pool_first_large
; p
; p
= t
) {
302 s
->pool_first_large
= NULL
;
303 s
->pool_cur
= s
->pool_end
= NULL
;
304 s
->pool_current
= NULL
;
307 typedef struct TCGHelperInfo
{
314 #include "exec/helper-proto.h"
316 static const TCGHelperInfo all_helpers
[] = {
317 #include "exec/helper-tcg.h"
320 void tcg_context_init(TCGContext
*s
)
322 int op
, total_args
, n
, i
;
324 TCGArgConstraint
*args_ct
;
326 GHashTable
*helper_table
;
328 memset(s
, 0, sizeof(*s
));
331 /* Count total number of arguments and allocate the corresponding
334 for(op
= 0; op
< NB_OPS
; op
++) {
335 def
= &tcg_op_defs
[op
];
336 n
= def
->nb_iargs
+ def
->nb_oargs
;
340 args_ct
= g_malloc(sizeof(TCGArgConstraint
) * total_args
);
341 sorted_args
= g_malloc(sizeof(int) * total_args
);
343 for(op
= 0; op
< NB_OPS
; op
++) {
344 def
= &tcg_op_defs
[op
];
345 def
->args_ct
= args_ct
;
346 def
->sorted_args
= sorted_args
;
347 n
= def
->nb_iargs
+ def
->nb_oargs
;
352 /* Register helpers. */
353 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
354 s
->helpers
= helper_table
= g_hash_table_new(NULL
, NULL
);
356 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
357 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
358 (gpointer
)&all_helpers
[i
]);
364 void tcg_prologue_init(TCGContext
*s
)
366 /* init global prologue and epilogue */
367 s
->code_buf
= s
->code_gen_prologue
;
368 s
->code_ptr
= s
->code_buf
;
369 tcg_target_qemu_prologue(s
);
370 flush_icache_range((uintptr_t)s
->code_buf
, (uintptr_t)s
->code_ptr
);
373 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
374 size_t size
= tcg_current_code_size(s
);
375 qemu_log("PROLOGUE: [size=%zu]\n", size
);
376 log_disas(s
->code_buf
, size
);
383 void tcg_set_frame(TCGContext
*s
, int reg
, intptr_t start
, intptr_t size
)
385 s
->frame_start
= start
;
386 s
->frame_end
= start
+ size
;
390 void tcg_func_start(TCGContext
*s
)
393 s
->nb_temps
= s
->nb_globals
;
395 /* No temps have been previously allocated for size or locality. */
396 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
399 s
->current_frame_offset
= s
->frame_start
;
401 #ifdef CONFIG_DEBUG_TCG
402 s
->goto_tb_issue_mask
= 0;
405 s
->gen_first_op_idx
= 0;
406 s
->gen_last_op_idx
= -1;
407 s
->gen_next_op_idx
= 0;
408 s
->gen_next_parm_idx
= 0;
410 s
->be
= tcg_malloc(sizeof(TCGBackendData
));
413 static inline void tcg_temp_alloc(TCGContext
*s
, int n
)
415 if (n
> TCG_MAX_TEMPS
)
419 static inline int tcg_global_reg_new_internal(TCGType type
, int reg
,
422 TCGContext
*s
= &tcg_ctx
;
426 #if TCG_TARGET_REG_BITS == 32
427 if (type
!= TCG_TYPE_I32
)
430 if (tcg_regset_test_reg(s
->reserved_regs
, reg
))
433 tcg_temp_alloc(s
, s
->nb_globals
+ 1);
434 ts
= &s
->temps
[s
->nb_globals
];
435 ts
->base_type
= type
;
441 tcg_regset_set_reg(s
->reserved_regs
, reg
);
445 TCGv_i32
tcg_global_reg_new_i32(int reg
, const char *name
)
449 idx
= tcg_global_reg_new_internal(TCG_TYPE_I32
, reg
, name
);
450 return MAKE_TCGV_I32(idx
);
453 TCGv_i64
tcg_global_reg_new_i64(int reg
, const char *name
)
457 idx
= tcg_global_reg_new_internal(TCG_TYPE_I64
, reg
, name
);
458 return MAKE_TCGV_I64(idx
);
461 static inline int tcg_global_mem_new_internal(TCGType type
, int reg
,
465 TCGContext
*s
= &tcg_ctx
;
470 #if TCG_TARGET_REG_BITS == 32
471 if (type
== TCG_TYPE_I64
) {
473 tcg_temp_alloc(s
, s
->nb_globals
+ 2);
474 ts
= &s
->temps
[s
->nb_globals
];
475 ts
->base_type
= type
;
476 ts
->type
= TCG_TYPE_I32
;
478 ts
->mem_allocated
= 1;
480 #ifdef HOST_WORDS_BIGENDIAN
481 ts
->mem_offset
= offset
+ 4;
483 ts
->mem_offset
= offset
;
485 pstrcpy(buf
, sizeof(buf
), name
);
486 pstrcat(buf
, sizeof(buf
), "_0");
487 ts
->name
= strdup(buf
);
490 ts
->base_type
= type
;
491 ts
->type
= TCG_TYPE_I32
;
493 ts
->mem_allocated
= 1;
495 #ifdef HOST_WORDS_BIGENDIAN
496 ts
->mem_offset
= offset
;
498 ts
->mem_offset
= offset
+ 4;
500 pstrcpy(buf
, sizeof(buf
), name
);
501 pstrcat(buf
, sizeof(buf
), "_1");
502 ts
->name
= strdup(buf
);
508 tcg_temp_alloc(s
, s
->nb_globals
+ 1);
509 ts
= &s
->temps
[s
->nb_globals
];
510 ts
->base_type
= type
;
513 ts
->mem_allocated
= 1;
515 ts
->mem_offset
= offset
;
522 TCGv_i32
tcg_global_mem_new_i32(int reg
, intptr_t offset
, const char *name
)
524 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
525 return MAKE_TCGV_I32(idx
);
528 TCGv_i64
tcg_global_mem_new_i64(int reg
, intptr_t offset
, const char *name
)
530 int idx
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
531 return MAKE_TCGV_I64(idx
);
534 static inline int tcg_temp_new_internal(TCGType type
, int temp_local
)
536 TCGContext
*s
= &tcg_ctx
;
540 k
= type
+ (temp_local
? TCG_TYPE_COUNT
: 0);
541 idx
= find_first_bit(s
->free_temps
[k
].l
, TCG_MAX_TEMPS
);
542 if (idx
< TCG_MAX_TEMPS
) {
543 /* There is already an available temp with the right type. */
544 clear_bit(idx
, s
->free_temps
[k
].l
);
547 ts
->temp_allocated
= 1;
548 assert(ts
->base_type
== type
);
549 assert(ts
->temp_local
== temp_local
);
552 #if TCG_TARGET_REG_BITS == 32
553 if (type
== TCG_TYPE_I64
) {
554 tcg_temp_alloc(s
, s
->nb_temps
+ 2);
555 ts
= &s
->temps
[s
->nb_temps
];
556 ts
->base_type
= type
;
557 ts
->type
= TCG_TYPE_I32
;
558 ts
->temp_allocated
= 1;
559 ts
->temp_local
= temp_local
;
562 ts
->base_type
= type
;
563 ts
->type
= TCG_TYPE_I32
;
564 ts
->temp_allocated
= 1;
565 ts
->temp_local
= temp_local
;
571 tcg_temp_alloc(s
, s
->nb_temps
+ 1);
572 ts
= &s
->temps
[s
->nb_temps
];
573 ts
->base_type
= type
;
575 ts
->temp_allocated
= 1;
576 ts
->temp_local
= temp_local
;
582 #if defined(CONFIG_DEBUG_TCG)
588 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
)
592 idx
= tcg_temp_new_internal(TCG_TYPE_I32
, temp_local
);
593 return MAKE_TCGV_I32(idx
);
596 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
)
600 idx
= tcg_temp_new_internal(TCG_TYPE_I64
, temp_local
);
601 return MAKE_TCGV_I64(idx
);
604 static void tcg_temp_free_internal(int idx
)
606 TCGContext
*s
= &tcg_ctx
;
610 #if defined(CONFIG_DEBUG_TCG)
612 if (s
->temps_in_use
< 0) {
613 fprintf(stderr
, "More temporaries freed than allocated!\n");
617 assert(idx
>= s
->nb_globals
&& idx
< s
->nb_temps
);
619 assert(ts
->temp_allocated
!= 0);
620 ts
->temp_allocated
= 0;
622 k
= ts
->base_type
+ (ts
->temp_local
? TCG_TYPE_COUNT
: 0);
623 set_bit(idx
, s
->free_temps
[k
].l
);
626 void tcg_temp_free_i32(TCGv_i32 arg
)
628 tcg_temp_free_internal(GET_TCGV_I32(arg
));
631 void tcg_temp_free_i64(TCGv_i64 arg
)
633 tcg_temp_free_internal(GET_TCGV_I64(arg
));
636 TCGv_i32
tcg_const_i32(int32_t val
)
639 t0
= tcg_temp_new_i32();
640 tcg_gen_movi_i32(t0
, val
);
644 TCGv_i64
tcg_const_i64(int64_t val
)
647 t0
= tcg_temp_new_i64();
648 tcg_gen_movi_i64(t0
, val
);
652 TCGv_i32
tcg_const_local_i32(int32_t val
)
655 t0
= tcg_temp_local_new_i32();
656 tcg_gen_movi_i32(t0
, val
);
660 TCGv_i64
tcg_const_local_i64(int64_t val
)
663 t0
= tcg_temp_local_new_i64();
664 tcg_gen_movi_i64(t0
, val
);
668 #if defined(CONFIG_DEBUG_TCG)
669 void tcg_clear_temp_count(void)
671 TCGContext
*s
= &tcg_ctx
;
675 int tcg_check_temp_count(void)
677 TCGContext
*s
= &tcg_ctx
;
678 if (s
->temps_in_use
) {
679 /* Clear the count so that we don't give another
680 * warning immediately next time around.
689 /* Note: we convert the 64 bit args to 32 bit and do some alignment
690 and endian swap. Maybe it would be better to do the alignment
691 and endian swap in tcg_reg_alloc_call(). */
692 void tcg_gen_callN(TCGContext
*s
, void *func
, TCGArg ret
,
693 int nargs
, TCGArg
*args
)
695 int i
, real_args
, nb_rets
, pi
, pi_first
;
696 unsigned sizemask
, flags
;
699 info
= g_hash_table_lookup(s
->helpers
, (gpointer
)func
);
701 sizemask
= info
->sizemask
;
703 #if defined(__sparc__) && !defined(__arch64__) \
704 && !defined(CONFIG_TCG_INTERPRETER)
705 /* We have 64-bit values in one register, but need to pass as two
706 separate parameters. Split them. */
707 int orig_sizemask
= sizemask
;
708 int orig_nargs
= nargs
;
711 TCGV_UNUSED_I64(retl
);
712 TCGV_UNUSED_I64(reth
);
714 TCGArg
*split_args
= __builtin_alloca(sizeof(TCGArg
) * nargs
* 2);
715 for (i
= real_args
= 0; i
< nargs
; ++i
) {
716 int is_64bit
= sizemask
& (1 << (i
+1)*2);
718 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
719 TCGv_i32 h
= tcg_temp_new_i32();
720 TCGv_i32 l
= tcg_temp_new_i32();
721 tcg_gen_extr_i64_i32(l
, h
, orig
);
722 split_args
[real_args
++] = GET_TCGV_I32(h
);
723 split_args
[real_args
++] = GET_TCGV_I32(l
);
725 split_args
[real_args
++] = args
[i
];
732 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
733 for (i
= 0; i
< nargs
; ++i
) {
734 int is_64bit
= sizemask
& (1 << (i
+1)*2);
735 int is_signed
= sizemask
& (2 << (i
+1)*2);
737 TCGv_i64 temp
= tcg_temp_new_i64();
738 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
740 tcg_gen_ext32s_i64(temp
, orig
);
742 tcg_gen_ext32u_i64(temp
, orig
);
744 args
[i
] = GET_TCGV_I64(temp
);
747 #endif /* TCG_TARGET_EXTEND_ARGS */
749 pi_first
= pi
= s
->gen_next_parm_idx
;
750 if (ret
!= TCG_CALL_DUMMY_ARG
) {
751 #if defined(__sparc__) && !defined(__arch64__) \
752 && !defined(CONFIG_TCG_INTERPRETER)
753 if (orig_sizemask
& 1) {
754 /* The 32-bit ABI is going to return the 64-bit value in
755 the %o0/%o1 register pair. Prepare for this by using
756 two return temporaries, and reassemble below. */
757 retl
= tcg_temp_new_i64();
758 reth
= tcg_temp_new_i64();
759 s
->gen_opparam_buf
[pi
++] = GET_TCGV_I64(reth
);
760 s
->gen_opparam_buf
[pi
++] = GET_TCGV_I64(retl
);
763 s
->gen_opparam_buf
[pi
++] = ret
;
767 if (TCG_TARGET_REG_BITS
< 64 && (sizemask
& 1)) {
768 #ifdef HOST_WORDS_BIGENDIAN
769 s
->gen_opparam_buf
[pi
++] = ret
+ 1;
770 s
->gen_opparam_buf
[pi
++] = ret
;
772 s
->gen_opparam_buf
[pi
++] = ret
;
773 s
->gen_opparam_buf
[pi
++] = ret
+ 1;
777 s
->gen_opparam_buf
[pi
++] = ret
;
785 for (i
= 0; i
< nargs
; i
++) {
786 int is_64bit
= sizemask
& (1 << (i
+1)*2);
787 if (TCG_TARGET_REG_BITS
< 64 && is_64bit
) {
788 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
789 /* some targets want aligned 64 bit args */
791 s
->gen_opparam_buf
[pi
++] = TCG_CALL_DUMMY_ARG
;
795 /* If stack grows up, then we will be placing successive
796 arguments at lower addresses, which means we need to
797 reverse the order compared to how we would normally
798 treat either big or little-endian. For those arguments
799 that will wind up in registers, this still works for
800 HPPA (the only current STACK_GROWSUP target) since the
801 argument registers are *also* allocated in decreasing
802 order. If another such target is added, this logic may
803 have to get more complicated to differentiate between
804 stack arguments and register arguments. */
805 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
806 s
->gen_opparam_buf
[pi
++] = args
[i
] + 1;
807 s
->gen_opparam_buf
[pi
++] = args
[i
];
809 s
->gen_opparam_buf
[pi
++] = args
[i
];
810 s
->gen_opparam_buf
[pi
++] = args
[i
] + 1;
816 s
->gen_opparam_buf
[pi
++] = args
[i
];
819 s
->gen_opparam_buf
[pi
++] = (uintptr_t)func
;
820 s
->gen_opparam_buf
[pi
++] = flags
;
822 i
= s
->gen_next_op_idx
;
823 tcg_debug_assert(i
< OPC_BUF_SIZE
);
824 tcg_debug_assert(pi
<= OPPARAM_BUF_SIZE
);
826 /* Set links for sequential allocation during translation. */
827 s
->gen_op_buf
[i
] = (TCGOp
){
828 .opc
= INDEX_op_call
,
836 /* Make sure the calli field didn't overflow. */
837 tcg_debug_assert(s
->gen_op_buf
[i
].calli
== real_args
);
839 s
->gen_last_op_idx
= i
;
840 s
->gen_next_op_idx
= i
+ 1;
841 s
->gen_next_parm_idx
= pi
;
843 #if defined(__sparc__) && !defined(__arch64__) \
844 && !defined(CONFIG_TCG_INTERPRETER)
845 /* Free all of the parts we allocated above. */
846 for (i
= real_args
= 0; i
< orig_nargs
; ++i
) {
847 int is_64bit
= orig_sizemask
& (1 << (i
+1)*2);
849 TCGv_i32 h
= MAKE_TCGV_I32(args
[real_args
++]);
850 TCGv_i32 l
= MAKE_TCGV_I32(args
[real_args
++]);
851 tcg_temp_free_i32(h
);
852 tcg_temp_free_i32(l
);
857 if (orig_sizemask
& 1) {
858 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
859 Note that describing these as TCGv_i64 eliminates an unnecessary
860 zero-extension that tcg_gen_concat_i32_i64 would create. */
861 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret
), retl
, reth
);
862 tcg_temp_free_i64(retl
);
863 tcg_temp_free_i64(reth
);
865 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
866 for (i
= 0; i
< nargs
; ++i
) {
867 int is_64bit
= sizemask
& (1 << (i
+1)*2);
869 TCGv_i64 temp
= MAKE_TCGV_I64(args
[i
]);
870 tcg_temp_free_i64(temp
);
873 #endif /* TCG_TARGET_EXTEND_ARGS */
876 static void tcg_reg_alloc_start(TCGContext
*s
)
880 for(i
= 0; i
< s
->nb_globals
; i
++) {
883 ts
->val_type
= TEMP_VAL_REG
;
885 ts
->val_type
= TEMP_VAL_MEM
;
888 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
890 if (ts
->temp_local
) {
891 ts
->val_type
= TEMP_VAL_MEM
;
893 ts
->val_type
= TEMP_VAL_DEAD
;
895 ts
->mem_allocated
= 0;
898 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
899 s
->reg_to_temp
[i
] = -1;
903 static char *tcg_get_arg_str_idx(TCGContext
*s
, char *buf
, int buf_size
,
908 assert(idx
>= 0 && idx
< s
->nb_temps
);
910 if (idx
< s
->nb_globals
) {
911 pstrcpy(buf
, buf_size
, ts
->name
);
914 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
916 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
921 char *tcg_get_arg_str_i32(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i32 arg
)
923 return tcg_get_arg_str_idx(s
, buf
, buf_size
, GET_TCGV_I32(arg
));
926 char *tcg_get_arg_str_i64(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i64 arg
)
928 return tcg_get_arg_str_idx(s
, buf
, buf_size
, GET_TCGV_I64(arg
));
931 /* Find helper name. */
932 static inline const char *tcg_find_helper(TCGContext
*s
, uintptr_t val
)
934 const char *ret
= NULL
;
936 TCGHelperInfo
*info
= g_hash_table_lookup(s
->helpers
, (gpointer
)val
);
944 static const char * const cond_name
[] =
946 [TCG_COND_NEVER
] = "never",
947 [TCG_COND_ALWAYS
] = "always",
948 [TCG_COND_EQ
] = "eq",
949 [TCG_COND_NE
] = "ne",
950 [TCG_COND_LT
] = "lt",
951 [TCG_COND_GE
] = "ge",
952 [TCG_COND_LE
] = "le",
953 [TCG_COND_GT
] = "gt",
954 [TCG_COND_LTU
] = "ltu",
955 [TCG_COND_GEU
] = "geu",
956 [TCG_COND_LEU
] = "leu",
957 [TCG_COND_GTU
] = "gtu"
960 static const char * const ldst_name
[] =
976 void tcg_dump_ops(TCGContext
*s
)
982 for (oi
= s
->gen_first_op_idx
; oi
>= 0; oi
= op
->next
) {
983 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
988 op
= &s
->gen_op_buf
[oi
];
990 def
= &tcg_op_defs
[c
];
991 args
= &s
->gen_opparam_buf
[op
->args
];
993 if (c
== INDEX_op_debug_insn_start
) {
995 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
996 pc
= ((uint64_t)args
[1] << 32) | args
[0];
1000 if (oi
!= s
->gen_first_op_idx
) {
1003 qemu_log(" ---- 0x%" PRIx64
, pc
);
1004 } else if (c
== INDEX_op_call
) {
1005 /* variable number of arguments */
1006 nb_oargs
= op
->callo
;
1007 nb_iargs
= op
->calli
;
1008 nb_cargs
= def
->nb_cargs
;
1010 /* function name, flags, out args */
1011 qemu_log(" %s %s,$0x%" TCG_PRIlx
",$%d", def
->name
,
1012 tcg_find_helper(s
, args
[nb_oargs
+ nb_iargs
]),
1013 args
[nb_oargs
+ nb_iargs
+ 1], nb_oargs
);
1014 for (i
= 0; i
< nb_oargs
; i
++) {
1015 qemu_log(",%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1018 for (i
= 0; i
< nb_iargs
; i
++) {
1019 TCGArg arg
= args
[nb_oargs
+ i
];
1020 const char *t
= "<dummy>";
1021 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1022 t
= tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), arg
);
1027 qemu_log(" %s ", def
->name
);
1029 nb_oargs
= def
->nb_oargs
;
1030 nb_iargs
= def
->nb_iargs
;
1031 nb_cargs
= def
->nb_cargs
;
1034 for (i
= 0; i
< nb_oargs
; i
++) {
1038 qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1041 for (i
= 0; i
< nb_iargs
; i
++) {
1045 qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1049 case INDEX_op_brcond_i32
:
1050 case INDEX_op_setcond_i32
:
1051 case INDEX_op_movcond_i32
:
1052 case INDEX_op_brcond2_i32
:
1053 case INDEX_op_setcond2_i32
:
1054 case INDEX_op_brcond_i64
:
1055 case INDEX_op_setcond_i64
:
1056 case INDEX_op_movcond_i64
:
1057 if (args
[k
] < ARRAY_SIZE(cond_name
) && cond_name
[args
[k
]]) {
1058 qemu_log(",%s", cond_name
[args
[k
++]]);
1060 qemu_log(",$0x%" TCG_PRIlx
, args
[k
++]);
1064 case INDEX_op_qemu_ld_i32
:
1065 case INDEX_op_qemu_st_i32
:
1066 case INDEX_op_qemu_ld_i64
:
1067 case INDEX_op_qemu_st_i64
:
1069 TCGMemOpIdx oi
= args
[k
++];
1070 TCGMemOp op
= get_memop(oi
);
1071 unsigned ix
= get_mmuidx(oi
);
1073 if (op
& ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
)) {
1074 qemu_log(",$0x%x,%u", op
, ix
);
1076 const char *s_al
= "", *s_op
;
1077 if (op
& MO_AMASK
) {
1078 if ((op
& MO_AMASK
) == MO_ALIGN
) {
1084 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
1085 qemu_log(",%s%s,%u", s_al
, s_op
, ix
);
1095 case INDEX_op_set_label
:
1097 case INDEX_op_brcond_i32
:
1098 case INDEX_op_brcond_i64
:
1099 case INDEX_op_brcond2_i32
:
1100 qemu_log("%s$L%d", k
? "," : "", arg_label(args
[k
])->id
);
1106 for (; i
< nb_cargs
; i
++, k
++) {
1107 qemu_log("%s$0x%" TCG_PRIlx
, k
? "," : "", args
[k
]);
1114 /* we give more priority to constraints with less registers */
1115 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
1117 const TCGArgConstraint
*arg_ct
;
1120 arg_ct
= &def
->args_ct
[k
];
1121 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
1122 /* an alias is equivalent to a single register */
1125 if (!(arg_ct
->ct
& TCG_CT_REG
))
1128 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1129 if (tcg_regset_test_reg(arg_ct
->u
.regs
, i
))
1133 return TCG_TARGET_NB_REGS
- n
+ 1;
1136 /* sort from highest priority to lowest */
1137 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
1139 int i
, j
, p1
, p2
, tmp
;
1141 for(i
= 0; i
< n
; i
++)
1142 def
->sorted_args
[start
+ i
] = start
+ i
;
1145 for(i
= 0; i
< n
- 1; i
++) {
1146 for(j
= i
+ 1; j
< n
; j
++) {
1147 p1
= get_constraint_priority(def
, def
->sorted_args
[start
+ i
]);
1148 p2
= get_constraint_priority(def
, def
->sorted_args
[start
+ j
]);
1150 tmp
= def
->sorted_args
[start
+ i
];
1151 def
->sorted_args
[start
+ i
] = def
->sorted_args
[start
+ j
];
1152 def
->sorted_args
[start
+ j
] = tmp
;
1158 void tcg_add_target_add_op_defs(const TCGTargetOpDef
*tdefs
)
1166 if (tdefs
->op
== (TCGOpcode
)-1)
1169 assert((unsigned)op
< NB_OPS
);
1170 def
= &tcg_op_defs
[op
];
1171 #if defined(CONFIG_DEBUG_TCG)
1172 /* Duplicate entry in op definitions? */
1176 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
1177 for(i
= 0; i
< nb_args
; i
++) {
1178 ct_str
= tdefs
->args_ct_str
[i
];
1179 /* Incomplete TCGTargetOpDef entry? */
1180 assert(ct_str
!= NULL
);
1181 tcg_regset_clear(def
->args_ct
[i
].u
.regs
);
1182 def
->args_ct
[i
].ct
= 0;
1183 if (ct_str
[0] >= '0' && ct_str
[0] <= '9') {
1185 oarg
= ct_str
[0] - '0';
1186 assert(oarg
< def
->nb_oargs
);
1187 assert(def
->args_ct
[oarg
].ct
& TCG_CT_REG
);
1188 /* TCG_CT_ALIAS is for the output arguments. The input
1189 argument is tagged with TCG_CT_IALIAS. */
1190 def
->args_ct
[i
] = def
->args_ct
[oarg
];
1191 def
->args_ct
[oarg
].ct
= TCG_CT_ALIAS
;
1192 def
->args_ct
[oarg
].alias_index
= i
;
1193 def
->args_ct
[i
].ct
|= TCG_CT_IALIAS
;
1194 def
->args_ct
[i
].alias_index
= oarg
;
1197 if (*ct_str
== '\0')
1201 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
1205 if (target_parse_constraint(&def
->args_ct
[i
], &ct_str
) < 0) {
1206 fprintf(stderr
, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1207 ct_str
, i
, def
->name
);
1215 /* TCGTargetOpDef entry with too much information? */
1216 assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
1218 /* sort the constraints (XXX: this is just an heuristic) */
1219 sort_constraints(def
, 0, def
->nb_oargs
);
1220 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
1226 printf("%s: sorted=", def
->name
);
1227 for(i
= 0; i
< def
->nb_oargs
+ def
->nb_iargs
; i
++)
1228 printf(" %d", def
->sorted_args
[i
]);
1235 #if defined(CONFIG_DEBUG_TCG)
1237 for (op
= 0; op
< tcg_op_defs_max
; op
++) {
1238 const TCGOpDef
*def
= &tcg_op_defs
[op
];
1239 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
1240 /* Wrong entry in op definitions? */
1242 fprintf(stderr
, "Invalid op definition for %s\n", def
->name
);
1246 /* Missing entry in op definitions? */
1248 fprintf(stderr
, "Missing op definition for %s\n", def
->name
);
1259 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
1261 int next
= op
->next
;
1262 int prev
= op
->prev
;
1265 s
->gen_op_buf
[next
].prev
= prev
;
1267 s
->gen_last_op_idx
= prev
;
1270 s
->gen_op_buf
[prev
].next
= next
;
1272 s
->gen_first_op_idx
= next
;
1275 memset(op
, -1, sizeof(*op
));
1277 #ifdef CONFIG_PROFILER
1282 #ifdef USE_LIVENESS_ANALYSIS
1283 /* liveness analysis: end of function: all temps are dead, and globals
1284 should be in memory. */
1285 static inline void tcg_la_func_end(TCGContext
*s
, uint8_t *dead_temps
,
1288 memset(dead_temps
, 1, s
->nb_temps
);
1289 memset(mem_temps
, 1, s
->nb_globals
);
1290 memset(mem_temps
+ s
->nb_globals
, 0, s
->nb_temps
- s
->nb_globals
);
1293 /* liveness analysis: end of basic block: all temps are dead, globals
1294 and local temps should be in memory. */
1295 static inline void tcg_la_bb_end(TCGContext
*s
, uint8_t *dead_temps
,
1300 memset(dead_temps
, 1, s
->nb_temps
);
1301 memset(mem_temps
, 1, s
->nb_globals
);
1302 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1303 mem_temps
[i
] = s
->temps
[i
].temp_local
;
1307 /* Liveness analysis : update the opc_dead_args array to tell if a
1308 given input arguments is dead. Instructions updating dead
1309 temporaries are removed. */
1310 static void tcg_liveness_analysis(TCGContext
*s
)
1312 uint8_t *dead_temps
, *mem_temps
;
1313 int oi
, oi_prev
, nb_ops
;
1315 nb_ops
= s
->gen_next_op_idx
;
1316 s
->op_dead_args
= tcg_malloc(nb_ops
* sizeof(uint16_t));
1317 s
->op_sync_args
= tcg_malloc(nb_ops
* sizeof(uint8_t));
1319 dead_temps
= tcg_malloc(s
->nb_temps
);
1320 mem_temps
= tcg_malloc(s
->nb_temps
);
1321 tcg_la_func_end(s
, dead_temps
, mem_temps
);
1323 for (oi
= s
->gen_last_op_idx
; oi
>= 0; oi
= oi_prev
) {
1324 int i
, nb_iargs
, nb_oargs
;
1325 TCGOpcode opc_new
, opc_new2
;
1331 TCGOp
* const op
= &s
->gen_op_buf
[oi
];
1332 TCGArg
* const args
= &s
->gen_opparam_buf
[op
->args
];
1333 TCGOpcode opc
= op
->opc
;
1334 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
1343 nb_oargs
= op
->callo
;
1344 nb_iargs
= op
->calli
;
1345 call_flags
= args
[nb_oargs
+ nb_iargs
+ 1];
1347 /* pure functions can be removed if their result is unused */
1348 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
1349 for (i
= 0; i
< nb_oargs
; i
++) {
1351 if (!dead_temps
[arg
] || mem_temps
[arg
]) {
1352 goto do_not_remove_call
;
1359 /* output args are dead */
1362 for (i
= 0; i
< nb_oargs
; i
++) {
1364 if (dead_temps
[arg
]) {
1365 dead_args
|= (1 << i
);
1367 if (mem_temps
[arg
]) {
1368 sync_args
|= (1 << i
);
1370 dead_temps
[arg
] = 1;
1374 if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
1375 /* globals should be synced to memory */
1376 memset(mem_temps
, 1, s
->nb_globals
);
1378 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
1379 TCG_CALL_NO_READ_GLOBALS
))) {
1380 /* globals should go back to memory */
1381 memset(dead_temps
, 1, s
->nb_globals
);
1384 /* record arguments that die in this helper */
1385 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1387 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1388 if (dead_temps
[arg
]) {
1389 dead_args
|= (1 << i
);
1393 /* input arguments are live for preceding opcodes */
1394 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1396 dead_temps
[arg
] = 0;
1398 s
->op_dead_args
[oi
] = dead_args
;
1399 s
->op_sync_args
[oi
] = sync_args
;
1403 case INDEX_op_debug_insn_start
:
1405 case INDEX_op_discard
:
1406 /* mark the temporary as dead */
1407 dead_temps
[args
[0]] = 1;
1408 mem_temps
[args
[0]] = 0;
1411 case INDEX_op_add2_i32
:
1412 opc_new
= INDEX_op_add_i32
;
1414 case INDEX_op_sub2_i32
:
1415 opc_new
= INDEX_op_sub_i32
;
1417 case INDEX_op_add2_i64
:
1418 opc_new
= INDEX_op_add_i64
;
1420 case INDEX_op_sub2_i64
:
1421 opc_new
= INDEX_op_sub_i64
;
1425 /* Test if the high part of the operation is dead, but not
1426 the low part. The result can be optimized to a simple
1427 add or sub. This happens often for x86_64 guest when the
1428 cpu mode is set to 32 bit. */
1429 if (dead_temps
[args
[1]] && !mem_temps
[args
[1]]) {
1430 if (dead_temps
[args
[0]] && !mem_temps
[args
[0]]) {
1433 /* Replace the opcode and adjust the args in place,
1434 leaving 3 unused args at the end. */
1435 op
->opc
= opc
= opc_new
;
1438 /* Fall through and mark the single-word operation live. */
1444 case INDEX_op_mulu2_i32
:
1445 opc_new
= INDEX_op_mul_i32
;
1446 opc_new2
= INDEX_op_muluh_i32
;
1447 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
1449 case INDEX_op_muls2_i32
:
1450 opc_new
= INDEX_op_mul_i32
;
1451 opc_new2
= INDEX_op_mulsh_i32
;
1452 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
1454 case INDEX_op_mulu2_i64
:
1455 opc_new
= INDEX_op_mul_i64
;
1456 opc_new2
= INDEX_op_muluh_i64
;
1457 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
1459 case INDEX_op_muls2_i64
:
1460 opc_new
= INDEX_op_mul_i64
;
1461 opc_new2
= INDEX_op_mulsh_i64
;
1462 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
1467 if (dead_temps
[args
[1]] && !mem_temps
[args
[1]]) {
1468 if (dead_temps
[args
[0]] && !mem_temps
[args
[0]]) {
1469 /* Both parts of the operation are dead. */
1472 /* The high part of the operation is dead; generate the low. */
1473 op
->opc
= opc
= opc_new
;
1476 } else if (have_opc_new2
&& dead_temps
[args
[0]]
1477 && !mem_temps
[args
[0]]) {
1478 /* The low part of the operation is dead; generate the high. */
1479 op
->opc
= opc
= opc_new2
;
1486 /* Mark the single-word operation live. */
1491 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
1492 nb_iargs
= def
->nb_iargs
;
1493 nb_oargs
= def
->nb_oargs
;
1495 /* Test if the operation can be removed because all
1496 its outputs are dead. We assume that nb_oargs == 0
1497 implies side effects */
1498 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
1499 for (i
= 0; i
< nb_oargs
; i
++) {
1501 if (!dead_temps
[arg
] || mem_temps
[arg
]) {
1506 tcg_op_remove(s
, op
);
1509 /* output args are dead */
1512 for (i
= 0; i
< nb_oargs
; i
++) {
1514 if (dead_temps
[arg
]) {
1515 dead_args
|= (1 << i
);
1517 if (mem_temps
[arg
]) {
1518 sync_args
|= (1 << i
);
1520 dead_temps
[arg
] = 1;
1524 /* if end of basic block, update */
1525 if (def
->flags
& TCG_OPF_BB_END
) {
1526 tcg_la_bb_end(s
, dead_temps
, mem_temps
);
1527 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
1528 /* globals should be synced to memory */
1529 memset(mem_temps
, 1, s
->nb_globals
);
1532 /* record arguments that die in this opcode */
1533 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1535 if (dead_temps
[arg
]) {
1536 dead_args
|= (1 << i
);
1539 /* input arguments are live for preceding opcodes */
1540 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1542 dead_temps
[arg
] = 0;
1544 s
->op_dead_args
[oi
] = dead_args
;
1545 s
->op_sync_args
[oi
] = sync_args
;
1552 /* dummy liveness analysis */
1553 static void tcg_liveness_analysis(TCGContext
*s
)
1556 nb_ops
= s
->gen_opc_ptr
- s
->gen_opc_buf
;
1558 s
->op_dead_args
= tcg_malloc(nb_ops
* sizeof(uint16_t));
1559 memset(s
->op_dead_args
, 0, nb_ops
* sizeof(uint16_t));
1560 s
->op_sync_args
= tcg_malloc(nb_ops
* sizeof(uint8_t));
1561 memset(s
->op_sync_args
, 0, nb_ops
* sizeof(uint8_t));
1566 static void dump_regs(TCGContext
*s
)
1572 for(i
= 0; i
< s
->nb_temps
; i
++) {
1574 printf(" %10s: ", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), i
));
1575 switch(ts
->val_type
) {
1577 printf("%s", tcg_target_reg_names
[ts
->reg
]);
1580 printf("%d(%s)", (int)ts
->mem_offset
, tcg_target_reg_names
[ts
->mem_reg
]);
1582 case TEMP_VAL_CONST
:
1583 printf("$0x%" TCG_PRIlx
, ts
->val
);
1595 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1596 if (s
->reg_to_temp
[i
] >= 0) {
1598 tcg_target_reg_names
[i
],
1599 tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), s
->reg_to_temp
[i
]));
1604 static void check_regs(TCGContext
*s
)
1610 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
1611 k
= s
->reg_to_temp
[reg
];
1614 if (ts
->val_type
!= TEMP_VAL_REG
||
1616 printf("Inconsistency for register %s:\n",
1617 tcg_target_reg_names
[reg
]);
1622 for(k
= 0; k
< s
->nb_temps
; k
++) {
1624 if (ts
->val_type
== TEMP_VAL_REG
&&
1626 s
->reg_to_temp
[ts
->reg
] != k
) {
1627 printf("Inconsistency for temp %s:\n",
1628 tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), k
));
1630 printf("reg state:\n");
1638 static void temp_allocate_frame(TCGContext
*s
, int temp
)
1641 ts
= &s
->temps
[temp
];
1642 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1643 /* Sparc64 stack is accessed with offset of 2047 */
1644 s
->current_frame_offset
= (s
->current_frame_offset
+
1645 (tcg_target_long
)sizeof(tcg_target_long
) - 1) &
1646 ~(sizeof(tcg_target_long
) - 1);
1648 if (s
->current_frame_offset
+ (tcg_target_long
)sizeof(tcg_target_long
) >
1652 ts
->mem_offset
= s
->current_frame_offset
;
1653 ts
->mem_reg
= s
->frame_reg
;
1654 ts
->mem_allocated
= 1;
1655 s
->current_frame_offset
+= sizeof(tcg_target_long
);
1658 /* sync register 'reg' by saving it to the corresponding temporary */
1659 static inline void tcg_reg_sync(TCGContext
*s
, int reg
)
1664 temp
= s
->reg_to_temp
[reg
];
1665 ts
= &s
->temps
[temp
];
1666 assert(ts
->val_type
== TEMP_VAL_REG
);
1667 if (!ts
->mem_coherent
&& !ts
->fixed_reg
) {
1668 if (!ts
->mem_allocated
) {
1669 temp_allocate_frame(s
, temp
);
1671 tcg_out_st(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
1673 ts
->mem_coherent
= 1;
1676 /* free register 'reg' by spilling the corresponding temporary if necessary */
1677 static void tcg_reg_free(TCGContext
*s
, int reg
)
1681 temp
= s
->reg_to_temp
[reg
];
1683 tcg_reg_sync(s
, reg
);
1684 s
->temps
[temp
].val_type
= TEMP_VAL_MEM
;
1685 s
->reg_to_temp
[reg
] = -1;
1689 /* Allocate a register belonging to reg1 & ~reg2 */
1690 static int tcg_reg_alloc(TCGContext
*s
, TCGRegSet reg1
, TCGRegSet reg2
)
1695 tcg_regset_andnot(reg_ct
, reg1
, reg2
);
1697 /* first try free registers */
1698 for(i
= 0; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); i
++) {
1699 reg
= tcg_target_reg_alloc_order
[i
];
1700 if (tcg_regset_test_reg(reg_ct
, reg
) && s
->reg_to_temp
[reg
] == -1)
1704 /* XXX: do better spill choice */
1705 for(i
= 0; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); i
++) {
1706 reg
= tcg_target_reg_alloc_order
[i
];
1707 if (tcg_regset_test_reg(reg_ct
, reg
)) {
1708 tcg_reg_free(s
, reg
);
1716 /* mark a temporary as dead. */
1717 static inline void temp_dead(TCGContext
*s
, int temp
)
1721 ts
= &s
->temps
[temp
];
1722 if (!ts
->fixed_reg
) {
1723 if (ts
->val_type
== TEMP_VAL_REG
) {
1724 s
->reg_to_temp
[ts
->reg
] = -1;
1726 if (temp
< s
->nb_globals
|| ts
->temp_local
) {
1727 ts
->val_type
= TEMP_VAL_MEM
;
1729 ts
->val_type
= TEMP_VAL_DEAD
;
1734 /* sync a temporary to memory. 'allocated_regs' is used in case a
1735 temporary registers needs to be allocated to store a constant. */
1736 static inline void temp_sync(TCGContext
*s
, int temp
, TCGRegSet allocated_regs
)
1740 ts
= &s
->temps
[temp
];
1741 if (!ts
->fixed_reg
) {
1742 switch(ts
->val_type
) {
1743 case TEMP_VAL_CONST
:
1744 ts
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
1746 ts
->val_type
= TEMP_VAL_REG
;
1747 s
->reg_to_temp
[ts
->reg
] = temp
;
1748 ts
->mem_coherent
= 0;
1749 tcg_out_movi(s
, ts
->type
, ts
->reg
, ts
->val
);
1752 tcg_reg_sync(s
, ts
->reg
);
1763 /* save a temporary to memory. 'allocated_regs' is used in case a
1764 temporary registers needs to be allocated to store a constant. */
1765 static inline void temp_save(TCGContext
*s
, int temp
, TCGRegSet allocated_regs
)
1767 #ifdef USE_LIVENESS_ANALYSIS
1768 /* The liveness analysis already ensures that globals are back
1769 in memory. Keep an assert for safety. */
1770 assert(s
->temps
[temp
].val_type
== TEMP_VAL_MEM
|| s
->temps
[temp
].fixed_reg
);
1772 temp_sync(s
, temp
, allocated_regs
);
1777 /* save globals to their canonical location and assume they can be
1778 modified be the following code. 'allocated_regs' is used in case a
1779 temporary registers needs to be allocated to store a constant. */
1780 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
1784 for(i
= 0; i
< s
->nb_globals
; i
++) {
1785 temp_save(s
, i
, allocated_regs
);
1789 /* sync globals to their canonical location and assume they can be
1790 read by the following code. 'allocated_regs' is used in case a
1791 temporary registers needs to be allocated to store a constant. */
1792 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
1796 for (i
= 0; i
< s
->nb_globals
; i
++) {
1797 #ifdef USE_LIVENESS_ANALYSIS
1798 assert(s
->temps
[i
].val_type
!= TEMP_VAL_REG
|| s
->temps
[i
].fixed_reg
||
1799 s
->temps
[i
].mem_coherent
);
1801 temp_sync(s
, i
, allocated_regs
);
1806 /* at the end of a basic block, we assume all temporaries are dead and
1807 all globals are stored at their canonical location. */
1808 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
1813 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
1815 if (ts
->temp_local
) {
1816 temp_save(s
, i
, allocated_regs
);
1818 #ifdef USE_LIVENESS_ANALYSIS
1819 /* The liveness analysis already ensures that temps are dead.
1820 Keep an assert for safety. */
1821 assert(ts
->val_type
== TEMP_VAL_DEAD
);
1828 save_globals(s
, allocated_regs
);
1831 #define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
1832 #define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
1834 static void tcg_reg_alloc_movi(TCGContext
*s
, const TCGArg
*args
,
1835 uint16_t dead_args
, uint8_t sync_args
)
1838 tcg_target_ulong val
;
1840 ots
= &s
->temps
[args
[0]];
1843 if (ots
->fixed_reg
) {
1844 /* for fixed registers, we do not do any constant
1846 tcg_out_movi(s
, ots
->type
, ots
->reg
, val
);
1848 /* The movi is not explicitly generated here */
1849 if (ots
->val_type
== TEMP_VAL_REG
)
1850 s
->reg_to_temp
[ots
->reg
] = -1;
1851 ots
->val_type
= TEMP_VAL_CONST
;
1854 if (NEED_SYNC_ARG(0)) {
1855 temp_sync(s
, args
[0], s
->reserved_regs
);
1857 if (IS_DEAD_ARG(0)) {
1858 temp_dead(s
, args
[0]);
1862 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOpDef
*def
,
1863 const TCGArg
*args
, uint16_t dead_args
,
1866 TCGRegSet allocated_regs
;
1868 TCGType otype
, itype
;
1870 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
1871 ots
= &s
->temps
[args
[0]];
1872 ts
= &s
->temps
[args
[1]];
1874 /* Note that otype != itype for no-op truncation. */
1878 /* If the source value is not in a register, and we're going to be
1879 forced to have it in a register in order to perform the copy,
1880 then copy the SOURCE value into its own register first. That way
1881 we don't have to reload SOURCE the next time it is used. */
1882 if (((NEED_SYNC_ARG(0) || ots
->fixed_reg
) && ts
->val_type
!= TEMP_VAL_REG
)
1883 || ts
->val_type
== TEMP_VAL_MEM
) {
1884 ts
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[itype
],
1886 if (ts
->val_type
== TEMP_VAL_MEM
) {
1887 tcg_out_ld(s
, itype
, ts
->reg
, ts
->mem_reg
, ts
->mem_offset
);
1888 ts
->mem_coherent
= 1;
1889 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
1890 tcg_out_movi(s
, itype
, ts
->reg
, ts
->val
);
1891 ts
->mem_coherent
= 0;
1893 s
->reg_to_temp
[ts
->reg
] = args
[1];
1894 ts
->val_type
= TEMP_VAL_REG
;
1897 if (IS_DEAD_ARG(0) && !ots
->fixed_reg
) {
1898 /* mov to a non-saved dead register makes no sense (even with
1899 liveness analysis disabled). */
1900 assert(NEED_SYNC_ARG(0));
1901 /* The code above should have moved the temp to a register. */
1902 assert(ts
->val_type
== TEMP_VAL_REG
);
1903 if (!ots
->mem_allocated
) {
1904 temp_allocate_frame(s
, args
[0]);
1906 tcg_out_st(s
, otype
, ts
->reg
, ots
->mem_reg
, ots
->mem_offset
);
1907 if (IS_DEAD_ARG(1)) {
1908 temp_dead(s
, args
[1]);
1910 temp_dead(s
, args
[0]);
1911 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
1912 /* propagate constant */
1913 if (ots
->val_type
== TEMP_VAL_REG
) {
1914 s
->reg_to_temp
[ots
->reg
] = -1;
1916 ots
->val_type
= TEMP_VAL_CONST
;
1918 if (IS_DEAD_ARG(1)) {
1919 temp_dead(s
, args
[1]);
1922 /* The code in the first if block should have moved the
1923 temp to a register. */
1924 assert(ts
->val_type
== TEMP_VAL_REG
);
1925 if (IS_DEAD_ARG(1) && !ts
->fixed_reg
&& !ots
->fixed_reg
) {
1926 /* the mov can be suppressed */
1927 if (ots
->val_type
== TEMP_VAL_REG
) {
1928 s
->reg_to_temp
[ots
->reg
] = -1;
1931 temp_dead(s
, args
[1]);
1933 if (ots
->val_type
!= TEMP_VAL_REG
) {
1934 /* When allocating a new register, make sure to not spill the
1936 tcg_regset_set_reg(allocated_regs
, ts
->reg
);
1937 ots
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
1940 tcg_out_mov(s
, otype
, ots
->reg
, ts
->reg
);
1942 ots
->val_type
= TEMP_VAL_REG
;
1943 ots
->mem_coherent
= 0;
1944 s
->reg_to_temp
[ots
->reg
] = args
[0];
1945 if (NEED_SYNC_ARG(0)) {
1946 tcg_reg_sync(s
, ots
->reg
);
1951 static void tcg_reg_alloc_op(TCGContext
*s
,
1952 const TCGOpDef
*def
, TCGOpcode opc
,
1953 const TCGArg
*args
, uint16_t dead_args
,
1956 TCGRegSet allocated_regs
;
1957 int i
, k
, nb_iargs
, nb_oargs
, reg
;
1959 const TCGArgConstraint
*arg_ct
;
1961 TCGArg new_args
[TCG_MAX_OP_ARGS
];
1962 int const_args
[TCG_MAX_OP_ARGS
];
1964 nb_oargs
= def
->nb_oargs
;
1965 nb_iargs
= def
->nb_iargs
;
1967 /* copy constants */
1968 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
1969 args
+ nb_oargs
+ nb_iargs
,
1970 sizeof(TCGArg
) * def
->nb_cargs
);
1972 /* satisfy input constraints */
1973 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
1974 for(k
= 0; k
< nb_iargs
; k
++) {
1975 i
= def
->sorted_args
[nb_oargs
+ k
];
1977 arg_ct
= &def
->args_ct
[i
];
1978 ts
= &s
->temps
[arg
];
1979 if (ts
->val_type
== TEMP_VAL_MEM
) {
1980 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
1981 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
1982 ts
->val_type
= TEMP_VAL_REG
;
1984 ts
->mem_coherent
= 1;
1985 s
->reg_to_temp
[reg
] = arg
;
1986 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
1987 if (tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
)) {
1988 /* constant is OK for instruction */
1990 new_args
[i
] = ts
->val
;
1993 /* need to move to a register */
1994 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
1995 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
1996 ts
->val_type
= TEMP_VAL_REG
;
1998 ts
->mem_coherent
= 0;
1999 s
->reg_to_temp
[reg
] = arg
;
2002 assert(ts
->val_type
== TEMP_VAL_REG
);
2003 if (arg_ct
->ct
& TCG_CT_IALIAS
) {
2004 if (ts
->fixed_reg
) {
2005 /* if fixed register, we must allocate a new register
2006 if the alias is not the same register */
2007 if (arg
!= args
[arg_ct
->alias_index
])
2008 goto allocate_in_reg
;
2010 /* if the input is aliased to an output and if it is
2011 not dead after the instruction, we must allocate
2012 a new register and move it */
2013 if (!IS_DEAD_ARG(i
)) {
2014 goto allocate_in_reg
;
2016 /* check if the current register has already been allocated
2017 for another input aliased to an output */
2019 for (k2
= 0 ; k2
< k
; k2
++) {
2020 i2
= def
->sorted_args
[nb_oargs
+ k2
];
2021 if ((def
->args_ct
[i2
].ct
& TCG_CT_IALIAS
) &&
2022 (new_args
[i2
] == ts
->reg
)) {
2023 goto allocate_in_reg
;
2029 if (tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2030 /* nothing to do : the constraint is satisfied */
2033 /* allocate a new register matching the constraint
2034 and move the temporary register into it */
2035 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2036 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2040 tcg_regset_set_reg(allocated_regs
, reg
);
2044 /* mark dead temporaries and free the associated registers */
2045 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
2046 if (IS_DEAD_ARG(i
)) {
2047 temp_dead(s
, args
[i
]);
2051 if (def
->flags
& TCG_OPF_BB_END
) {
2052 tcg_reg_alloc_bb_end(s
, allocated_regs
);
2054 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
2055 /* XXX: permit generic clobber register list ? */
2056 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
2057 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, reg
)) {
2058 tcg_reg_free(s
, reg
);
2062 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
2063 /* sync globals if the op has side effects and might trigger
2065 sync_globals(s
, allocated_regs
);
2068 /* satisfy the output constraints */
2069 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2070 for(k
= 0; k
< nb_oargs
; k
++) {
2071 i
= def
->sorted_args
[k
];
2073 arg_ct
= &def
->args_ct
[i
];
2074 ts
= &s
->temps
[arg
];
2075 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
2076 reg
= new_args
[arg_ct
->alias_index
];
2078 /* if fixed register, we try to use it */
2080 if (ts
->fixed_reg
&&
2081 tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2084 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, allocated_regs
);
2086 tcg_regset_set_reg(allocated_regs
, reg
);
2087 /* if a fixed register is used, then a move will be done afterwards */
2088 if (!ts
->fixed_reg
) {
2089 if (ts
->val_type
== TEMP_VAL_REG
) {
2090 s
->reg_to_temp
[ts
->reg
] = -1;
2092 ts
->val_type
= TEMP_VAL_REG
;
2094 /* temp value is modified, so the value kept in memory is
2095 potentially not the same */
2096 ts
->mem_coherent
= 0;
2097 s
->reg_to_temp
[reg
] = arg
;
2104 /* emit instruction */
2105 tcg_out_op(s
, opc
, new_args
, const_args
);
2107 /* move the outputs in the correct register if needed */
2108 for(i
= 0; i
< nb_oargs
; i
++) {
2109 ts
= &s
->temps
[args
[i
]];
2111 if (ts
->fixed_reg
&& ts
->reg
!= reg
) {
2112 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2114 if (NEED_SYNC_ARG(i
)) {
2115 tcg_reg_sync(s
, reg
);
2117 if (IS_DEAD_ARG(i
)) {
2118 temp_dead(s
, args
[i
]);
2123 #ifdef TCG_TARGET_STACK_GROWSUP
2124 #define STACK_DIR(x) (-(x))
2126 #define STACK_DIR(x) (x)
2129 static void tcg_reg_alloc_call(TCGContext
*s
, int nb_oargs
, int nb_iargs
,
2130 const TCGArg
* const args
, uint16_t dead_args
,
2133 int flags
, nb_regs
, i
, reg
;
2136 intptr_t stack_offset
;
2137 size_t call_stack_size
;
2138 tcg_insn_unit
*func_addr
;
2140 TCGRegSet allocated_regs
;
2142 func_addr
= (tcg_insn_unit
*)(intptr_t)args
[nb_oargs
+ nb_iargs
];
2143 flags
= args
[nb_oargs
+ nb_iargs
+ 1];
2145 nb_regs
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
2146 if (nb_regs
> nb_iargs
) {
2150 /* assign stack slots first */
2151 call_stack_size
= (nb_iargs
- nb_regs
) * sizeof(tcg_target_long
);
2152 call_stack_size
= (call_stack_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
2153 ~(TCG_TARGET_STACK_ALIGN
- 1);
2154 allocate_args
= (call_stack_size
> TCG_STATIC_CALL_ARGS_SIZE
);
2155 if (allocate_args
) {
2156 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2157 preallocate call stack */
2161 stack_offset
= TCG_TARGET_CALL_STACK_OFFSET
;
2162 for(i
= nb_regs
; i
< nb_iargs
; i
++) {
2163 arg
= args
[nb_oargs
+ i
];
2164 #ifdef TCG_TARGET_STACK_GROWSUP
2165 stack_offset
-= sizeof(tcg_target_long
);
2167 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2168 ts
= &s
->temps
[arg
];
2169 if (ts
->val_type
== TEMP_VAL_REG
) {
2170 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
, stack_offset
);
2171 } else if (ts
->val_type
== TEMP_VAL_MEM
) {
2172 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
2174 /* XXX: not correct if reading values from the stack */
2175 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2176 tcg_out_st(s
, ts
->type
, reg
, TCG_REG_CALL_STACK
, stack_offset
);
2177 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2178 reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[ts
->type
],
2180 /* XXX: sign extend may be needed on some targets */
2181 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2182 tcg_out_st(s
, ts
->type
, reg
, TCG_REG_CALL_STACK
, stack_offset
);
2187 #ifndef TCG_TARGET_STACK_GROWSUP
2188 stack_offset
+= sizeof(tcg_target_long
);
2192 /* assign input registers */
2193 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2194 for(i
= 0; i
< nb_regs
; i
++) {
2195 arg
= args
[nb_oargs
+ i
];
2196 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2197 ts
= &s
->temps
[arg
];
2198 reg
= tcg_target_call_iarg_regs
[i
];
2199 tcg_reg_free(s
, reg
);
2200 if (ts
->val_type
== TEMP_VAL_REG
) {
2201 if (ts
->reg
!= reg
) {
2202 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2204 } else if (ts
->val_type
== TEMP_VAL_MEM
) {
2205 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_reg
, ts
->mem_offset
);
2206 } else if (ts
->val_type
== TEMP_VAL_CONST
) {
2207 /* XXX: sign extend ? */
2208 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2212 tcg_regset_set_reg(allocated_regs
, reg
);
2216 /* mark dead temporaries and free the associated registers */
2217 for(i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
2218 if (IS_DEAD_ARG(i
)) {
2219 temp_dead(s
, args
[i
]);
2223 /* clobber call registers */
2224 for(reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
2225 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, reg
)) {
2226 tcg_reg_free(s
, reg
);
2230 /* Save globals if they might be written by the helper, sync them if
2231 they might be read. */
2232 if (flags
& TCG_CALL_NO_READ_GLOBALS
) {
2234 } else if (flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
2235 sync_globals(s
, allocated_regs
);
2237 save_globals(s
, allocated_regs
);
2240 tcg_out_call(s
, func_addr
);
2242 /* assign output registers and emit moves if needed */
2243 for(i
= 0; i
< nb_oargs
; i
++) {
2245 ts
= &s
->temps
[arg
];
2246 reg
= tcg_target_call_oarg_regs
[i
];
2247 assert(s
->reg_to_temp
[reg
] == -1);
2249 if (ts
->fixed_reg
) {
2250 if (ts
->reg
!= reg
) {
2251 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2254 if (ts
->val_type
== TEMP_VAL_REG
) {
2255 s
->reg_to_temp
[ts
->reg
] = -1;
2257 ts
->val_type
= TEMP_VAL_REG
;
2259 ts
->mem_coherent
= 0;
2260 s
->reg_to_temp
[reg
] = arg
;
2261 if (NEED_SYNC_ARG(i
)) {
2262 tcg_reg_sync(s
, reg
);
2264 if (IS_DEAD_ARG(i
)) {
2265 temp_dead(s
, args
[i
]);
2271 #ifdef CONFIG_PROFILER
2273 static int64_t tcg_table_op_count
[NB_OPS
];
2275 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
)
2279 for (i
= 0; i
< NB_OPS
; i
++) {
2280 cpu_fprintf(f
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
2281 tcg_table_op_count
[i
]);
2285 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
)
2287 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2292 static inline int tcg_gen_code_common(TCGContext
*s
,
2293 tcg_insn_unit
*gen_code_buf
,
2299 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
2306 #ifdef CONFIG_PROFILER
2307 s
->opt_time
-= profile_getclock();
2310 #ifdef USE_TCG_OPTIMIZATIONS
2314 #ifdef CONFIG_PROFILER
2315 s
->opt_time
+= profile_getclock();
2316 s
->la_time
-= profile_getclock();
2319 tcg_liveness_analysis(s
);
2321 #ifdef CONFIG_PROFILER
2322 s
->la_time
+= profile_getclock();
2326 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
))) {
2327 qemu_log("OP after optimization and liveness analysis:\n");
2333 tcg_reg_alloc_start(s
);
2335 s
->code_buf
= gen_code_buf
;
2336 s
->code_ptr
= gen_code_buf
;
2340 for (oi
= s
->gen_first_op_idx
; oi
>= 0; oi
= oi_next
) {
2341 TCGOp
* const op
= &s
->gen_op_buf
[oi
];
2342 TCGArg
* const args
= &s
->gen_opparam_buf
[op
->args
];
2343 TCGOpcode opc
= op
->opc
;
2344 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
2345 uint16_t dead_args
= s
->op_dead_args
[oi
];
2346 uint8_t sync_args
= s
->op_sync_args
[oi
];
2349 #ifdef CONFIG_PROFILER
2350 tcg_table_op_count
[opc
]++;
2354 case INDEX_op_mov_i32
:
2355 case INDEX_op_mov_i64
:
2356 tcg_reg_alloc_mov(s
, def
, args
, dead_args
, sync_args
);
2358 case INDEX_op_movi_i32
:
2359 case INDEX_op_movi_i64
:
2360 tcg_reg_alloc_movi(s
, args
, dead_args
, sync_args
);
2362 case INDEX_op_debug_insn_start
:
2364 case INDEX_op_discard
:
2365 temp_dead(s
, args
[0]);
2367 case INDEX_op_set_label
:
2368 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
2369 tcg_out_label(s
, arg_label(args
[0]), s
->code_ptr
);
2372 tcg_reg_alloc_call(s
, op
->callo
, op
->calli
, args
,
2373 dead_args
, sync_args
);
2376 /* Sanity check that we've not introduced any unhandled opcodes. */
2377 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2380 /* Note: in order to speed up the code, it would be much
2381 faster to have specialized register allocator functions for
2382 some common argument patterns */
2383 tcg_reg_alloc_op(s
, def
, opc
, args
, dead_args
, sync_args
);
2386 if (search_pc
>= 0 && search_pc
< tcg_current_code_size(s
)) {
2394 /* Generate TB finalization at the end of block */
2395 tcg_out_tb_finalize(s
);
2399 int tcg_gen_code(TCGContext
*s
, tcg_insn_unit
*gen_code_buf
)
2401 #ifdef CONFIG_PROFILER
2405 n
= s
->gen_last_op_idx
+ 1;
2407 if (n
> s
->op_count_max
) {
2408 s
->op_count_max
= n
;
2413 if (n
> s
->temp_count_max
) {
2414 s
->temp_count_max
= n
;
2419 tcg_gen_code_common(s
, gen_code_buf
, -1);
2421 /* flush instruction cache */
2422 flush_icache_range((uintptr_t)s
->code_buf
, (uintptr_t)s
->code_ptr
);
2424 return tcg_current_code_size(s
);
2427 /* Return the index of the micro operation such as the pc after is <
2428 offset bytes from the start of the TB. The contents of gen_code_buf must
2429 not be changed, though writing the same values is ok.
2430 Return -1 if not found. */
2431 int tcg_gen_code_search_pc(TCGContext
*s
, tcg_insn_unit
*gen_code_buf
,
2434 return tcg_gen_code_common(s
, gen_code_buf
, offset
);
2437 #ifdef CONFIG_PROFILER
2438 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2440 TCGContext
*s
= &tcg_ctx
;
2443 tot
= s
->interm_time
+ s
->code_time
;
2444 cpu_fprintf(f
, "JIT cycles %" PRId64
" (%0.3f s at 2.4 GHz)\n",
2446 cpu_fprintf(f
, "translated TBs %" PRId64
" (aborted=%" PRId64
" %0.1f%%)\n",
2448 s
->tb_count1
- s
->tb_count
,
2449 s
->tb_count1
? (double)(s
->tb_count1
- s
->tb_count
) / s
->tb_count1
* 100.0 : 0);
2450 cpu_fprintf(f
, "avg ops/TB %0.1f max=%d\n",
2451 s
->tb_count
? (double)s
->op_count
/ s
->tb_count
: 0, s
->op_count_max
);
2452 cpu_fprintf(f
, "deleted ops/TB %0.2f\n",
2454 (double)s
->del_op_count
/ s
->tb_count
: 0);
2455 cpu_fprintf(f
, "avg temps/TB %0.2f max=%d\n",
2457 (double)s
->temp_count
/ s
->tb_count
: 0,
2460 cpu_fprintf(f
, "cycles/op %0.1f\n",
2461 s
->op_count
? (double)tot
/ s
->op_count
: 0);
2462 cpu_fprintf(f
, "cycles/in byte %0.1f\n",
2463 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
2464 cpu_fprintf(f
, "cycles/out byte %0.1f\n",
2465 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
2468 cpu_fprintf(f
, " gen_interm time %0.1f%%\n",
2469 (double)s
->interm_time
/ tot
* 100.0);
2470 cpu_fprintf(f
, " gen_code time %0.1f%%\n",
2471 (double)s
->code_time
/ tot
* 100.0);
2472 cpu_fprintf(f
, "optim./code time %0.1f%%\n",
2473 (double)s
->opt_time
/ (s
->code_time
? s
->code_time
: 1)
2475 cpu_fprintf(f
, "liveness/code time %0.1f%%\n",
2476 (double)s
->la_time
/ (s
->code_time
? s
->code_time
: 1) * 100.0);
2477 cpu_fprintf(f
, "cpu_restore count %" PRId64
"\n",
2479 cpu_fprintf(f
, " avg cycles %0.1f\n",
2480 s
->restore_count
? (double)s
->restore_time
/ s
->restore_count
: 0);
2483 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2485 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2489 #ifdef ELF_HOST_MACHINE
2490 /* In order to use this feature, the backend needs to do three things:
2492 (1) Define ELF_HOST_MACHINE to indicate both what value to
2493 put into the ELF image and to indicate support for the feature.
2495 (2) Define tcg_register_jit. This should create a buffer containing
2496 the contents of a .debug_frame section that describes the post-
2497 prologue unwind info for the tcg machine.
2499 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2502 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2509 struct jit_code_entry
{
2510 struct jit_code_entry
*next_entry
;
2511 struct jit_code_entry
*prev_entry
;
2512 const void *symfile_addr
;
2513 uint64_t symfile_size
;
2516 struct jit_descriptor
{
2518 uint32_t action_flag
;
2519 struct jit_code_entry
*relevant_entry
;
2520 struct jit_code_entry
*first_entry
;
2523 void __jit_debug_register_code(void) __attribute__((noinline
));
2524 void __jit_debug_register_code(void)
2529 /* Must statically initialize the version, because GDB may check
2530 the version before we can set it. */
2531 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
2533 /* End GDB interface. */
2535 static int find_string(const char *strtab
, const char *str
)
2537 const char *p
= strtab
+ 1;
2540 if (strcmp(p
, str
) == 0) {
2547 static void tcg_register_jit_int(void *buf_ptr
, size_t buf_size
,
2548 const void *debug_frame
,
2549 size_t debug_frame_size
)
2551 struct __attribute__((packed
)) DebugInfo
{
2558 uintptr_t cu_low_pc
;
2559 uintptr_t cu_high_pc
;
2562 uintptr_t fn_low_pc
;
2563 uintptr_t fn_high_pc
;
2572 struct DebugInfo di
;
2577 struct ElfImage
*img
;
2579 static const struct ElfImage img_template
= {
2581 .e_ident
[EI_MAG0
] = ELFMAG0
,
2582 .e_ident
[EI_MAG1
] = ELFMAG1
,
2583 .e_ident
[EI_MAG2
] = ELFMAG2
,
2584 .e_ident
[EI_MAG3
] = ELFMAG3
,
2585 .e_ident
[EI_CLASS
] = ELF_CLASS
,
2586 .e_ident
[EI_DATA
] = ELF_DATA
,
2587 .e_ident
[EI_VERSION
] = EV_CURRENT
,
2589 .e_machine
= ELF_HOST_MACHINE
,
2590 .e_version
= EV_CURRENT
,
2591 .e_phoff
= offsetof(struct ElfImage
, phdr
),
2592 .e_shoff
= offsetof(struct ElfImage
, shdr
),
2593 .e_ehsize
= sizeof(ElfW(Shdr
)),
2594 .e_phentsize
= sizeof(ElfW(Phdr
)),
2596 .e_shentsize
= sizeof(ElfW(Shdr
)),
2597 .e_shnum
= ARRAY_SIZE(img
->shdr
),
2598 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
2599 #ifdef ELF_HOST_FLAGS
2600 .e_flags
= ELF_HOST_FLAGS
,
2603 .e_ident
[EI_OSABI
] = ELF_OSABI
,
2611 [0] = { .sh_type
= SHT_NULL
},
2612 /* Trick: The contents of code_gen_buffer are not present in
2613 this fake ELF file; that got allocated elsewhere. Therefore
2614 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2615 will not look for contents. We can record any address. */
2617 .sh_type
= SHT_NOBITS
,
2618 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
2620 [2] = { /* .debug_info */
2621 .sh_type
= SHT_PROGBITS
,
2622 .sh_offset
= offsetof(struct ElfImage
, di
),
2623 .sh_size
= sizeof(struct DebugInfo
),
2625 [3] = { /* .debug_abbrev */
2626 .sh_type
= SHT_PROGBITS
,
2627 .sh_offset
= offsetof(struct ElfImage
, da
),
2628 .sh_size
= sizeof(img
->da
),
2630 [4] = { /* .debug_frame */
2631 .sh_type
= SHT_PROGBITS
,
2632 .sh_offset
= sizeof(struct ElfImage
),
2634 [5] = { /* .symtab */
2635 .sh_type
= SHT_SYMTAB
,
2636 .sh_offset
= offsetof(struct ElfImage
, sym
),
2637 .sh_size
= sizeof(img
->sym
),
2639 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
2640 .sh_entsize
= sizeof(ElfW(Sym
)),
2642 [6] = { /* .strtab */
2643 .sh_type
= SHT_STRTAB
,
2644 .sh_offset
= offsetof(struct ElfImage
, str
),
2645 .sh_size
= sizeof(img
->str
),
2649 [1] = { /* code_gen_buffer */
2650 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
2655 .len
= sizeof(struct DebugInfo
) - 4,
2657 .ptr_size
= sizeof(void *),
2659 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
2661 .fn_name
= "code_gen_buffer"
2664 1, /* abbrev number (the cu) */
2665 0x11, 1, /* DW_TAG_compile_unit, has children */
2666 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2667 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2668 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2669 0, 0, /* end of abbrev */
2670 2, /* abbrev number (the fn) */
2671 0x2e, 0, /* DW_TAG_subprogram, no children */
2672 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2673 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2674 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2675 0, 0, /* end of abbrev */
2676 0 /* no more abbrev */
2678 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2679 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
2682 /* We only need a single jit entry; statically allocate it. */
2683 static struct jit_code_entry one_entry
;
2685 uintptr_t buf
= (uintptr_t)buf_ptr
;
2686 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
2687 DebugFrameHeader
*dfh
;
2689 img
= g_malloc(img_size
);
2690 *img
= img_template
;
2692 img
->phdr
.p_vaddr
= buf
;
2693 img
->phdr
.p_paddr
= buf
;
2694 img
->phdr
.p_memsz
= buf_size
;
2696 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
2697 img
->shdr
[1].sh_addr
= buf
;
2698 img
->shdr
[1].sh_size
= buf_size
;
2700 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
2701 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
2703 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
2704 img
->shdr
[4].sh_size
= debug_frame_size
;
2706 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
2707 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
2709 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
2710 img
->sym
[1].st_value
= buf
;
2711 img
->sym
[1].st_size
= buf_size
;
2713 img
->di
.cu_low_pc
= buf
;
2714 img
->di
.cu_high_pc
= buf
+ buf_size
;
2715 img
->di
.fn_low_pc
= buf
;
2716 img
->di
.fn_high_pc
= buf
+ buf_size
;
2718 dfh
= (DebugFrameHeader
*)(img
+ 1);
2719 memcpy(dfh
, debug_frame
, debug_frame_size
);
2720 dfh
->fde
.func_start
= buf
;
2721 dfh
->fde
.func_len
= buf_size
;
2724 /* Enable this block to be able to debug the ELF image file creation.
2725 One can use readelf, objdump, or other inspection utilities. */
2727 FILE *f
= fopen("/tmp/qemu.jit", "w+b");
2729 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
2730 /* Avoid stupid unused return value warning for fwrite. */
2737 one_entry
.symfile_addr
= img
;
2738 one_entry
.symfile_size
= img_size
;
2740 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
2741 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
2742 __jit_debug_descriptor
.first_entry
= &one_entry
;
2743 __jit_debug_register_code();
2746 /* No support for the feature. Provide the entry point expected by exec.c,
2747 and implement the internal function we declared earlier. */
2749 static void tcg_register_jit_int(void *buf
, size_t size
,
2750 const void *debug_frame
,
2751 size_t debug_frame_size
)
2755 void tcg_register_jit(void *buf
, size_t buf_size
)
2758 #endif /* ELF_HOST_MACHINE */