4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
10 * This code is licensed under GPL version 2 or later. See
11 * the COPYING file in the top-level directory.
15 #include "hw/timer/imx_gpt.h"
16 #include "hw/misc/imx_ccm.h"
17 #include "qemu/main-loop.h"
20 * Define to 1 for debug messages
25 static char const *imx_gpt_reg_name(uint32_t reg
)
53 # define DPRINTF(fmt, args...) \
54 do { printf("%s: " fmt , __func__, ##args); } while (0)
56 # define DPRINTF(fmt, args...) do {} while (0)
60 * Define to 1 for messages about attempts to
61 * access unimplemented registers or similar.
63 #define DEBUG_IMPLEMENTATION 1
64 #if DEBUG_IMPLEMENTATION
65 # define IPRINTF(fmt, args...) \
66 do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
68 # define IPRINTF(fmt, args...) do {} while (0)
71 static const VMStateDescription vmstate_imx_timer_gpt
= {
74 .minimum_version_id
= 3,
75 .fields
= (VMStateField
[]) {
76 VMSTATE_UINT32(cr
, IMXGPTState
),
77 VMSTATE_UINT32(pr
, IMXGPTState
),
78 VMSTATE_UINT32(sr
, IMXGPTState
),
79 VMSTATE_UINT32(ir
, IMXGPTState
),
80 VMSTATE_UINT32(ocr1
, IMXGPTState
),
81 VMSTATE_UINT32(ocr2
, IMXGPTState
),
82 VMSTATE_UINT32(ocr3
, IMXGPTState
),
83 VMSTATE_UINT32(icr1
, IMXGPTState
),
84 VMSTATE_UINT32(icr2
, IMXGPTState
),
85 VMSTATE_UINT32(cnt
, IMXGPTState
),
86 VMSTATE_UINT32(next_timeout
, IMXGPTState
),
87 VMSTATE_UINT32(next_int
, IMXGPTState
),
88 VMSTATE_UINT32(freq
, IMXGPTState
),
89 VMSTATE_PTIMER(timer
, IMXGPTState
),
94 static const IMXClk imx_gpt_clocks
[] = {
95 NOCLK
, /* 000 No clock source */
96 IPG
, /* 001 ipg_clk, 532MHz*/
97 IPG
, /* 010 ipg_clk_highfreq */
98 NOCLK
, /* 011 not defined */
99 CLK_32k
, /* 100 ipg_clk_32k */
100 NOCLK
, /* 101 not defined */
101 NOCLK
, /* 110 not defined */
102 NOCLK
, /* 111 not defined */
105 static void imx_gpt_set_freq(IMXGPTState
*s
)
107 uint32_t clksrc
= extract32(s
->cr
, GPT_CR_CLKSRC_SHIFT
, 3);
108 uint32_t freq
= imx_clock_frequency(s
->ccm
, imx_gpt_clocks
[clksrc
])
112 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc
, freq
);
115 ptimer_set_freq(s
->timer
, freq
);
119 static void imx_gpt_update_int(IMXGPTState
*s
)
121 if ((s
->sr
& s
->ir
) && (s
->cr
& GPT_CR_EN
)) {
122 qemu_irq_raise(s
->irq
);
124 qemu_irq_lower(s
->irq
);
128 static uint32_t imx_gpt_update_count(IMXGPTState
*s
)
130 s
->cnt
= s
->next_timeout
- (uint32_t)ptimer_get_count(s
->timer
);
135 static inline uint32_t imx_gpt_find_limit(uint32_t count
, uint32_t reg
,
138 if ((count
< reg
) && (timeout
> reg
)) {
145 static void imx_gpt_compute_next_timeout(IMXGPTState
*s
, bool event
)
147 uint32_t timeout
= GPT_TIMER_MAX
;
151 if (!(s
->cr
& GPT_CR_EN
)) {
152 /* if not enabled just return */
157 /* This is a timer event */
159 if ((s
->cr
& GPT_CR_FRR
) && (s
->next_timeout
!= GPT_TIMER_MAX
)) {
161 * if we are in free running mode and we have not reached
162 * the GPT_TIMER_MAX limit, then update the count
164 count
= imx_gpt_update_count(s
);
167 /* not a timer event, then just update the count */
169 count
= imx_gpt_update_count(s
);
172 /* now, find the next timeout related to count */
174 if (s
->ir
& GPT_IR_OF1IE
) {
175 timeout
= imx_gpt_find_limit(count
, s
->ocr1
, timeout
);
177 if (s
->ir
& GPT_IR_OF2IE
) {
178 timeout
= imx_gpt_find_limit(count
, s
->ocr2
, timeout
);
180 if (s
->ir
& GPT_IR_OF3IE
) {
181 timeout
= imx_gpt_find_limit(count
, s
->ocr3
, timeout
);
184 /* find the next set of interrupts to raise for next timer event */
187 if ((s
->ir
& GPT_IR_OF1IE
) && (timeout
== s
->ocr1
)) {
188 s
->next_int
|= GPT_SR_OF1
;
190 if ((s
->ir
& GPT_IR_OF2IE
) && (timeout
== s
->ocr2
)) {
191 s
->next_int
|= GPT_SR_OF2
;
193 if ((s
->ir
& GPT_IR_OF3IE
) && (timeout
== s
->ocr3
)) {
194 s
->next_int
|= GPT_SR_OF3
;
196 if ((s
->ir
& GPT_IR_ROVIE
) && (timeout
== GPT_TIMER_MAX
)) {
197 s
->next_int
|= GPT_SR_ROV
;
200 /* the new range to count down from */
201 limit
= timeout
- imx_gpt_update_count(s
);
205 * if we reach here, then QEMU is running too slow and we pass the
206 * timeout limit while computing it. Let's deliver the interrupt
207 * and compute a new limit.
209 s
->sr
|= s
->next_int
;
211 imx_gpt_compute_next_timeout(s
, event
);
213 imx_gpt_update_int(s
);
215 /* New timeout value */
216 s
->next_timeout
= timeout
;
218 /* reset the limit to the computed range */
219 ptimer_set_limit(s
->timer
, limit
, 1);
223 static uint64_t imx_gpt_read(void *opaque
, hwaddr offset
, unsigned size
)
225 IMXGPTState
*s
= IMX_GPT(opaque
);
226 uint32_t reg_value
= 0;
227 uint32_t reg
= offset
>> 2;
230 case 0: /* Control Register */
234 case 1: /* prescaler */
238 case 2: /* Status Register */
242 case 3: /* Interrupt Register */
246 case 4: /* Output Compare Register 1 */
250 case 5: /* Output Compare Register 2 */
254 case 6: /* Output Compare Register 3 */
258 case 7: /* input Capture Register 1 */
259 qemu_log_mask(LOG_UNIMP
, "icr1 feature is not implemented\n");
263 case 8: /* input Capture Register 2 */
264 qemu_log_mask(LOG_UNIMP
, "icr2 feature is not implemented\n");
269 imx_gpt_update_count(s
);
274 IPRINTF("Bad offset %x\n", reg
);
278 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg
), reg_value
);
283 static void imx_gpt_reset(DeviceState
*dev
)
285 IMXGPTState
*s
= IMX_GPT(dev
);
288 ptimer_stop(s
->timer
);
291 * Soft reset doesn't touch some bits; hard reset clears them
293 s
->cr
&= ~(GPT_CR_EN
|GPT_CR_ENMOD
|GPT_CR_STOPEN
|GPT_CR_DOZEN
|
294 GPT_CR_WAITEN
|GPT_CR_DBGEN
);
299 s
->ocr1
= GPT_TIMER_MAX
;
300 s
->ocr2
= GPT_TIMER_MAX
;
301 s
->ocr3
= GPT_TIMER_MAX
;
305 s
->next_timeout
= GPT_TIMER_MAX
;
308 /* compute new freq */
311 /* reset the limit to GPT_TIMER_MAX */
312 ptimer_set_limit(s
->timer
, GPT_TIMER_MAX
, 1);
314 /* if the timer is still enabled, restart it */
315 if (s
->freq
&& (s
->cr
& GPT_CR_EN
)) {
316 ptimer_run(s
->timer
, 1);
320 static void imx_gpt_write(void *opaque
, hwaddr offset
, uint64_t value
,
323 IMXGPTState
*s
= IMX_GPT(opaque
);
325 uint32_t reg
= offset
>> 2;
327 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg
),
333 s
->cr
= value
& ~0x7c14;
334 if (s
->cr
& GPT_CR_SWR
) { /* force reset */
335 /* handle the reset */
336 imx_gpt_reset(DEVICE(s
));
338 /* set our freq, as the source might have changed */
341 if ((oldreg
^ s
->cr
) & GPT_CR_EN
) {
342 if (s
->cr
& GPT_CR_EN
) {
343 if (s
->cr
& GPT_CR_ENMOD
) {
344 s
->next_timeout
= GPT_TIMER_MAX
;
345 ptimer_set_count(s
->timer
, GPT_TIMER_MAX
);
346 imx_gpt_compute_next_timeout(s
, false);
348 ptimer_run(s
->timer
, 1);
351 ptimer_stop(s
->timer
);
357 case 1: /* Prescaler */
358 s
->pr
= value
& 0xfff;
363 s
->sr
&= ~(value
& 0x3f);
364 imx_gpt_update_int(s
);
367 case 3: /* IR -- interrupt register */
368 s
->ir
= value
& 0x3f;
369 imx_gpt_update_int(s
);
371 imx_gpt_compute_next_timeout(s
, false);
375 case 4: /* OCR1 -- output compare register */
378 /* In non-freerun mode, reset count when this register is written */
379 if (!(s
->cr
& GPT_CR_FRR
)) {
380 s
->next_timeout
= GPT_TIMER_MAX
;
381 ptimer_set_limit(s
->timer
, GPT_TIMER_MAX
, 1);
384 /* compute the new timeout */
385 imx_gpt_compute_next_timeout(s
, false);
389 case 5: /* OCR2 -- output compare register */
392 /* compute the new timeout */
393 imx_gpt_compute_next_timeout(s
, false);
397 case 6: /* OCR3 -- output compare register */
400 /* compute the new timeout */
401 imx_gpt_compute_next_timeout(s
, false);
406 IPRINTF("Bad offset %x\n", reg
);
411 static void imx_gpt_timeout(void *opaque
)
413 IMXGPTState
*s
= IMX_GPT(opaque
);
417 s
->sr
|= s
->next_int
;
420 imx_gpt_compute_next_timeout(s
, true);
422 imx_gpt_update_int(s
);
424 if (s
->freq
&& (s
->cr
& GPT_CR_EN
)) {
425 ptimer_run(s
->timer
, 1);
429 static const MemoryRegionOps imx_gpt_ops
= {
430 .read
= imx_gpt_read
,
431 .write
= imx_gpt_write
,
432 .endianness
= DEVICE_NATIVE_ENDIAN
,
436 static void imx_gpt_realize(DeviceState
*dev
, Error
**errp
)
438 IMXGPTState
*s
= IMX_GPT(dev
);
439 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
442 sysbus_init_irq(sbd
, &s
->irq
);
443 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_gpt_ops
, s
, TYPE_IMX_GPT
,
445 sysbus_init_mmio(sbd
, &s
->iomem
);
447 bh
= qemu_bh_new(imx_gpt_timeout
, s
);
448 s
->timer
= ptimer_init(bh
);
451 static void imx_gpt_class_init(ObjectClass
*klass
, void *data
)
453 DeviceClass
*dc
= DEVICE_CLASS(klass
);
455 dc
->realize
= imx_gpt_realize
;
456 dc
->reset
= imx_gpt_reset
;
457 dc
->vmsd
= &vmstate_imx_timer_gpt
;
458 dc
->desc
= "i.MX general timer";
461 static const TypeInfo imx_gpt_info
= {
462 .name
= TYPE_IMX_GPT
,
463 .parent
= TYPE_SYS_BUS_DEVICE
,
464 .instance_size
= sizeof(IMXGPTState
),
465 .class_init
= imx_gpt_class_init
,
468 static void imx_gpt_register_types(void)
470 type_register_static(&imx_gpt_info
);
473 type_init(imx_gpt_register_types
)