2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/ssi/ssi.h"
14 #include "hw/arm/boot.h"
15 #include "qemu/timer.h"
16 #include "hw/i2c/i2c.h"
18 #include "hw/boards.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/sysemu.h"
22 #include "hw/arm/armv7m.h"
23 #include "hw/char/pl011.h"
24 #include "hw/input/gamepad.h"
25 #include "hw/watchdog/cmsdk-apb-watchdog.h"
26 #include "hw/misc/unimp.h"
37 #define BP_OLED_I2C 0x01
38 #define BP_OLED_SSI 0x02
39 #define BP_GAMEPAD 0x04
41 #define NUM_IRQ_LINES 64
43 typedef const struct {
53 } stellaris_board_info
;
55 /* General purpose timer module. */
57 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
58 #define STELLARIS_GPTM(obj) \
59 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
61 typedef struct gptm_state
{
62 SysBusDevice parent_obj
;
73 uint32_t match_prescale
[2];
76 struct gptm_state
*opaque
[2];
78 /* The timers have an alternate output used to trigger the ADC. */
83 static void gptm_update_irq(gptm_state
*s
)
86 level
= (s
->state
& s
->mask
) != 0;
87 qemu_set_irq(s
->irq
, level
);
90 static void gptm_stop(gptm_state
*s
, int n
)
92 timer_del(s
->timer
[n
]);
95 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
99 tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
103 if (s
->config
== 0) {
104 /* 32-bit CountDown. */
106 count
= s
->load
[0] | (s
->load
[1] << 16);
107 tick
+= (int64_t)count
* system_clock_scale
;
108 } else if (s
->config
== 1) {
109 /* 32-bit RTC. 1Hz tick. */
110 tick
+= NANOSECONDS_PER_SECOND
;
111 } else if (s
->mode
[n
] == 0xa) {
112 /* PWM mode. Not implemented. */
114 qemu_log_mask(LOG_UNIMP
,
115 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
120 timer_mod(s
->timer
[n
], tick
);
123 static void gptm_tick(void *opaque
)
125 gptm_state
**p
= (gptm_state
**)opaque
;
131 if (s
->config
== 0) {
133 if ((s
->control
& 0x20)) {
134 /* Output trigger. */
135 qemu_irq_pulse(s
->trigger
);
137 if (s
->mode
[0] & 1) {
142 gptm_reload(s
, 0, 0);
144 } else if (s
->config
== 1) {
148 match
= s
->match
[0] | (s
->match
[1] << 16);
154 gptm_reload(s
, 0, 0);
155 } else if (s
->mode
[n
] == 0xa) {
156 /* PWM mode. Not implemented. */
158 qemu_log_mask(LOG_UNIMP
,
159 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
165 static uint64_t gptm_read(void *opaque
, hwaddr offset
,
168 gptm_state
*s
= (gptm_state
*)opaque
;
173 case 0x04: /* TAMR */
175 case 0x08: /* TBMR */
184 return s
->state
& s
->mask
;
187 case 0x28: /* TAILR */
188 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
189 case 0x2c: /* TBILR */
191 case 0x30: /* TAMARCHR */
192 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
193 case 0x34: /* TBMATCHR */
195 case 0x38: /* TAPR */
196 return s
->prescale
[0];
197 case 0x3c: /* TBPR */
198 return s
->prescale
[1];
199 case 0x40: /* TAPMR */
200 return s
->match_prescale
[0];
201 case 0x44: /* TBPMR */
202 return s
->match_prescale
[1];
204 if (s
->config
== 1) {
207 qemu_log_mask(LOG_UNIMP
,
208 "GPTM: read of TAR but timer read not supported\n");
211 qemu_log_mask(LOG_UNIMP
,
212 "GPTM: read of TBR but timer read not supported\n");
215 qemu_log_mask(LOG_GUEST_ERROR
,
216 "GPTM: read at bad offset 0x02%" HWADDR_PRIx
"\n",
222 static void gptm_write(void *opaque
, hwaddr offset
,
223 uint64_t value
, unsigned size
)
225 gptm_state
*s
= (gptm_state
*)opaque
;
228 /* The timers should be disabled before changing the configuration.
229 We take advantage of this and defer everything until the timer
235 case 0x04: /* TAMR */
238 case 0x08: /* TBMR */
244 /* TODO: Implement pause. */
245 if ((oldval
^ value
) & 1) {
247 gptm_reload(s
, 0, 1);
252 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
254 gptm_reload(s
, 1, 1);
261 s
->mask
= value
& 0x77;
267 case 0x28: /* TAILR */
268 s
->load
[0] = value
& 0xffff;
270 s
->load
[1] = value
>> 16;
273 case 0x2c: /* TBILR */
274 s
->load
[1] = value
& 0xffff;
276 case 0x30: /* TAMARCHR */
277 s
->match
[0] = value
& 0xffff;
279 s
->match
[1] = value
>> 16;
282 case 0x34: /* TBMATCHR */
283 s
->match
[1] = value
>> 16;
285 case 0x38: /* TAPR */
286 s
->prescale
[0] = value
;
288 case 0x3c: /* TBPR */
289 s
->prescale
[1] = value
;
291 case 0x40: /* TAPMR */
292 s
->match_prescale
[0] = value
;
294 case 0x44: /* TBPMR */
295 s
->match_prescale
[0] = value
;
298 qemu_log_mask(LOG_GUEST_ERROR
,
299 "GPTM: write at bad offset 0x02%" HWADDR_PRIx
"\n",
305 static const MemoryRegionOps gptm_ops
= {
308 .endianness
= DEVICE_NATIVE_ENDIAN
,
311 static const VMStateDescription vmstate_stellaris_gptm
= {
312 .name
= "stellaris_gptm",
314 .minimum_version_id
= 1,
315 .fields
= (VMStateField
[]) {
316 VMSTATE_UINT32(config
, gptm_state
),
317 VMSTATE_UINT32_ARRAY(mode
, gptm_state
, 2),
318 VMSTATE_UINT32(control
, gptm_state
),
319 VMSTATE_UINT32(state
, gptm_state
),
320 VMSTATE_UINT32(mask
, gptm_state
),
322 VMSTATE_UINT32_ARRAY(load
, gptm_state
, 2),
323 VMSTATE_UINT32_ARRAY(match
, gptm_state
, 2),
324 VMSTATE_UINT32_ARRAY(prescale
, gptm_state
, 2),
325 VMSTATE_UINT32_ARRAY(match_prescale
, gptm_state
, 2),
326 VMSTATE_UINT32(rtc
, gptm_state
),
327 VMSTATE_INT64_ARRAY(tick
, gptm_state
, 2),
328 VMSTATE_TIMER_PTR_ARRAY(timer
, gptm_state
, 2),
329 VMSTATE_END_OF_LIST()
333 static void stellaris_gptm_init(Object
*obj
)
335 DeviceState
*dev
= DEVICE(obj
);
336 gptm_state
*s
= STELLARIS_GPTM(obj
);
337 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
339 sysbus_init_irq(sbd
, &s
->irq
);
340 qdev_init_gpio_out(dev
, &s
->trigger
, 1);
342 memory_region_init_io(&s
->iomem
, obj
, &gptm_ops
, s
,
344 sysbus_init_mmio(sbd
, &s
->iomem
);
346 s
->opaque
[0] = s
->opaque
[1] = s
;
347 s
->timer
[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[0]);
348 s
->timer
[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, gptm_tick
, &s
->opaque
[1]);
352 /* System controller. */
371 stellaris_board_info
*board
;
374 static void ssys_update(ssys_state
*s
)
376 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
379 static uint32_t pllcfg_sandstorm
[16] = {
381 0x1ae0, /* 1.8432 Mhz */
383 0xd573, /* 2.4576 Mhz */
384 0x37a6, /* 3.57954 Mhz */
385 0x1ae2, /* 3.6864 Mhz */
387 0x98bc, /* 4.906 Mhz */
388 0x935b, /* 4.9152 Mhz */
390 0x4dee, /* 5.12 Mhz */
392 0x75db, /* 6.144 Mhz */
393 0x1ae6, /* 7.3728 Mhz */
395 0x585b /* 8.192 Mhz */
398 static uint32_t pllcfg_fury
[16] = {
400 0x1b20, /* 1.8432 Mhz */
402 0xf42b, /* 2.4576 Mhz */
403 0x37e3, /* 3.57954 Mhz */
404 0x1b21, /* 3.6864 Mhz */
406 0x98ee, /* 4.906 Mhz */
407 0xd5b4, /* 4.9152 Mhz */
409 0x4e27, /* 5.12 Mhz */
411 0xec1c, /* 6.144 Mhz */
412 0x1b23, /* 7.3728 Mhz */
414 0xb11c /* 8.192 Mhz */
417 #define DID0_VER_MASK 0x70000000
418 #define DID0_VER_0 0x00000000
419 #define DID0_VER_1 0x10000000
421 #define DID0_CLASS_MASK 0x00FF0000
422 #define DID0_CLASS_SANDSTORM 0x00000000
423 #define DID0_CLASS_FURY 0x00010000
425 static int ssys_board_class(const ssys_state
*s
)
427 uint32_t did0
= s
->board
->did0
;
428 switch (did0
& DID0_VER_MASK
) {
430 return DID0_CLASS_SANDSTORM
;
432 switch (did0
& DID0_CLASS_MASK
) {
433 case DID0_CLASS_SANDSTORM
:
434 case DID0_CLASS_FURY
:
435 return did0
& DID0_CLASS_MASK
;
437 /* for unknown classes, fall through */
439 /* This can only happen if the hardwired constant did0 value
440 * in this board's stellaris_board_info struct is wrong.
442 g_assert_not_reached();
446 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
449 ssys_state
*s
= (ssys_state
*)opaque
;
452 case 0x000: /* DID0 */
453 return s
->board
->did0
;
454 case 0x004: /* DID1 */
455 return s
->board
->did1
;
456 case 0x008: /* DC0 */
457 return s
->board
->dc0
;
458 case 0x010: /* DC1 */
459 return s
->board
->dc1
;
460 case 0x014: /* DC2 */
461 return s
->board
->dc2
;
462 case 0x018: /* DC3 */
463 return s
->board
->dc3
;
464 case 0x01c: /* DC4 */
465 return s
->board
->dc4
;
466 case 0x030: /* PBORCTL */
468 case 0x034: /* LDOPCTL */
470 case 0x040: /* SRCR0 */
472 case 0x044: /* SRCR1 */
474 case 0x048: /* SRCR2 */
476 case 0x050: /* RIS */
477 return s
->int_status
;
478 case 0x054: /* IMC */
480 case 0x058: /* MISC */
481 return s
->int_status
& s
->int_mask
;
482 case 0x05c: /* RESC */
484 case 0x060: /* RCC */
486 case 0x064: /* PLLCFG */
489 xtal
= (s
->rcc
>> 6) & 0xf;
490 switch (ssys_board_class(s
)) {
491 case DID0_CLASS_FURY
:
492 return pllcfg_fury
[xtal
];
493 case DID0_CLASS_SANDSTORM
:
494 return pllcfg_sandstorm
[xtal
];
496 g_assert_not_reached();
499 case 0x070: /* RCC2 */
501 case 0x100: /* RCGC0 */
503 case 0x104: /* RCGC1 */
505 case 0x108: /* RCGC2 */
507 case 0x110: /* SCGC0 */
509 case 0x114: /* SCGC1 */
511 case 0x118: /* SCGC2 */
513 case 0x120: /* DCGC0 */
515 case 0x124: /* DCGC1 */
517 case 0x128: /* DCGC2 */
519 case 0x150: /* CLKVCLR */
521 case 0x160: /* LDOARST */
523 case 0x1e0: /* USER0 */
525 case 0x1e4: /* USER1 */
528 qemu_log_mask(LOG_GUEST_ERROR
,
529 "SSYS: read at bad offset 0x%x\n", (int)offset
);
534 static bool ssys_use_rcc2(ssys_state
*s
)
536 return (s
->rcc2
>> 31) & 0x1;
540 * Caculate the sys. clock period in ms.
542 static void ssys_calculate_system_clock(ssys_state
*s
)
544 if (ssys_use_rcc2(s
)) {
545 system_clock_scale
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
547 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
551 static void ssys_write(void *opaque
, hwaddr offset
,
552 uint64_t value
, unsigned size
)
554 ssys_state
*s
= (ssys_state
*)opaque
;
557 case 0x030: /* PBORCTL */
558 s
->pborctl
= value
& 0xffff;
560 case 0x034: /* LDOPCTL */
561 s
->ldopctl
= value
& 0x1f;
563 case 0x040: /* SRCR0 */
564 case 0x044: /* SRCR1 */
565 case 0x048: /* SRCR2 */
566 qemu_log_mask(LOG_UNIMP
, "Peripheral reset not implemented\n");
568 case 0x054: /* IMC */
569 s
->int_mask
= value
& 0x7f;
571 case 0x058: /* MISC */
572 s
->int_status
&= ~value
;
574 case 0x05c: /* RESC */
575 s
->resc
= value
& 0x3f;
577 case 0x060: /* RCC */
578 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
580 s
->int_status
|= (1 << 6);
583 ssys_calculate_system_clock(s
);
585 case 0x070: /* RCC2 */
586 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
590 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
592 s
->int_status
|= (1 << 6);
595 ssys_calculate_system_clock(s
);
597 case 0x100: /* RCGC0 */
600 case 0x104: /* RCGC1 */
603 case 0x108: /* RCGC2 */
606 case 0x110: /* SCGC0 */
609 case 0x114: /* SCGC1 */
612 case 0x118: /* SCGC2 */
615 case 0x120: /* DCGC0 */
618 case 0x124: /* DCGC1 */
621 case 0x128: /* DCGC2 */
624 case 0x150: /* CLKVCLR */
627 case 0x160: /* LDOARST */
631 qemu_log_mask(LOG_GUEST_ERROR
,
632 "SSYS: write at bad offset 0x%x\n", (int)offset
);
637 static const MemoryRegionOps ssys_ops
= {
640 .endianness
= DEVICE_NATIVE_ENDIAN
,
643 static void ssys_reset(void *opaque
)
645 ssys_state
*s
= (ssys_state
*)opaque
;
650 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
653 s
->rcc2
= 0x07802810;
658 ssys_calculate_system_clock(s
);
661 static int stellaris_sys_post_load(void *opaque
, int version_id
)
663 ssys_state
*s
= opaque
;
665 ssys_calculate_system_clock(s
);
670 static const VMStateDescription vmstate_stellaris_sys
= {
671 .name
= "stellaris_sys",
673 .minimum_version_id
= 1,
674 .post_load
= stellaris_sys_post_load
,
675 .fields
= (VMStateField
[]) {
676 VMSTATE_UINT32(pborctl
, ssys_state
),
677 VMSTATE_UINT32(ldopctl
, ssys_state
),
678 VMSTATE_UINT32(int_mask
, ssys_state
),
679 VMSTATE_UINT32(int_status
, ssys_state
),
680 VMSTATE_UINT32(resc
, ssys_state
),
681 VMSTATE_UINT32(rcc
, ssys_state
),
682 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
683 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
684 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
685 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
686 VMSTATE_UINT32(clkvclr
, ssys_state
),
687 VMSTATE_UINT32(ldoarst
, ssys_state
),
688 VMSTATE_END_OF_LIST()
692 static int stellaris_sys_init(uint32_t base
, qemu_irq irq
,
693 stellaris_board_info
* board
,
698 s
= g_new0(ssys_state
, 1);
701 /* Most devices come preprogrammed with a MAC address in the user data. */
702 s
->user0
= macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16);
703 s
->user1
= macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16);
705 memory_region_init_io(&s
->iomem
, NULL
, &ssys_ops
, s
, "ssys", 0x00001000);
706 memory_region_add_subregion(get_system_memory(), base
, &s
->iomem
);
708 vmstate_register(NULL
, -1, &vmstate_stellaris_sys
, s
);
713 /* I2C controller. */
715 #define TYPE_STELLARIS_I2C "stellaris-i2c"
716 #define STELLARIS_I2C(obj) \
717 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
720 SysBusDevice parent_obj
;
732 } stellaris_i2c_state
;
734 #define STELLARIS_I2C_MCS_BUSY 0x01
735 #define STELLARIS_I2C_MCS_ERROR 0x02
736 #define STELLARIS_I2C_MCS_ADRACK 0x04
737 #define STELLARIS_I2C_MCS_DATACK 0x08
738 #define STELLARIS_I2C_MCS_ARBLST 0x10
739 #define STELLARIS_I2C_MCS_IDLE 0x20
740 #define STELLARIS_I2C_MCS_BUSBSY 0x40
742 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
745 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
751 /* We don't emulate timing, so the controller is never busy. */
752 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
755 case 0x0c: /* MTPR */
757 case 0x10: /* MIMR */
759 case 0x14: /* MRIS */
761 case 0x18: /* MMIS */
762 return s
->mris
& s
->mimr
;
766 qemu_log_mask(LOG_GUEST_ERROR
,
767 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset
);
772 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
776 level
= (s
->mris
& s
->mimr
) != 0;
777 qemu_set_irq(s
->irq
, level
);
780 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
781 uint64_t value
, unsigned size
)
783 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
787 s
->msa
= value
& 0xff;
790 if ((s
->mcr
& 0x10) == 0) {
791 /* Disabled. Do nothing. */
794 /* Grab the bus if this is starting a transfer. */
795 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
796 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
797 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
799 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
800 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
803 /* If we don't have the bus then indicate an error. */
804 if (!i2c_bus_busy(s
->bus
)
805 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
806 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
809 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
811 /* Transfer a byte. */
812 /* TODO: Handle errors. */
815 s
->mdr
= i2c_recv(s
->bus
);
818 i2c_send(s
->bus
, s
->mdr
);
820 /* Raise an interrupt. */
824 /* Finish transfer. */
825 i2c_end_transfer(s
->bus
);
826 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
830 s
->mdr
= value
& 0xff;
832 case 0x0c: /* MTPR */
833 s
->mtpr
= value
& 0xff;
835 case 0x10: /* MIMR */
838 case 0x1c: /* MICR */
843 qemu_log_mask(LOG_UNIMP
,
844 "stellaris_i2c: Loopback not implemented\n");
847 qemu_log_mask(LOG_UNIMP
,
848 "stellaris_i2c: Slave mode not implemented\n");
850 s
->mcr
= value
& 0x31;
853 qemu_log_mask(LOG_GUEST_ERROR
,
854 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset
);
856 stellaris_i2c_update(s
);
859 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
861 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
862 i2c_end_transfer(s
->bus
);
871 stellaris_i2c_update(s
);
874 static const MemoryRegionOps stellaris_i2c_ops
= {
875 .read
= stellaris_i2c_read
,
876 .write
= stellaris_i2c_write
,
877 .endianness
= DEVICE_NATIVE_ENDIAN
,
880 static const VMStateDescription vmstate_stellaris_i2c
= {
881 .name
= "stellaris_i2c",
883 .minimum_version_id
= 1,
884 .fields
= (VMStateField
[]) {
885 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
886 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
887 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
888 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
889 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
890 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
891 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
892 VMSTATE_END_OF_LIST()
896 static void stellaris_i2c_init(Object
*obj
)
898 DeviceState
*dev
= DEVICE(obj
);
899 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
900 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
903 sysbus_init_irq(sbd
, &s
->irq
);
904 bus
= i2c_init_bus(dev
, "i2c");
907 memory_region_init_io(&s
->iomem
, obj
, &stellaris_i2c_ops
, s
,
909 sysbus_init_mmio(sbd
, &s
->iomem
);
910 /* ??? For now we only implement the master interface. */
911 stellaris_i2c_reset(s
);
914 /* Analogue to Digital Converter. This is only partially implemented,
915 enough for applications that use a combined ADC and timer tick. */
917 #define STELLARIS_ADC_EM_CONTROLLER 0
918 #define STELLARIS_ADC_EM_COMP 1
919 #define STELLARIS_ADC_EM_EXTERNAL 4
920 #define STELLARIS_ADC_EM_TIMER 5
921 #define STELLARIS_ADC_EM_PWM0 6
922 #define STELLARIS_ADC_EM_PWM1 7
923 #define STELLARIS_ADC_EM_PWM2 8
925 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
926 #define STELLARIS_ADC_FIFO_FULL 0x1000
928 #define TYPE_STELLARIS_ADC "stellaris-adc"
929 #define STELLARIS_ADC(obj) \
930 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
932 typedef struct StellarisADCState
{
933 SysBusDevice parent_obj
;
952 } stellaris_adc_state
;
954 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
958 tail
= s
->fifo
[n
].state
& 0xf;
959 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
962 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
963 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
964 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
965 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
967 return s
->fifo
[n
].data
[tail
];
970 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
975 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
976 FIFO fir each sequencer. */
977 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
978 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
982 s
->fifo
[n
].data
[head
] = value
;
983 head
= (head
+ 1) & 0xf;
984 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
985 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
986 if ((s
->fifo
[n
].state
& 0xf) == head
)
987 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
990 static void stellaris_adc_update(stellaris_adc_state
*s
)
995 for (n
= 0; n
< 4; n
++) {
996 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
997 qemu_set_irq(s
->irq
[n
], level
);
1001 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
1003 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1006 for (n
= 0; n
< 4; n
++) {
1007 if ((s
->actss
& (1 << n
)) == 0) {
1011 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
1015 /* Some applications use the ADC as a random number source, so introduce
1016 some variation into the signal. */
1017 s
->noise
= s
->noise
* 314159 + 1;
1018 /* ??? actual inputs not implemented. Return an arbitrary value. */
1019 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
1021 stellaris_adc_update(s
);
1025 static void stellaris_adc_reset(stellaris_adc_state
*s
)
1029 for (n
= 0; n
< 4; n
++) {
1032 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
1036 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
1039 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1041 /* TODO: Implement this. */
1042 if (offset
>= 0x40 && offset
< 0xc0) {
1044 n
= (offset
- 0x40) >> 5;
1045 switch (offset
& 0x1f) {
1046 case 0x00: /* SSMUX */
1048 case 0x04: /* SSCTL */
1050 case 0x08: /* SSFIFO */
1051 return stellaris_adc_fifo_read(s
, n
);
1052 case 0x0c: /* SSFSTAT */
1053 return s
->fifo
[n
].state
;
1059 case 0x00: /* ACTSS */
1061 case 0x04: /* RIS */
1065 case 0x0c: /* ISC */
1066 return s
->ris
& s
->im
;
1067 case 0x10: /* OSTAT */
1069 case 0x14: /* EMUX */
1071 case 0x18: /* USTAT */
1073 case 0x20: /* SSPRI */
1075 case 0x30: /* SAC */
1078 qemu_log_mask(LOG_GUEST_ERROR
,
1079 "stellaris_adc: read at bad offset 0x%x\n", (int)offset
);
1084 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
1085 uint64_t value
, unsigned size
)
1087 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1089 /* TODO: Implement this. */
1090 if (offset
>= 0x40 && offset
< 0xc0) {
1092 n
= (offset
- 0x40) >> 5;
1093 switch (offset
& 0x1f) {
1094 case 0x00: /* SSMUX */
1095 s
->ssmux
[n
] = value
& 0x33333333;
1097 case 0x04: /* SSCTL */
1099 qemu_log_mask(LOG_UNIMP
,
1100 "ADC: Unimplemented sequence %" PRIx64
"\n",
1103 s
->ssctl
[n
] = value
;
1110 case 0x00: /* ACTSS */
1111 s
->actss
= value
& 0xf;
1116 case 0x0c: /* ISC */
1119 case 0x10: /* OSTAT */
1122 case 0x14: /* EMUX */
1125 case 0x18: /* USTAT */
1128 case 0x20: /* SSPRI */
1131 case 0x28: /* PSSI */
1132 qemu_log_mask(LOG_UNIMP
, "ADC: sample initiate unimplemented\n");
1134 case 0x30: /* SAC */
1138 qemu_log_mask(LOG_GUEST_ERROR
,
1139 "stellaris_adc: write at bad offset 0x%x\n", (int)offset
);
1141 stellaris_adc_update(s
);
1144 static const MemoryRegionOps stellaris_adc_ops
= {
1145 .read
= stellaris_adc_read
,
1146 .write
= stellaris_adc_write
,
1147 .endianness
= DEVICE_NATIVE_ENDIAN
,
1150 static const VMStateDescription vmstate_stellaris_adc
= {
1151 .name
= "stellaris_adc",
1153 .minimum_version_id
= 1,
1154 .fields
= (VMStateField
[]) {
1155 VMSTATE_UINT32(actss
, stellaris_adc_state
),
1156 VMSTATE_UINT32(ris
, stellaris_adc_state
),
1157 VMSTATE_UINT32(im
, stellaris_adc_state
),
1158 VMSTATE_UINT32(emux
, stellaris_adc_state
),
1159 VMSTATE_UINT32(ostat
, stellaris_adc_state
),
1160 VMSTATE_UINT32(ustat
, stellaris_adc_state
),
1161 VMSTATE_UINT32(sspri
, stellaris_adc_state
),
1162 VMSTATE_UINT32(sac
, stellaris_adc_state
),
1163 VMSTATE_UINT32(fifo
[0].state
, stellaris_adc_state
),
1164 VMSTATE_UINT32_ARRAY(fifo
[0].data
, stellaris_adc_state
, 16),
1165 VMSTATE_UINT32(ssmux
[0], stellaris_adc_state
),
1166 VMSTATE_UINT32(ssctl
[0], stellaris_adc_state
),
1167 VMSTATE_UINT32(fifo
[1].state
, stellaris_adc_state
),
1168 VMSTATE_UINT32_ARRAY(fifo
[1].data
, stellaris_adc_state
, 16),
1169 VMSTATE_UINT32(ssmux
[1], stellaris_adc_state
),
1170 VMSTATE_UINT32(ssctl
[1], stellaris_adc_state
),
1171 VMSTATE_UINT32(fifo
[2].state
, stellaris_adc_state
),
1172 VMSTATE_UINT32_ARRAY(fifo
[2].data
, stellaris_adc_state
, 16),
1173 VMSTATE_UINT32(ssmux
[2], stellaris_adc_state
),
1174 VMSTATE_UINT32(ssctl
[2], stellaris_adc_state
),
1175 VMSTATE_UINT32(fifo
[3].state
, stellaris_adc_state
),
1176 VMSTATE_UINT32_ARRAY(fifo
[3].data
, stellaris_adc_state
, 16),
1177 VMSTATE_UINT32(ssmux
[3], stellaris_adc_state
),
1178 VMSTATE_UINT32(ssctl
[3], stellaris_adc_state
),
1179 VMSTATE_UINT32(noise
, stellaris_adc_state
),
1180 VMSTATE_END_OF_LIST()
1184 static void stellaris_adc_init(Object
*obj
)
1186 DeviceState
*dev
= DEVICE(obj
);
1187 stellaris_adc_state
*s
= STELLARIS_ADC(obj
);
1188 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1191 for (n
= 0; n
< 4; n
++) {
1192 sysbus_init_irq(sbd
, &s
->irq
[n
]);
1195 memory_region_init_io(&s
->iomem
, obj
, &stellaris_adc_ops
, s
,
1197 sysbus_init_mmio(sbd
, &s
->iomem
);
1198 stellaris_adc_reset(s
);
1199 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
1203 void do_sys_reset(void *opaque
, int n
, int level
)
1206 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
1211 static stellaris_board_info stellaris_boards
[] = {
1215 0x001f001f, /* dc0 */
1225 0x00ff007f, /* dc0 */
1230 BP_OLED_SSI
| BP_GAMEPAD
1234 static void stellaris_init(MachineState
*ms
, stellaris_board_info
*board
)
1236 static const int uart_irq
[] = {5, 6, 33, 34};
1237 static const int timer_irq
[] = {19, 21, 23, 35};
1238 static const uint32_t gpio_addr
[7] =
1239 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1240 0x40024000, 0x40025000, 0x40026000};
1241 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1243 /* Memory map of SoC devices, from
1244 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1245 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1248 * 40002000 i2c (unimplemented)
1258 * 40021000 i2c (unimplemented)
1262 * 40028000 PWM (unimplemented)
1263 * 4002c000 QEI (unimplemented)
1264 * 4002d000 QEI (unimplemented)
1270 * 4003c000 analogue comparator (unimplemented)
1272 * 400fc000 hibernation module (unimplemented)
1273 * 400fd000 flash memory control (unimplemented)
1274 * 400fe000 system control
1277 DeviceState
*gpio_dev
[7], *nvic
;
1278 qemu_irq gpio_in
[7][8];
1279 qemu_irq gpio_out
[7][8];
1288 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1289 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1290 MemoryRegion
*system_memory
= get_system_memory();
1292 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1293 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1295 /* Flash programming is done via the SCU, so pretend it is ROM. */
1296 memory_region_init_ram(flash
, NULL
, "stellaris.flash", flash_size
,
1298 memory_region_set_readonly(flash
, true);
1299 memory_region_add_subregion(system_memory
, 0, flash
);
1301 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1303 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1305 nvic
= qdev_create(NULL
, TYPE_ARMV7M
);
1306 qdev_prop_set_uint32(nvic
, "num-irq", NUM_IRQ_LINES
);
1307 qdev_prop_set_string(nvic
, "cpu-type", ms
->cpu_type
);
1308 qdev_prop_set_bit(nvic
, "enable-bitband", true);
1309 object_property_set_link(OBJECT(nvic
), OBJECT(get_system_memory()),
1310 "memory", &error_abort
);
1311 /* This will exit with an error if the user passed us a bad cpu_type */
1312 qdev_init_nofail(nvic
);
1314 qdev_connect_gpio_out_named(nvic
, "SYSRESETREQ", 0,
1315 qemu_allocate_irq(&do_sys_reset
, NULL
, 0));
1317 if (board
->dc1
& (1 << 16)) {
1318 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1319 qdev_get_gpio_in(nvic
, 14),
1320 qdev_get_gpio_in(nvic
, 15),
1321 qdev_get_gpio_in(nvic
, 16),
1322 qdev_get_gpio_in(nvic
, 17),
1324 adc
= qdev_get_gpio_in(dev
, 0);
1328 for (i
= 0; i
< 4; i
++) {
1329 if (board
->dc2
& (0x10000 << i
)) {
1330 dev
= sysbus_create_simple(TYPE_STELLARIS_GPTM
,
1331 0x40030000 + i
* 0x1000,
1332 qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1333 /* TODO: This is incorrect, but we get away with it because
1334 the ADC output is only ever pulsed. */
1335 qdev_connect_gpio_out(dev
, 0, adc
);
1339 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic
, 28),
1340 board
, nd_table
[0].macaddr
.a
);
1343 if (board
->dc1
& (1 << 3)) { /* watchdog present */
1344 dev
= qdev_create(NULL
, TYPE_LUMINARY_WATCHDOG
);
1346 /* system_clock_scale is valid now */
1347 uint32_t mainclk
= NANOSECONDS_PER_SECOND
/ system_clock_scale
;
1348 qdev_prop_set_uint32(dev
, "wdogclk-frq", mainclk
);
1350 qdev_init_nofail(dev
);
1351 sysbus_mmio_map(SYS_BUS_DEVICE(dev
),
1354 sysbus_connect_irq(SYS_BUS_DEVICE(dev
),
1356 qdev_get_gpio_in(nvic
, 18));
1360 for (i
= 0; i
< 7; i
++) {
1361 if (board
->dc4
& (1 << i
)) {
1362 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1363 qdev_get_gpio_in(nvic
,
1365 for (j
= 0; j
< 8; j
++) {
1366 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1367 gpio_out
[i
][j
] = NULL
;
1372 if (board
->dc2
& (1 << 12)) {
1373 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1374 qdev_get_gpio_in(nvic
, 8));
1375 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1376 if (board
->peripherals
& BP_OLED_I2C
) {
1377 i2c_create_slave(i2c
, "ssd0303", 0x3d);
1381 for (i
= 0; i
< 4; i
++) {
1382 if (board
->dc2
& (1 << i
)) {
1383 pl011_luminary_create(0x4000c000 + i
* 0x1000,
1384 qdev_get_gpio_in(nvic
, uart_irq
[i
]),
1388 if (board
->dc2
& (1 << 4)) {
1389 dev
= sysbus_create_simple("pl022", 0x40008000,
1390 qdev_get_gpio_in(nvic
, 7));
1391 if (board
->peripherals
& BP_OLED_SSI
) {
1394 DeviceState
*ssddev
;
1396 /* Some boards have both an OLED controller and SD card connected to
1397 * the same SSI port, with the SD card chip select connected to a
1398 * GPIO pin. Technically the OLED chip select is connected to the
1399 * SSI Fss pin. We do not bother emulating that as both devices
1400 * should never be selected simultaneously, and our OLED controller
1401 * ignores stray 0xff commands that occur when deselecting the SD
1404 bus
= qdev_get_child_bus(dev
, "ssi");
1406 sddev
= ssi_create_slave(bus
, "ssi-sd");
1407 ssddev
= ssi_create_slave(bus
, "ssd0323");
1408 gpio_out
[GPIO_D
][0] = qemu_irq_split(
1409 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0),
1410 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1411 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1413 /* Make sure the select pin is high. */
1414 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1417 if (board
->dc4
& (1 << 28)) {
1420 qemu_check_nic_model(&nd_table
[0], "stellaris");
1422 enet
= qdev_create(NULL
, "stellaris_enet");
1423 qdev_set_nic_properties(enet
, &nd_table
[0]);
1424 qdev_init_nofail(enet
);
1425 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1426 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1428 if (board
->peripherals
& BP_GAMEPAD
) {
1429 qemu_irq gpad_irq
[5];
1430 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1432 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1433 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1434 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1435 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1436 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1438 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1440 for (i
= 0; i
< 7; i
++) {
1441 if (board
->dc4
& (1 << i
)) {
1442 for (j
= 0; j
< 8; j
++) {
1443 if (gpio_out
[i
][j
]) {
1444 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1450 /* Add dummy regions for the devices we don't implement yet,
1451 * so guest accesses don't cause unlogged crashes.
1453 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1454 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1455 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1456 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1457 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1458 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1459 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1460 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1462 armv7m_load_kernel(ARM_CPU(first_cpu
), ms
->kernel_filename
, flash_size
);
1465 /* FIXME: Figure out how to generate these from stellaris_boards. */
1466 static void lm3s811evb_init(MachineState
*machine
)
1468 stellaris_init(machine
, &stellaris_boards
[0]);
1471 static void lm3s6965evb_init(MachineState
*machine
)
1473 stellaris_init(machine
, &stellaris_boards
[1]);
1476 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1478 MachineClass
*mc
= MACHINE_CLASS(oc
);
1480 mc
->desc
= "Stellaris LM3S811EVB";
1481 mc
->init
= lm3s811evb_init
;
1482 mc
->ignore_memory_transaction_failures
= true;
1483 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1486 static const TypeInfo lm3s811evb_type
= {
1487 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1488 .parent
= TYPE_MACHINE
,
1489 .class_init
= lm3s811evb_class_init
,
1492 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1494 MachineClass
*mc
= MACHINE_CLASS(oc
);
1496 mc
->desc
= "Stellaris LM3S6965EVB";
1497 mc
->init
= lm3s6965evb_init
;
1498 mc
->ignore_memory_transaction_failures
= true;
1499 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1502 static const TypeInfo lm3s6965evb_type
= {
1503 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1504 .parent
= TYPE_MACHINE
,
1505 .class_init
= lm3s6965evb_class_init
,
1508 static void stellaris_machine_init(void)
1510 type_register_static(&lm3s811evb_type
);
1511 type_register_static(&lm3s6965evb_type
);
1514 type_init(stellaris_machine_init
)
1516 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1518 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1520 dc
->vmsd
= &vmstate_stellaris_i2c
;
1523 static const TypeInfo stellaris_i2c_info
= {
1524 .name
= TYPE_STELLARIS_I2C
,
1525 .parent
= TYPE_SYS_BUS_DEVICE
,
1526 .instance_size
= sizeof(stellaris_i2c_state
),
1527 .instance_init
= stellaris_i2c_init
,
1528 .class_init
= stellaris_i2c_class_init
,
1531 static void stellaris_gptm_class_init(ObjectClass
*klass
, void *data
)
1533 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1535 dc
->vmsd
= &vmstate_stellaris_gptm
;
1538 static const TypeInfo stellaris_gptm_info
= {
1539 .name
= TYPE_STELLARIS_GPTM
,
1540 .parent
= TYPE_SYS_BUS_DEVICE
,
1541 .instance_size
= sizeof(gptm_state
),
1542 .instance_init
= stellaris_gptm_init
,
1543 .class_init
= stellaris_gptm_class_init
,
1546 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1548 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1550 dc
->vmsd
= &vmstate_stellaris_adc
;
1553 static const TypeInfo stellaris_adc_info
= {
1554 .name
= TYPE_STELLARIS_ADC
,
1555 .parent
= TYPE_SYS_BUS_DEVICE
,
1556 .instance_size
= sizeof(stellaris_adc_state
),
1557 .instance_init
= stellaris_adc_init
,
1558 .class_init
= stellaris_adc_class_init
,
1561 static void stellaris_register_types(void)
1563 type_register_static(&stellaris_i2c_info
);
1564 type_register_static(&stellaris_gptm_info
);
1565 type_register_static(&stellaris_adc_info
);
1568 type_init(stellaris_register_types
)