hw/arm/fsl-imx31.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX31 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "hw/arm/fsl-imx31.h"
  26 #include "sysemu/sysemu.h"
  27 #include "exec/address-spaces.h"
  28 #include "hw/qdev-properties.h"
  29 #include "chardev/char.h"
  30
  31 static void fsl_imx31_init(Object *obj)
  32 {
  33     FslIMX31State *s = FSL_IMX31(obj);
  34     int i;
  35
  36     object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
  37
  38     object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
  39
  40     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM);
  41
  42     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  43         object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
  44     }
  45
  46     object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT);
  47
  48     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
  49         object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
  50     }
  51
  52     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
  53         object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
  54     }
  55
  56     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
  57         object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
  58     }
  59
  60     object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
  61 }
  62
  63 static void fsl_imx31_realize(DeviceState *dev, Error **errp)
  64 {
  65     FslIMX31State *s = FSL_IMX31(dev);
  66     uint16_t i;
  67     Error *err = NULL;
  68
  69     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
  70         return;
  71     }
  72
  73     if (!sysbus_realize(SYS_BUS_DEVICE(&s->avic), errp)) {
  74         return;
  75     }
  76     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
  77     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  78                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  79     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  80                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  81
  82     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
  83         return;
  84     }
  85     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
  86
  87     /* Initialize all UARTS */
  88     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  89         static const struct {
  90             hwaddr addr;
  91             unsigned int irq;
  92         } serial_table[FSL_IMX31_NUM_UARTS] = {
  93             { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
  94             { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
  95         };
  96
  97         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
  98
  99         if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
 100             return;
 101         }
 102
 103         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 104         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 105                            qdev_get_gpio_in(DEVICE(&s->avic),
 106                                             serial_table[i].irq));
 107     }
 108
 109     s->gpt.ccm = IMX_CCM(&s->ccm);
 110
 111     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
 112         return;
 113     }
 114
 115     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
 116     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 117                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
 118
 119     /* Initialize all EPIT timers */
 120     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
 121         static const struct {
 122             hwaddr addr;
 123             unsigned int irq;
 124         } epit_table[FSL_IMX31_NUM_EPITS] = {
 125             { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
 126             { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
 127         };
 128
 129         s->epit[i].ccm = IMX_CCM(&s->ccm);
 130
 131         if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) {
 132             return;
 133         }
 134
 135         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 136         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 137                            qdev_get_gpio_in(DEVICE(&s->avic),
 138                                             epit_table[i].irq));
 139     }
 140
 141     /* Initialize all I2C */
 142     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
 143         static const struct {
 144             hwaddr addr;
 145             unsigned int irq;
 146         } i2c_table[FSL_IMX31_NUM_I2CS] = {
 147             { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
 148             { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
 149             { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
 150         };
 151
 152         /* Initialize the I2C */
 153         if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
 154             return;
 155         }
 156         /* Map I2C memory */
 157         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 158         /* Connect I2C IRQ to PIC */
 159         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 160                            qdev_get_gpio_in(DEVICE(&s->avic),
 161                                             i2c_table[i].irq));
 162     }
 163
 164     /* Initialize all GPIOs */
 165     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
 166         static const struct {
 167             hwaddr addr;
 168             unsigned int irq;
 169         } gpio_table[FSL_IMX31_NUM_GPIOS] = {
 170             { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
 171             { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
 172             { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
 173         };
 174
 175         object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", false,
 176                                  &error_abort);
 177         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
 178             return;
 179         }
 180         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 181         /* Connect GPIO IRQ to PIC */
 182         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 183                            qdev_get_gpio_in(DEVICE(&s->avic),
 184                                             gpio_table[i].irq));
 185     }
 186
 187     /* Watchdog */
 188     sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
 189     sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
 190
 191     /* On a real system, the first 16k is a `secure boot rom' */
 192     memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
 193                            FSL_IMX31_SECURE_ROM_SIZE, &err);
 194     if (err) {
 195         error_propagate(errp, err);
 196         return;
 197     }
 198     memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
 199                                 &s->secure_rom);
 200
 201     /* There is also a 16k ROM */
 202     memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom",
 203                            FSL_IMX31_ROM_SIZE, &err);
 204     if (err) {
 205         error_propagate(errp, err);
 206         return;
 207     }
 208     memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
 209                                 &s->rom);
 210
 211     /* initialize internal RAM (16 KB) */
 212     memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
 213                            &err);
 214     if (err) {
 215         error_propagate(errp, err);
 216         return;
 217     }
 218     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
 219                                 &s->iram);
 220
 221     /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
 222     memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx31.iram_alias",
 223                              &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
 224     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
 225                                 &s->iram_alias);
 226 }
 227
 228 static void fsl_imx31_class_init(ObjectClass *oc, void *data)
 229 {
 230     DeviceClass *dc = DEVICE_CLASS(oc);
 231
 232     dc->realize = fsl_imx31_realize;
 233     dc->desc = "i.MX31 SOC";
 234     /*
 235      * Reason: uses serial_hds in realize and the kzm board does not
 236      * support multiple CPUs
 237      */
 238     dc->user_creatable = false;
 239 }
 240
 241 static const TypeInfo fsl_imx31_type_info = {
 242     .name = TYPE_FSL_IMX31,
 243     .parent = TYPE_DEVICE,
 244     .instance_size = sizeof(FslIMX31State),
 245     .instance_init = fsl_imx31_init,
 246     .class_init = fsl_imx31_class_init,
 247 };
 248
 249 static void fsl_imx31_register_types(void)
 250 {
 251     type_register_static(&fsl_imx31_type_info);
 252 }
 253
 254 type_init(fsl_imx31_register_types)