hw/display/cirrus_vga: Clean up indentation in pci_cirrus_vga_realize()
[qemu/ar7.git] / hw / rdma / rdma_rm_defs.h
blob534f2f74d3d19bfaa2df029e22d594f4943b6353
1 /*
2 * RDMA device: Definitions of Resource Manager structures
4 * Copyright (C) 2018 Oracle
5 * Copyright (C) 2018 Red Hat Inc
7 * Authors:
8 * Yuval Shaia <yuval.shaia@oracle.com>
9 * Marcel Apfelbaum <marcel@redhat.com>
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
16 #ifndef RDMA_RM_DEFS_H
17 #define RDMA_RM_DEFS_H
19 #include "rdma_backend_defs.h"
21 #define MAX_PORTS 1 /* Do not change - we support only one port */
22 #define MAX_PORT_GIDS 255
23 #define MAX_GIDS MAX_PORT_GIDS
24 #define MAX_PORT_PKEYS 1
25 #define MAX_PKEYS MAX_PORT_PKEYS
26 #define MAX_UCS 512
27 #define MAX_MR_SIZE (1UL << 27)
28 #define MAX_QP 1024
29 #define MAX_SGE 4
30 #define MAX_CQ 2048
31 #define MAX_MR 1024
32 #define MAX_PD 1024
33 #define MAX_QP_RD_ATOM 16
34 #define MAX_QP_INIT_RD_ATOM 16
35 #define MAX_AH 64
36 #define MAX_SRQ 512
38 #define MAX_RM_TBL_NAME 16
39 #define MAX_CONSEQ_EMPTY_POLL_CQ 4096 /* considered as error above this */
41 typedef struct RdmaRmResTbl {
42 char name[MAX_RM_TBL_NAME];
43 QemuMutex lock;
44 unsigned long *bitmap;
45 size_t tbl_sz;
46 size_t res_sz;
47 void *tbl;
48 uint32_t used; /* number of used entries in the table */
49 } RdmaRmResTbl;
51 typedef struct RdmaRmPD {
52 RdmaBackendPD backend_pd;
53 uint32_t ctx_handle;
54 } RdmaRmPD;
56 typedef enum CQNotificationType {
57 CNT_CLEAR,
58 CNT_ARM,
59 CNT_SET,
60 } CQNotificationType;
62 typedef struct RdmaRmCQ {
63 RdmaBackendCQ backend_cq;
64 void *opaque;
65 CQNotificationType notify;
66 } RdmaRmCQ;
68 /* MR (DMA region) */
69 typedef struct RdmaRmMR {
70 RdmaBackendMR backend_mr;
71 void *virt;
72 uint64_t start;
73 size_t length;
74 uint32_t pd_handle;
75 uint32_t lkey;
76 uint32_t rkey;
77 } RdmaRmMR;
79 typedef struct RdmaRmUC {
80 uint64_t uc_handle;
81 } RdmaRmUC;
83 typedef struct RdmaRmQP {
84 RdmaBackendQP backend_qp;
85 void *opaque;
86 uint32_t qp_type;
87 uint32_t qpn;
88 uint32_t send_cq_handle;
89 uint32_t recv_cq_handle;
90 enum ibv_qp_state qp_state;
91 uint8_t is_srq;
92 } RdmaRmQP;
94 typedef struct RdmaRmSRQ {
95 RdmaBackendSRQ backend_srq;
96 uint32_t recv_cq_handle;
97 void *opaque;
98 } RdmaRmSRQ;
100 typedef struct RdmaRmGid {
101 union ibv_gid gid;
102 int backend_gid_index;
103 } RdmaRmGid;
105 typedef struct RdmaRmPort {
106 RdmaRmGid gid_tbl[MAX_PORT_GIDS];
107 enum ibv_port_state state;
108 } RdmaRmPort;
110 typedef struct RdmaRmStats {
111 uint64_t tx;
112 uint64_t tx_len;
113 uint64_t tx_err;
114 uint64_t rx_bufs;
115 uint64_t rx_bufs_len;
116 uint64_t rx_bufs_err;
117 uint64_t rx_srq;
118 uint64_t completions;
119 uint64_t mad_tx;
120 uint64_t mad_tx_err;
121 uint64_t mad_rx;
122 uint64_t mad_rx_err;
123 uint64_t mad_rx_bufs;
124 uint64_t mad_rx_bufs_err;
125 uint64_t poll_cq_from_bk;
126 uint64_t poll_cq_from_guest;
127 uint64_t poll_cq_from_guest_empty;
128 uint64_t poll_cq_ppoll_to;
129 uint32_t missing_cqe;
130 } RdmaRmStats;
132 struct RdmaDeviceResources {
133 RdmaRmPort port;
134 RdmaRmResTbl pd_tbl;
135 RdmaRmResTbl mr_tbl;
136 RdmaRmResTbl uc_tbl;
137 RdmaRmResTbl qp_tbl;
138 RdmaRmResTbl cq_tbl;
139 RdmaRmResTbl cqe_ctx_tbl;
140 RdmaRmResTbl srq_tbl;
141 GHashTable *qp_hash; /* Keeps mapping between real and emulated */
142 QemuMutex lock;
143 RdmaRmStats stats;
146 #endif