hw/core/cpu-common.c

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/core/cpu.h"
  24 #include "sysemu/hw_accel.h"
  25 #include "qemu/notify.h"
  26 #include "qemu/log.h"
  27 #include "qemu/main-loop.h"
  28 #include "exec/log.h"
  29 #include "exec/cpu-common.h"
  30 #include "qemu/error-report.h"
  31 #include "qemu/qemu-print.h"
  32 #include "sysemu/tcg.h"
  33 #include "hw/boards.h"
  34 #include "hw/qdev-properties.h"
  35 #include "trace/trace-root.h"
  36 #include "qemu/plugin.h"
  37
  38 CPUState *cpu_by_arch_id(int64_t id)
  39 {
  40     CPUState *cpu;
  41
  42     CPU_FOREACH(cpu) {
  43         CPUClass *cc = CPU_GET_CLASS(cpu);
  44
  45         if (cc->get_arch_id(cpu) == id) {
  46             return cpu;
  47         }
  48     }
  49     return NULL;
  50 }
  51
  52 bool cpu_exists(int64_t id)
  53 {
  54     return !!cpu_by_arch_id(id);
  55 }
  56
  57 CPUState *cpu_create(const char *typename)
  58 {
  59     Error *err = NULL;
  60     CPUState *cpu = CPU(object_new(typename));
  61     if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
  62         error_report_err(err);
  63         object_unref(OBJECT(cpu));
  64         exit(EXIT_FAILURE);
  65     }
  66     return cpu;
  67 }
  68
  69 bool cpu_paging_enabled(const CPUState *cpu)
  70 {
  71     CPUClass *cc = CPU_GET_CLASS(cpu);
  72
  73     return cc->get_paging_enabled(cpu);
  74 }
  75
  76 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
  77 {
  78     return false;
  79 }
  80
  81 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
  82                             Error **errp)
  83 {
  84     CPUClass *cc = CPU_GET_CLASS(cpu);
  85
  86     cc->get_memory_mapping(cpu, list, errp);
  87 }
  88
  89 static void cpu_common_get_memory_mapping(CPUState *cpu,
  90                                           MemoryMappingList *list,
  91                                           Error **errp)
  92 {
  93     error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
  94 }
  95
  96 /* Resetting the IRQ comes from across the code base so we take the
  97  * BQL here if we need to.  cpu_interrupt assumes it is held.*/
  98 void cpu_reset_interrupt(CPUState *cpu, int mask)
  99 {
 100     bool need_lock = !qemu_mutex_iothread_locked();
 101
 102     if (need_lock) {
 103         qemu_mutex_lock_iothread();
 104     }
 105     cpu->interrupt_request &= ~mask;
 106     if (need_lock) {
 107         qemu_mutex_unlock_iothread();
 108     }
 109 }
 110
 111 void cpu_exit(CPUState *cpu)
 112 {
 113     qatomic_set(&cpu->exit_request, 1);
 114     /* Ensure cpu_exec will see the exit request after TCG has exited.  */
 115     smp_wmb();
 116     qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
 117 }
 118
 119 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
 120 {
 121     return 0;
 122 }
 123
 124 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
 125 {
 126     return 0;
 127 }
 128
 129 void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
 130 {
 131     CPUClass *cc = CPU_GET_CLASS(cpu);
 132
 133     if (cc->dump_state) {
 134         cpu_synchronize_state(cpu);
 135         cc->dump_state(cpu, f, flags);
 136     }
 137 }
 138
 139 void cpu_dump_statistics(CPUState *cpu, int flags)
 140 {
 141     CPUClass *cc = CPU_GET_CLASS(cpu);
 142
 143     if (cc->dump_statistics) {
 144         cc->dump_statistics(cpu, flags);
 145     }
 146 }
 147
 148 void cpu_reset(CPUState *cpu)
 149 {
 150     device_cold_reset(DEVICE(cpu));
 151
 152     trace_guest_cpu_reset(cpu);
 153 }
 154
 155 static void cpu_common_reset(DeviceState *dev)
 156 {
 157     CPUState *cpu = CPU(dev);
 158     CPUClass *cc = CPU_GET_CLASS(cpu);
 159
 160     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 161         qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
 162         log_cpu_state(cpu, cc->reset_dump_flags);
 163     }
 164
 165     cpu->interrupt_request = 0;
 166     cpu->halted = cpu->start_powered_off;
 167     cpu->mem_io_pc = 0;
 168     cpu->icount_extra = 0;
 169     qatomic_set(&cpu->icount_decr_ptr->u32, 0);
 170     cpu->can_do_io = 1;
 171     cpu->exception_index = -1;
 172     cpu->crash_occurred = false;
 173     cpu->cflags_next_tb = -1;
 174
 175     if (tcg_enabled()) {
 176         cpu_tb_jmp_cache_clear(cpu);
 177
 178         tcg_flush_softmmu_tlb(cpu);
 179     }
 180 }
 181
 182 static bool cpu_common_has_work(CPUState *cs)
 183 {
 184     return false;
 185 }
 186
 187 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
 188 {
 189     CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
 190
 191     assert(cpu_model && cc->class_by_name);
 192     return cc->class_by_name(cpu_model);
 193 }
 194
 195 static void cpu_common_parse_features(const char *typename, char *features,
 196                                       Error **errp)
 197 {
 198     char *val;
 199     static bool cpu_globals_initialized;
 200     /* Single "key=value" string being parsed */
 201     char *featurestr = features ? strtok(features, ",") : NULL;
 202
 203     /* should be called only once, catch invalid users */
 204     assert(!cpu_globals_initialized);
 205     cpu_globals_initialized = true;
 206
 207     while (featurestr) {
 208         val = strchr(featurestr, '=');
 209         if (val) {
 210             GlobalProperty *prop = g_new0(typeof(*prop), 1);
 211             *val = 0;
 212             val++;
 213             prop->driver = typename;
 214             prop->property = g_strdup(featurestr);
 215             prop->value = g_strdup(val);
 216             qdev_prop_register_global(prop);
 217         } else {
 218             error_setg(errp, "Expected key=value format, found %s.",
 219                        featurestr);
 220             return;
 221         }
 222         featurestr = strtok(NULL, ",");
 223     }
 224 }
 225
 226 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
 227 {
 228     CPUState *cpu = CPU(dev);
 229     Object *machine = qdev_get_machine();
 230
 231     /* qdev_get_machine() can return something that's not TYPE_MACHINE
 232      * if this is one of the user-only emulators; in that case there's
 233      * no need to check the ignore_memory_transaction_failures board flag.
 234      */
 235     if (object_dynamic_cast(machine, TYPE_MACHINE)) {
 236         ObjectClass *oc = object_get_class(machine);
 237         MachineClass *mc = MACHINE_CLASS(oc);
 238
 239         if (mc) {
 240             cpu->ignore_memory_transaction_failures =
 241                 mc->ignore_memory_transaction_failures;
 242         }
 243     }
 244
 245     if (dev->hotplugged) {
 246         cpu_synchronize_post_init(cpu);
 247         cpu_resume(cpu);
 248     }
 249
 250     /* NOTE: latest generic point where the cpu is fully realized */
 251     trace_init_vcpu(cpu);
 252 }
 253
 254 static void cpu_common_unrealizefn(DeviceState *dev)
 255 {
 256     CPUState *cpu = CPU(dev);
 257
 258     /* NOTE: latest generic point before the cpu is fully unrealized */
 259     trace_fini_vcpu(cpu);
 260     cpu_exec_unrealizefn(cpu);
 261 }
 262
 263 static void cpu_common_initfn(Object *obj)
 264 {
 265     CPUState *cpu = CPU(obj);
 266     CPUClass *cc = CPU_GET_CLASS(obj);
 267
 268     cpu->cpu_index = UNASSIGNED_CPU_INDEX;
 269     cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
 270     cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
 271     /* *-user doesn't have configurable SMP topology */
 272     /* the default value is changed by qemu_init_vcpu() for softmmu */
 273     cpu->nr_cores = 1;
 274     cpu->nr_threads = 1;
 275
 276     qemu_mutex_init(&cpu->work_mutex);
 277     QSIMPLEQ_INIT(&cpu->work_list);
 278     QTAILQ_INIT(&cpu->breakpoints);
 279     QTAILQ_INIT(&cpu->watchpoints);
 280
 281     cpu_exec_initfn(cpu);
 282 }
 283
 284 static void cpu_common_finalize(Object *obj)
 285 {
 286     CPUState *cpu = CPU(obj);
 287
 288     qemu_mutex_destroy(&cpu->work_mutex);
 289 }
 290
 291 static int64_t cpu_common_get_arch_id(CPUState *cpu)
 292 {
 293     return cpu->cpu_index;
 294 }
 295
 296 static Property cpu_common_props[] = {
 297 #ifndef CONFIG_USER_ONLY
 298     /* Create a memory property for softmmu CPU object,
 299      * so users can wire up its memory. (This can't go in hw/core/cpu.c
 300      * because that file is compiled only once for both user-mode
 301      * and system builds.) The default if no link is set up is to use
 302      * the system address space.
 303      */
 304     DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 305                      MemoryRegion *),
 306 #endif
 307     DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
 308     DEFINE_PROP_END_OF_LIST(),
 309 };
 310
 311 static void cpu_class_init(ObjectClass *klass, void *data)
 312 {
 313     DeviceClass *dc = DEVICE_CLASS(klass);
 314     CPUClass *k = CPU_CLASS(klass);
 315
 316     k->parse_features = cpu_common_parse_features;
 317     k->get_arch_id = cpu_common_get_arch_id;
 318     k->has_work = cpu_common_has_work;
 319     k->get_paging_enabled = cpu_common_get_paging_enabled;
 320     k->get_memory_mapping = cpu_common_get_memory_mapping;
 321     k->gdb_read_register = cpu_common_gdb_read_register;
 322     k->gdb_write_register = cpu_common_gdb_write_register;
 323     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
 324     dc->realize = cpu_common_realizefn;
 325     dc->unrealize = cpu_common_unrealizefn;
 326     dc->reset = cpu_common_reset;
 327     device_class_set_props(dc, cpu_common_props);
 328     /*
 329      * Reason: CPUs still need special care by board code: wiring up
 330      * IRQs, adding reset handlers, halting non-first CPUs, ...
 331      */
 332     dc->user_creatable = false;
 333 }
 334
 335 static const TypeInfo cpu_type_info = {
 336     .name = TYPE_CPU,
 337     .parent = TYPE_DEVICE,
 338     .instance_size = sizeof(CPUState),
 339     .instance_init = cpu_common_initfn,
 340     .instance_finalize = cpu_common_finalize,
 341     .abstract = true,
 342     .class_size = sizeof(CPUClass),
 343     .class_init = cpu_class_init,
 344 };
 345
 346 static void cpu_register_types(void)
 347 {
 348     type_register_static(&cpu_type_info);
 349 }
 350
 351 type_init(cpu_register_types)