Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-07-15' into staging
[qemu/ar7.git] / target / xtensa / cpu.h
blob2c277134f199be5227cbe4182419ebd88901e240
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #ifndef XTENSA_CPU_H
29 #define XTENSA_CPU_H
31 #include "cpu-qom.h"
32 #include "exec/cpu-defs.h"
33 #include "xtensa-isa.h"
35 #define ALIGNED_ONLY
37 /* Xtensa processors have a weak memory model */
38 #define TCG_GUEST_DEFAULT_MO (0)
40 enum {
41 /* Additional instructions */
42 XTENSA_OPTION_CODE_DENSITY,
43 XTENSA_OPTION_LOOP,
44 XTENSA_OPTION_EXTENDED_L32R,
45 XTENSA_OPTION_16_BIT_IMUL,
46 XTENSA_OPTION_32_BIT_IMUL,
47 XTENSA_OPTION_32_BIT_IMUL_HIGH,
48 XTENSA_OPTION_32_BIT_IDIV,
49 XTENSA_OPTION_MAC16,
50 XTENSA_OPTION_MISC_OP_NSA,
51 XTENSA_OPTION_MISC_OP_MINMAX,
52 XTENSA_OPTION_MISC_OP_SEXT,
53 XTENSA_OPTION_MISC_OP_CLAMPS,
54 XTENSA_OPTION_COPROCESSOR,
55 XTENSA_OPTION_BOOLEAN,
56 XTENSA_OPTION_FP_COPROCESSOR,
57 XTENSA_OPTION_MP_SYNCHRO,
58 XTENSA_OPTION_CONDITIONAL_STORE,
59 XTENSA_OPTION_ATOMCTL,
60 XTENSA_OPTION_DEPBITS,
62 /* Interrupts and exceptions */
63 XTENSA_OPTION_EXCEPTION,
64 XTENSA_OPTION_RELOCATABLE_VECTOR,
65 XTENSA_OPTION_UNALIGNED_EXCEPTION,
66 XTENSA_OPTION_INTERRUPT,
67 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
68 XTENSA_OPTION_TIMER_INTERRUPT,
70 /* Local memory */
71 XTENSA_OPTION_ICACHE,
72 XTENSA_OPTION_ICACHE_TEST,
73 XTENSA_OPTION_ICACHE_INDEX_LOCK,
74 XTENSA_OPTION_DCACHE,
75 XTENSA_OPTION_DCACHE_TEST,
76 XTENSA_OPTION_DCACHE_INDEX_LOCK,
77 XTENSA_OPTION_IRAM,
78 XTENSA_OPTION_IROM,
79 XTENSA_OPTION_DRAM,
80 XTENSA_OPTION_DROM,
81 XTENSA_OPTION_XLMI,
82 XTENSA_OPTION_HW_ALIGNMENT,
83 XTENSA_OPTION_MEMORY_ECC_PARITY,
85 /* Memory protection and translation */
86 XTENSA_OPTION_REGION_PROTECTION,
87 XTENSA_OPTION_REGION_TRANSLATION,
88 XTENSA_OPTION_MPU,
89 XTENSA_OPTION_MMU,
90 XTENSA_OPTION_CACHEATTR,
92 /* Other */
93 XTENSA_OPTION_WINDOWED_REGISTER,
94 XTENSA_OPTION_PROCESSOR_INTERFACE,
95 XTENSA_OPTION_MISC_SR,
96 XTENSA_OPTION_THREAD_POINTER,
97 XTENSA_OPTION_PROCESSOR_ID,
98 XTENSA_OPTION_DEBUG,
99 XTENSA_OPTION_TRACE_PORT,
100 XTENSA_OPTION_EXTERN_REGS,
103 enum {
104 EXPSTATE = 230,
105 THREADPTR = 231,
106 FCR = 232,
107 FSR = 233,
110 enum {
111 LBEG = 0,
112 LEND = 1,
113 LCOUNT = 2,
114 SAR = 3,
115 BR = 4,
116 LITBASE = 5,
117 SCOMPARE1 = 12,
118 ACCLO = 16,
119 ACCHI = 17,
120 MR = 32,
121 PREFCTL = 40,
122 WINDOW_BASE = 72,
123 WINDOW_START = 73,
124 PTEVADDR = 83,
125 MMID = 89,
126 RASID = 90,
127 MPUENB = 90,
128 ITLBCFG = 91,
129 DTLBCFG = 92,
130 MPUCFG = 92,
131 ERACCESS = 95,
132 IBREAKENABLE = 96,
133 MEMCTL = 97,
134 CACHEATTR = 98,
135 CACHEADRDIS = 98,
136 ATOMCTL = 99,
137 DDR = 104,
138 MEPC = 106,
139 MEPS = 107,
140 MESAVE = 108,
141 MESR = 109,
142 MECR = 110,
143 MEVADDR = 111,
144 IBREAKA = 128,
145 DBREAKA = 144,
146 DBREAKC = 160,
147 CONFIGID0 = 176,
148 EPC1 = 177,
149 DEPC = 192,
150 EPS2 = 194,
151 CONFIGID1 = 208,
152 EXCSAVE1 = 209,
153 CPENABLE = 224,
154 INTSET = 226,
155 INTCLEAR = 227,
156 INTENABLE = 228,
157 PS = 230,
158 VECBASE = 231,
159 EXCCAUSE = 232,
160 DEBUGCAUSE = 233,
161 CCOUNT = 234,
162 PRID = 235,
163 ICOUNT = 236,
164 ICOUNTLEVEL = 237,
165 EXCVADDR = 238,
166 CCOMPARE = 240,
167 MISC = 244,
170 #define PS_INTLEVEL 0xf
171 #define PS_INTLEVEL_SHIFT 0
173 #define PS_EXCM 0x10
174 #define PS_UM 0x20
176 #define PS_RING 0xc0
177 #define PS_RING_SHIFT 6
179 #define PS_OWB 0xf00
180 #define PS_OWB_SHIFT 8
181 #define PS_OWB_LEN 4
183 #define PS_CALLINC 0x30000
184 #define PS_CALLINC_SHIFT 16
185 #define PS_CALLINC_LEN 2
187 #define PS_WOE 0x40000
189 #define DEBUGCAUSE_IC 0x1
190 #define DEBUGCAUSE_IB 0x2
191 #define DEBUGCAUSE_DB 0x4
192 #define DEBUGCAUSE_BI 0x8
193 #define DEBUGCAUSE_BN 0x10
194 #define DEBUGCAUSE_DI 0x20
195 #define DEBUGCAUSE_DBNUM 0xf00
196 #define DEBUGCAUSE_DBNUM_SHIFT 8
198 #define DBREAKC_SB 0x80000000
199 #define DBREAKC_LB 0x40000000
200 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
201 #define DBREAKC_MASK 0x3f
203 #define MEMCTL_INIT 0x00800000
204 #define MEMCTL_IUSEWAYS_SHIFT 18
205 #define MEMCTL_IUSEWAYS_LEN 5
206 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
207 #define MEMCTL_DALLOCWAYS_SHIFT 13
208 #define MEMCTL_DALLOCWAYS_LEN 5
209 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
210 #define MEMCTL_DUSEWAYS_SHIFT 8
211 #define MEMCTL_DUSEWAYS_LEN 5
212 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
213 #define MEMCTL_ISNP 0x4
214 #define MEMCTL_DSNP 0x2
215 #define MEMCTL_IL0EN 0x1
217 #define MAX_INSN_LENGTH 64
218 #define MAX_INSN_SLOTS 32
219 #define MAX_OPCODE_ARGS 16
220 #define MAX_NAREG 64
221 #define MAX_NINTERRUPT 32
222 #define MAX_NLEVEL 6
223 #define MAX_NNMI 1
224 #define MAX_NCCOMPARE 3
225 #define MAX_TLB_WAY_SIZE 8
226 #define MAX_NDBREAK 2
227 #define MAX_NMEMORY 4
228 #define MAX_MPU_FOREGROUND_SEGMENTS 32
230 #define REGION_PAGE_MASK 0xe0000000
232 #define PAGE_CACHE_MASK 0x700
233 #define PAGE_CACHE_SHIFT 8
234 #define PAGE_CACHE_INVALID 0x000
235 #define PAGE_CACHE_BYPASS 0x100
236 #define PAGE_CACHE_WT 0x200
237 #define PAGE_CACHE_WB 0x400
238 #define PAGE_CACHE_ISOLATE 0x600
240 enum {
241 /* Static vectors */
242 EXC_RESET0,
243 EXC_RESET1,
244 EXC_MEMORY_ERROR,
246 /* Dynamic vectors */
247 EXC_WINDOW_OVERFLOW4,
248 EXC_WINDOW_UNDERFLOW4,
249 EXC_WINDOW_OVERFLOW8,
250 EXC_WINDOW_UNDERFLOW8,
251 EXC_WINDOW_OVERFLOW12,
252 EXC_WINDOW_UNDERFLOW12,
253 EXC_IRQ,
254 EXC_KERNEL,
255 EXC_USER,
256 EXC_DOUBLE,
257 EXC_DEBUG,
258 EXC_MAX
261 enum {
262 ILLEGAL_INSTRUCTION_CAUSE = 0,
263 SYSCALL_CAUSE,
264 INSTRUCTION_FETCH_ERROR_CAUSE,
265 LOAD_STORE_ERROR_CAUSE,
266 LEVEL1_INTERRUPT_CAUSE,
267 ALLOCA_CAUSE,
268 INTEGER_DIVIDE_BY_ZERO_CAUSE,
269 PC_VALUE_ERROR_CAUSE,
270 PRIVILEGED_CAUSE,
271 LOAD_STORE_ALIGNMENT_CAUSE,
272 EXTERNAL_REG_PRIVILEGE_CAUSE,
273 EXCLUSIVE_ERROR_CAUSE,
274 INSTR_PIF_DATA_ERROR_CAUSE,
275 LOAD_STORE_PIF_DATA_ERROR_CAUSE,
276 INSTR_PIF_ADDR_ERROR_CAUSE,
277 LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
278 INST_TLB_MISS_CAUSE,
279 INST_TLB_MULTI_HIT_CAUSE,
280 INST_FETCH_PRIVILEGE_CAUSE,
281 INST_FETCH_PROHIBITED_CAUSE = 20,
282 LOAD_STORE_TLB_MISS_CAUSE = 24,
283 LOAD_STORE_TLB_MULTI_HIT_CAUSE,
284 LOAD_STORE_PRIVILEGE_CAUSE,
285 LOAD_PROHIBITED_CAUSE = 28,
286 STORE_PROHIBITED_CAUSE,
288 COPROCESSOR0_DISABLED = 32,
291 typedef enum {
292 INTTYPE_LEVEL,
293 INTTYPE_EDGE,
294 INTTYPE_NMI,
295 INTTYPE_SOFTWARE,
296 INTTYPE_TIMER,
297 INTTYPE_DEBUG,
298 INTTYPE_WRITE_ERR,
299 INTTYPE_PROFILING,
300 INTTYPE_IDMA_DONE,
301 INTTYPE_IDMA_ERR,
302 INTTYPE_GS_ERR,
303 INTTYPE_MAX
304 } interrupt_type;
306 struct CPUXtensaState;
308 typedef struct xtensa_tlb_entry {
309 uint32_t vaddr;
310 uint32_t paddr;
311 uint8_t asid;
312 uint8_t attr;
313 bool variable;
314 } xtensa_tlb_entry;
316 typedef struct xtensa_tlb {
317 unsigned nways;
318 const unsigned way_size[10];
319 bool varway56;
320 unsigned nrefillentries;
321 } xtensa_tlb;
323 typedef struct xtensa_mpu_entry {
324 uint32_t vaddr;
325 uint32_t attr;
326 } xtensa_mpu_entry;
328 typedef struct XtensaGdbReg {
329 int targno;
330 unsigned flags;
331 int type;
332 int group;
333 unsigned size;
334 } XtensaGdbReg;
336 typedef struct XtensaGdbRegmap {
337 int num_regs;
338 int num_core_regs;
339 /* PC + a + ar + sr + ur */
340 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
341 } XtensaGdbRegmap;
343 typedef struct XtensaCcompareTimer {
344 struct CPUXtensaState *env;
345 QEMUTimer *timer;
346 } XtensaCcompareTimer;
348 typedef struct XtensaMemory {
349 unsigned num;
350 struct XtensaMemoryRegion {
351 uint32_t addr;
352 uint32_t size;
353 } location[MAX_NMEMORY];
354 } XtensaMemory;
356 typedef struct opcode_arg {
357 uint32_t imm;
358 uint32_t raw_imm;
359 void *in;
360 void *out;
361 } OpcodeArg;
363 typedef struct DisasContext DisasContext;
364 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
365 const uint32_t par[]);
366 typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
367 const OpcodeArg arg[],
368 const uint32_t par[]);
369 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
370 const OpcodeArg arg[],
371 const uint32_t par[]);
373 enum {
374 XTENSA_OP_ILL = 0x1,
375 XTENSA_OP_PRIVILEGED = 0x2,
376 XTENSA_OP_SYSCALL = 0x4,
377 XTENSA_OP_DEBUG_BREAK = 0x8,
379 XTENSA_OP_OVERFLOW = 0x10,
380 XTENSA_OP_UNDERFLOW = 0x20,
381 XTENSA_OP_ALLOCA = 0x40,
382 XTENSA_OP_COPROCESSOR = 0x80,
384 XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
386 /* Postprocessing flags */
387 XTENSA_OP_CHECK_INTERRUPTS = 0x200,
388 XTENSA_OP_EXIT_TB_M1 = 0x400,
389 XTENSA_OP_EXIT_TB_0 = 0x800,
390 XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000,
392 XTENSA_OP_POSTPROCESS =
393 XTENSA_OP_CHECK_INTERRUPTS |
394 XTENSA_OP_EXIT_TB_M1 |
395 XTENSA_OP_EXIT_TB_0 |
396 XTENSA_OP_SYNC_REGISTER_WINDOW,
398 XTENSA_OP_NAME_ARRAY = 0x8000,
400 XTENSA_OP_CONTROL_FLOW = 0x10000,
401 XTENSA_OP_STORE = 0x20000,
402 XTENSA_OP_LOAD = 0x40000,
403 XTENSA_OP_LOAD_STORE =
404 XTENSA_OP_LOAD | XTENSA_OP_STORE,
407 typedef struct XtensaOpcodeOps {
408 const void *name;
409 XtensaOpcodeOp translate;
410 XtensaOpcodeBoolTest test_ill;
411 XtensaOpcodeUintTest test_overflow;
412 const uint32_t *par;
413 uint32_t op_flags;
414 uint32_t coprocessor;
415 } XtensaOpcodeOps;
417 typedef struct XtensaOpcodeTranslators {
418 unsigned num_opcodes;
419 const XtensaOpcodeOps *opcode;
420 } XtensaOpcodeTranslators;
422 extern const XtensaOpcodeTranslators xtensa_core_opcodes;
423 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
425 struct XtensaConfig {
426 const char *name;
427 uint64_t options;
428 XtensaGdbRegmap gdb_regmap;
429 unsigned nareg;
430 int excm_level;
431 int ndepc;
432 unsigned inst_fetch_width;
433 unsigned max_insn_size;
434 uint32_t vecbase;
435 uint32_t exception_vector[EXC_MAX];
436 unsigned ninterrupt;
437 unsigned nlevel;
438 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
439 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
440 uint32_t inttype_mask[INTTYPE_MAX];
441 struct {
442 uint32_t level;
443 interrupt_type inttype;
444 } interrupt[MAX_NINTERRUPT];
445 unsigned nccompare;
446 uint32_t timerint[MAX_NCCOMPARE];
447 unsigned nextint;
448 unsigned extint[MAX_NINTERRUPT];
450 unsigned debug_level;
451 unsigned nibreak;
452 unsigned ndbreak;
454 unsigned icache_ways;
455 unsigned dcache_ways;
456 unsigned dcache_line_bytes;
457 uint32_t memctl_mask;
459 XtensaMemory instrom;
460 XtensaMemory instram;
461 XtensaMemory datarom;
462 XtensaMemory dataram;
463 XtensaMemory sysrom;
464 XtensaMemory sysram;
466 uint32_t configid[2];
468 void *isa_internal;
469 xtensa_isa isa;
470 XtensaOpcodeOps **opcode_ops;
471 const XtensaOpcodeTranslators **opcode_translators;
472 xtensa_regfile a_regfile;
473 void ***regfile;
475 uint32_t clock_freq_khz;
477 xtensa_tlb itlb;
478 xtensa_tlb dtlb;
480 uint32_t mpu_align;
481 unsigned n_mpu_fg_segments;
482 unsigned n_mpu_bg_segments;
483 const xtensa_mpu_entry *mpu_bg;
486 typedef struct XtensaConfigList {
487 const XtensaConfig *config;
488 struct XtensaConfigList *next;
489 } XtensaConfigList;
491 #ifdef HOST_WORDS_BIGENDIAN
492 enum {
493 FP_F32_HIGH,
494 FP_F32_LOW,
496 #else
497 enum {
498 FP_F32_LOW,
499 FP_F32_HIGH,
501 #endif
503 typedef struct CPUXtensaState {
504 const XtensaConfig *config;
505 uint32_t regs[16];
506 uint32_t pc;
507 uint32_t sregs[256];
508 uint32_t uregs[256];
509 uint32_t phys_regs[MAX_NAREG];
510 union {
511 float32 f32[2];
512 float64 f64;
513 } fregs[16];
514 float_status fp_status;
515 uint32_t windowbase_next;
516 uint32_t exclusive_addr;
517 uint32_t exclusive_val;
519 #ifndef CONFIG_USER_ONLY
520 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
521 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
522 xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
523 unsigned autorefill_idx;
524 bool runstall;
525 AddressSpace *address_space_er;
526 MemoryRegion *system_er;
527 int pending_irq_level; /* level of last raised IRQ */
528 qemu_irq *irq_inputs;
529 qemu_irq ext_irq_inputs[MAX_NINTERRUPT];
530 qemu_irq runstall_irq;
531 XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
532 uint64_t time_base;
533 uint64_t ccount_time;
534 uint32_t ccount_base;
535 #endif
537 int exception_taken;
538 int yield_needed;
539 unsigned static_vectors;
541 /* Watchpoints for DBREAK registers */
542 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
543 } CPUXtensaState;
546 * XtensaCPU:
547 * @env: #CPUXtensaState
549 * An Xtensa CPU.
551 struct XtensaCPU {
552 /*< private >*/
553 CPUState parent_obj;
554 /*< public >*/
556 CPUNegativeOffsetState neg;
557 CPUXtensaState env;
561 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
562 MMUAccessType access_type, int mmu_idx,
563 bool probe, uintptr_t retaddr);
564 void xtensa_cpu_do_interrupt(CPUState *cpu);
565 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
566 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
567 unsigned size, MMUAccessType access_type,
568 int mmu_idx, MemTxAttrs attrs,
569 MemTxResult response, uintptr_t retaddr);
570 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
571 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
572 void xtensa_count_regs(const XtensaConfig *config,
573 unsigned *n_regs, unsigned *n_core_regs);
574 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
575 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
576 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
577 MMUAccessType access_type,
578 int mmu_idx, uintptr_t retaddr);
580 #define cpu_signal_handler cpu_xtensa_signal_handler
581 #define cpu_list xtensa_cpu_list
583 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
584 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
585 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
587 #ifdef TARGET_WORDS_BIGENDIAN
588 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
589 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
590 #else
591 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
592 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
593 #endif
594 #define XTENSA_DEFAULT_CPU_TYPE \
595 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
596 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
597 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
599 void xtensa_collect_sr_names(const XtensaConfig *config);
600 void xtensa_translate_init(void);
601 void **xtensa_get_regfile_by_name(const char *name);
602 void xtensa_breakpoint_handler(CPUState *cs);
603 void xtensa_register_core(XtensaConfigList *node);
604 void xtensa_sim_open_console(Chardev *chr);
605 void check_interrupts(CPUXtensaState *s);
606 void xtensa_irq_init(CPUXtensaState *env);
607 qemu_irq *xtensa_get_extints(CPUXtensaState *env);
608 qemu_irq xtensa_get_runstall(CPUXtensaState *env);
609 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
610 void xtensa_cpu_list(void);
611 void xtensa_sync_window_from_phys(CPUXtensaState *env);
612 void xtensa_sync_phys_from_window(CPUXtensaState *env);
613 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
614 void xtensa_restore_owb(CPUXtensaState *env);
615 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
617 static inline void xtensa_select_static_vectors(CPUXtensaState *env,
618 unsigned n)
620 assert(n < 2);
621 env->static_vectors = n;
623 void xtensa_runstall(CPUXtensaState *env, bool runstall);
625 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
626 #define XTENSA_OPTION_ALL (~(uint64_t)0)
628 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
629 uint64_t opt)
631 return (config->options & opt) != 0;
634 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
636 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
639 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
641 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
642 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
643 level = env->config->excm_level;
645 return level;
648 static inline int xtensa_get_ring(const CPUXtensaState *env)
650 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
651 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
652 } else {
653 return 0;
657 static inline int xtensa_get_cring(const CPUXtensaState *env)
659 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
660 (env->sregs[PS] & PS_EXCM) == 0) {
661 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
662 } else {
663 return 0;
667 #ifndef CONFIG_USER_ONLY
668 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
669 uint32_t vaddr, int is_write, int mmu_idx,
670 uint32_t *paddr, uint32_t *page_size, unsigned *access);
671 void reset_mmu(CPUXtensaState *env);
672 void dump_mmu(CPUXtensaState *env);
674 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
676 return env->system_er;
678 #endif
680 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
682 return env->sregs[WINDOW_START] |
683 (env->sregs[WINDOW_START] << env->config->nareg / 4);
686 /* MMU modes definitions */
687 #define MMU_MODE0_SUFFIX _ring0
688 #define MMU_MODE1_SUFFIX _ring1
689 #define MMU_MODE2_SUFFIX _ring2
690 #define MMU_MODE3_SUFFIX _ring3
691 #define MMU_USER_IDX 3
693 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
695 return xtensa_get_cring(env);
698 #define XTENSA_TBFLAG_RING_MASK 0x3
699 #define XTENSA_TBFLAG_EXCM 0x4
700 #define XTENSA_TBFLAG_LITBASE 0x8
701 #define XTENSA_TBFLAG_DEBUG 0x10
702 #define XTENSA_TBFLAG_ICOUNT 0x20
703 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
704 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
705 #define XTENSA_TBFLAG_EXCEPTION 0x4000
706 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
707 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
708 #define XTENSA_TBFLAG_YIELD 0x20000
709 #define XTENSA_TBFLAG_CWOE 0x40000
710 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000
711 #define XTENSA_TBFLAG_CALLINC_SHIFT 19
713 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff
714 #define XTENSA_CSBASE_LEND_SHIFT 0
715 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
716 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
718 typedef CPUXtensaState CPUArchState;
719 typedef XtensaCPU ArchCPU;
721 #include "exec/cpu-all.h"
723 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
724 target_ulong *cs_base, uint32_t *flags)
726 CPUState *cs = env_cpu(env);
728 *pc = env->pc;
729 *cs_base = 0;
730 *flags = 0;
731 *flags |= xtensa_get_ring(env);
732 if (env->sregs[PS] & PS_EXCM) {
733 *flags |= XTENSA_TBFLAG_EXCM;
734 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
735 target_ulong lend_dist =
736 env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
739 * 0 in the csbase_lend field means that there may not be a loopback
740 * for any instruction that starts inside this page. Any other value
741 * means that an instruction that ends at this offset from the page
742 * start may loop back and will need loopback code to be generated.
744 * lend_dist is 0 when LEND points to the start of the page, but
745 * no instruction that starts inside this page may end at offset 0,
746 * so it's still correct.
748 * When an instruction ends at a page boundary it may only start in
749 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
750 * for the TB that contains this instruction.
752 if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
753 target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
755 *cs_base = lend_dist;
756 if (lbeg_off < 256) {
757 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
761 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
762 (env->sregs[LITBASE] & 1)) {
763 *flags |= XTENSA_TBFLAG_LITBASE;
765 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
766 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
767 *flags |= XTENSA_TBFLAG_DEBUG;
769 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
770 *flags |= XTENSA_TBFLAG_ICOUNT;
773 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
774 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
776 if (cs->singlestep_enabled && env->exception_taken) {
777 *flags |= XTENSA_TBFLAG_EXCEPTION;
779 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
780 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
781 uint32_t windowstart = xtensa_replicate_windowstart(env) >>
782 (env->sregs[WINDOW_BASE] + 1);
783 uint32_t w = ctz32(windowstart | 0x8);
785 *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
786 *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
787 PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
788 } else {
789 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
791 if (env->yield_needed) {
792 *flags |= XTENSA_TBFLAG_YIELD;
796 #endif