4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 /* CPUClass::reset() */
159 static void arm_cpu_reset(CPUState
*s
)
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(s
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
178 s
->halted
= cpu
->start_powered_off
;
180 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
181 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
184 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
185 /* 64 bit CPUs always start in 64 bit mode */
187 #if defined(CONFIG_USER_ONLY)
188 env
->pstate
= PSTATE_MODE_EL0t
;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
191 /* Enable all PAC keys. */
192 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
193 SCTLR_EnDA
| SCTLR_EnDB
);
194 /* Enable all PAC instructions */
195 env
->cp15
.hcr_el2
|= HCR_API
;
196 env
->cp15
.scr_el3
|= SCR_API
;
197 /* and to the FP/Neon instructions */
198 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
199 /* and to the SVE instructions */
200 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
201 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
202 /* with maximum vector length */
203 env
->vfp
.zcr_el
[1] = cpu
->sve_max_vq
- 1;
204 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
205 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
207 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
208 * turning on both here will produce smaller code and otherwise
209 * make no difference to the user-level emulation.
211 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
213 /* Reset into the highest available EL */
214 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
215 env
->pstate
= PSTATE_MODE_EL3h
;
216 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
217 env
->pstate
= PSTATE_MODE_EL2h
;
219 env
->pstate
= PSTATE_MODE_EL1h
;
221 env
->pc
= cpu
->rvbar
;
224 #if defined(CONFIG_USER_ONLY)
225 /* Userspace expects access to cp10 and cp11 for FP/Neon */
226 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
230 #if defined(CONFIG_USER_ONLY)
231 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
232 /* For user mode we must enable access to coprocessors */
233 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
234 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
235 env
->cp15
.c15_cpar
= 3;
236 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
237 env
->cp15
.c15_cpar
= 1;
242 * If the highest available EL is EL2, AArch32 will start in Hyp
243 * mode; otherwise it starts in SVC. Note that if we start in
244 * AArch64 then these values in the uncached_cpsr will be ignored.
246 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
247 !arm_feature(env
, ARM_FEATURE_EL3
)) {
248 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
250 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
252 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
254 if (arm_feature(env
, ARM_FEATURE_M
)) {
255 uint32_t initial_msp
; /* Loaded from 0x0 */
256 uint32_t initial_pc
; /* Loaded from 0x4 */
260 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
261 env
->v7m
.secure
= true;
263 /* This bit resets to 0 if security is supported, but 1 if
264 * it is not. The bit is not present in v7M, but we set it
265 * here so we can avoid having to make checks on it conditional
266 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
268 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
271 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
272 * that it resets to 1, so QEMU always does that rather than making
273 * it dependent on CPU model. In v8M it is RES1.
275 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
276 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
277 if (arm_feature(env
, ARM_FEATURE_V8
)) {
278 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
279 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
280 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
282 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
283 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
284 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
287 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
288 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
289 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
290 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
292 /* Unlike A/R profile, M profile defines the reset LR value */
293 env
->regs
[14] = 0xffffffff;
295 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
297 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
298 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
299 rom
= rom_ptr(vecbase
, 8);
301 /* Address zero is covered by ROM which hasn't yet been
302 * copied into physical memory.
304 initial_msp
= ldl_p(rom
);
305 initial_pc
= ldl_p(rom
+ 4);
307 /* Address zero not covered by a ROM blob, or the ROM blob
308 * is in non-modifiable memory and this is a second reset after
309 * it got copied into memory. In the latter case, rom_ptr
310 * will return a NULL pointer and we should use ldl_phys instead.
312 initial_msp
= ldl_phys(s
->as
, vecbase
);
313 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
316 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
317 env
->regs
[15] = initial_pc
& ~1;
318 env
->thumb
= initial_pc
& 1;
321 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
322 * executing as AArch32 then check if highvecs are enabled and
323 * adjust the PC accordingly.
325 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
326 env
->regs
[15] = 0xFFFF0000;
329 /* M profile requires that reset clears the exclusive monitor;
330 * A profile does not, but clearing it makes more sense than having it
331 * set with an exclusive access on address zero.
333 arm_clear_exclusive(env
);
335 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
338 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
339 if (cpu
->pmsav7_dregion
> 0) {
340 if (arm_feature(env
, ARM_FEATURE_V8
)) {
341 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
342 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
343 * cpu
->pmsav7_dregion
);
344 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
345 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
346 * cpu
->pmsav7_dregion
);
347 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
348 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
349 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
350 * cpu
->pmsav7_dregion
);
351 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
352 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
353 * cpu
->pmsav7_dregion
);
355 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
356 memset(env
->pmsav7
.drbar
, 0,
357 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
358 memset(env
->pmsav7
.drsr
, 0,
359 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
360 memset(env
->pmsav7
.dracr
, 0,
361 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
364 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
365 env
->pmsav7
.rnr
[M_REG_S
] = 0;
366 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
367 env
->pmsav8
.mair0
[M_REG_S
] = 0;
368 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
369 env
->pmsav8
.mair1
[M_REG_S
] = 0;
372 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
373 if (cpu
->sau_sregion
> 0) {
374 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
375 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
378 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
379 * the Cortex-M33 does.
384 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
385 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
386 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
387 set_float_detect_tininess(float_tininess_before_rounding
,
388 &env
->vfp
.fp_status
);
389 set_float_detect_tininess(float_tininess_before_rounding
,
390 &env
->vfp
.standard_fp_status
);
391 set_float_detect_tininess(float_tininess_before_rounding
,
392 &env
->vfp
.fp_status_f16
);
393 #ifndef CONFIG_USER_ONLY
395 kvm_arm_reset_vcpu(cpu
);
399 hw_breakpoint_update_all(cpu
);
400 hw_watchpoint_update_all(cpu
);
403 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
405 CPUClass
*cc
= CPU_GET_CLASS(cs
);
406 CPUARMState
*env
= cs
->env_ptr
;
407 uint32_t cur_el
= arm_current_el(env
);
408 bool secure
= arm_is_secure(env
);
413 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
415 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
416 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
417 cs
->exception_index
= excp_idx
;
418 env
->exception
.target_el
= target_el
;
419 cc
->do_interrupt(cs
);
423 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
425 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
426 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
427 cs
->exception_index
= excp_idx
;
428 env
->exception
.target_el
= target_el
;
429 cc
->do_interrupt(cs
);
433 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
434 excp_idx
= EXCP_VIRQ
;
436 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
437 cs
->exception_index
= excp_idx
;
438 env
->exception
.target_el
= target_el
;
439 cc
->do_interrupt(cs
);
443 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
444 excp_idx
= EXCP_VFIQ
;
446 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
447 cs
->exception_index
= excp_idx
;
448 env
->exception
.target_el
= target_el
;
449 cc
->do_interrupt(cs
);
457 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
458 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
460 CPUClass
*cc
= CPU_GET_CLASS(cs
);
461 ARMCPU
*cpu
= ARM_CPU(cs
);
462 CPUARMState
*env
= &cpu
->env
;
465 /* ARMv7-M interrupt masking works differently than -A or -R.
466 * There is no FIQ/IRQ distinction. Instead of I and F bits
467 * masking FIQ and IRQ interrupts, an exception is taken only
468 * if it is higher priority than the current execution priority
469 * (which depends on state like BASEPRI, FAULTMASK and the
470 * currently active exception).
472 if (interrupt_request
& CPU_INTERRUPT_HARD
473 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
474 cs
->exception_index
= EXCP_IRQ
;
475 cc
->do_interrupt(cs
);
482 void arm_cpu_update_virq(ARMCPU
*cpu
)
485 * Update the interrupt level for VIRQ, which is the logical OR of
486 * the HCR_EL2.VI bit and the input line level from the GIC.
488 CPUARMState
*env
= &cpu
->env
;
489 CPUState
*cs
= CPU(cpu
);
491 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
492 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
494 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
496 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
498 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
503 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
506 * Update the interrupt level for VFIQ, which is the logical OR of
507 * the HCR_EL2.VF bit and the input line level from the GIC.
509 CPUARMState
*env
= &cpu
->env
;
510 CPUState
*cs
= CPU(cpu
);
512 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
513 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
515 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
517 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
519 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
524 #ifndef CONFIG_USER_ONLY
525 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
527 ARMCPU
*cpu
= opaque
;
528 CPUARMState
*env
= &cpu
->env
;
529 CPUState
*cs
= CPU(cpu
);
530 static const int mask
[] = {
531 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
532 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
533 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
534 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
538 env
->irq_line_state
|= mask
[irq
];
540 env
->irq_line_state
&= ~mask
[irq
];
545 assert(arm_feature(env
, ARM_FEATURE_EL2
));
546 arm_cpu_update_virq(cpu
);
549 assert(arm_feature(env
, ARM_FEATURE_EL2
));
550 arm_cpu_update_vfiq(cpu
);
555 cpu_interrupt(cs
, mask
[irq
]);
557 cpu_reset_interrupt(cs
, mask
[irq
]);
561 g_assert_not_reached();
565 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
568 ARMCPU
*cpu
= opaque
;
569 CPUARMState
*env
= &cpu
->env
;
570 CPUState
*cs
= CPU(cpu
);
571 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
572 uint32_t linestate_bit
;
576 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
577 linestate_bit
= CPU_INTERRUPT_HARD
;
580 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
581 linestate_bit
= CPU_INTERRUPT_FIQ
;
584 g_assert_not_reached();
588 env
->irq_line_state
|= linestate_bit
;
590 env
->irq_line_state
&= ~linestate_bit
;
593 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
594 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
598 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
600 ARMCPU
*cpu
= ARM_CPU(cs
);
601 CPUARMState
*env
= &cpu
->env
;
603 cpu_synchronize_state(cs
);
604 return arm_cpu_data_is_big_endian(env
);
609 static inline void set_feature(CPUARMState
*env
, int feature
)
611 env
->features
|= 1ULL << feature
;
614 static inline void unset_feature(CPUARMState
*env
, int feature
)
616 env
->features
&= ~(1ULL << feature
);
620 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
622 return print_insn_arm(pc
| 1, info
);
625 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
627 ARMCPU
*ac
= ARM_CPU(cpu
);
628 CPUARMState
*env
= &ac
->env
;
632 /* We might not be compiled with the A64 disassembler
633 * because it needs a C++ compiler. Leave print_insn
634 * unset in this case to use the caller default behaviour.
636 #if defined(CONFIG_ARM_A64_DIS)
637 info
->print_insn
= print_insn_arm_a64
;
639 info
->cap_arch
= CS_ARCH_ARM64
;
640 info
->cap_insn_unit
= 4;
641 info
->cap_insn_split
= 4;
645 info
->print_insn
= print_insn_thumb1
;
646 info
->cap_insn_unit
= 2;
647 info
->cap_insn_split
= 4;
648 cap_mode
= CS_MODE_THUMB
;
650 info
->print_insn
= print_insn_arm
;
651 info
->cap_insn_unit
= 4;
652 info
->cap_insn_split
= 4;
653 cap_mode
= CS_MODE_ARM
;
655 if (arm_feature(env
, ARM_FEATURE_V8
)) {
656 cap_mode
|= CS_MODE_V8
;
658 if (arm_feature(env
, ARM_FEATURE_M
)) {
659 cap_mode
|= CS_MODE_MCLASS
;
661 info
->cap_arch
= CS_ARCH_ARM
;
662 info
->cap_mode
= cap_mode
;
665 sctlr_b
= arm_sctlr_b(env
);
666 if (bswap_code(sctlr_b
)) {
667 #ifdef TARGET_WORDS_BIGENDIAN
668 info
->endian
= BFD_ENDIAN_LITTLE
;
670 info
->endian
= BFD_ENDIAN_BIG
;
673 info
->flags
&= ~INSN_ARM_BE32
;
674 #ifndef CONFIG_USER_ONLY
676 info
->flags
|= INSN_ARM_BE32
;
681 #ifdef TARGET_AARCH64
683 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
685 ARMCPU
*cpu
= ARM_CPU(cs
);
686 CPUARMState
*env
= &cpu
->env
;
687 uint32_t psr
= pstate_read(env
);
689 int el
= arm_current_el(env
);
690 const char *ns_status
;
692 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
693 for (i
= 0; i
< 32; i
++) {
695 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
697 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
698 (i
+ 2) % 3 ? " " : "\n");
702 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
703 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
707 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
709 psr
& PSTATE_N
? 'N' : '-',
710 psr
& PSTATE_Z
? 'Z' : '-',
711 psr
& PSTATE_C
? 'C' : '-',
712 psr
& PSTATE_V
? 'V' : '-',
715 psr
& PSTATE_SP
? 'h' : 't');
717 if (cpu_isar_feature(aa64_bti
, cpu
)) {
718 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
720 if (!(flags
& CPU_DUMP_FPU
)) {
721 qemu_fprintf(f
, "\n");
724 if (fp_exception_el(env
, el
) != 0) {
725 qemu_fprintf(f
, " FPU disabled\n");
728 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
729 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
731 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
732 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
734 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
736 if (i
== FFR_PRED_NUM
) {
737 qemu_fprintf(f
, "FFR=");
738 /* It's last, so end the line. */
741 qemu_fprintf(f
, "P%02d=", i
);
754 /* More than one quadword per predicate. */
759 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
761 if (j
* 4 + 4 <= zcr_len
+ 1) {
764 digits
= (zcr_len
% 4 + 1) * 4;
766 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
767 env
->vfp
.pregs
[i
].p
[j
],
768 j
? ":" : eol
? "\n" : " ");
772 for (i
= 0; i
< 32; i
++) {
774 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
775 i
, env
->vfp
.zregs
[i
].d
[1],
776 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
777 } else if (zcr_len
== 1) {
778 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
779 ":%016" PRIx64
":%016" PRIx64
"\n",
780 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
781 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
783 for (j
= zcr_len
; j
>= 0; j
--) {
784 bool odd
= (zcr_len
- j
) % 2 != 0;
786 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
789 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
791 qemu_fprintf(f
, " [%x]=", j
);
794 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
795 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
796 env
->vfp
.zregs
[i
].d
[j
* 2],
797 odd
|| j
== 0 ? "\n" : ":");
802 for (i
= 0; i
< 32; i
++) {
803 uint64_t *q
= aa64_vfp_qreg(env
, i
);
804 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
805 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
812 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
814 g_assert_not_reached();
819 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
821 ARMCPU
*cpu
= ARM_CPU(cs
);
822 CPUARMState
*env
= &cpu
->env
;
826 aarch64_cpu_dump_state(cs
, f
, flags
);
830 for (i
= 0; i
< 16; i
++) {
831 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
833 qemu_fprintf(f
, "\n");
835 qemu_fprintf(f
, " ");
839 if (arm_feature(env
, ARM_FEATURE_M
)) {
840 uint32_t xpsr
= xpsr_read(env
);
842 const char *ns_status
= "";
844 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
845 ns_status
= env
->v7m
.secure
? "S " : "NS ";
848 if (xpsr
& XPSR_EXCP
) {
851 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
852 mode
= "unpriv-thread";
854 mode
= "priv-thread";
858 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
860 xpsr
& XPSR_N
? 'N' : '-',
861 xpsr
& XPSR_Z
? 'Z' : '-',
862 xpsr
& XPSR_C
? 'C' : '-',
863 xpsr
& XPSR_V
? 'V' : '-',
864 xpsr
& XPSR_T
? 'T' : 'A',
868 uint32_t psr
= cpsr_read(env
);
869 const char *ns_status
= "";
871 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
872 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
873 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
876 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
878 psr
& CPSR_N
? 'N' : '-',
879 psr
& CPSR_Z
? 'Z' : '-',
880 psr
& CPSR_C
? 'C' : '-',
881 psr
& CPSR_V
? 'V' : '-',
882 psr
& CPSR_T
? 'T' : 'A',
884 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
887 if (flags
& CPU_DUMP_FPU
) {
889 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
892 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
895 for (i
= 0; i
< numvfpregs
; i
++) {
896 uint64_t v
= *aa32_vfp_dreg(env
, i
);
897 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
899 i
* 2 + 1, (uint32_t)(v
>> 32),
902 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
906 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
908 uint32_t Aff1
= idx
/ clustersz
;
909 uint32_t Aff0
= idx
% clustersz
;
910 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
913 static void cpreg_hashtable_data_destroy(gpointer data
)
916 * Destroy function for cpu->cp_regs hashtable data entries.
917 * We must free the name string because it was g_strdup()ed in
918 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
919 * from r->name because we know we definitely allocated it.
921 ARMCPRegInfo
*r
= data
;
923 g_free((void *)r
->name
);
927 static void arm_cpu_initfn(Object
*obj
)
929 ARMCPU
*cpu
= ARM_CPU(obj
);
931 cpu_set_cpustate_pointers(cpu
);
932 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
933 g_free
, cpreg_hashtable_data_destroy
);
935 QLIST_INIT(&cpu
->pre_el_change_hooks
);
936 QLIST_INIT(&cpu
->el_change_hooks
);
938 #ifndef CONFIG_USER_ONLY
939 /* Our inbound IRQ and FIQ lines */
941 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
942 * the same interface as non-KVM CPUs.
944 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
946 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
949 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
950 ARRAY_SIZE(cpu
->gt_timer_outputs
));
952 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
953 "gicv3-maintenance-interrupt", 1);
954 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
958 /* DTB consumers generally don't in fact care what the 'compatible'
959 * string is, so always provide some string and trust that a hypothetical
960 * picky DTB consumer will also provide a helpful error message.
962 cpu
->dtb_compatible
= "qemu,unknown";
963 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
964 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
967 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
971 static Property arm_cpu_reset_cbar_property
=
972 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
974 static Property arm_cpu_reset_hivecs_property
=
975 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
977 static Property arm_cpu_rvbar_property
=
978 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
980 static Property arm_cpu_has_el2_property
=
981 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
983 static Property arm_cpu_has_el3_property
=
984 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
986 static Property arm_cpu_cfgend_property
=
987 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
989 /* use property name "pmu" to match other archs and virt tools */
990 static Property arm_cpu_has_pmu_property
=
991 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
993 static Property arm_cpu_has_vfp_property
=
994 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
996 static Property arm_cpu_has_neon_property
=
997 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
999 static Property arm_cpu_has_dsp_property
=
1000 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1002 static Property arm_cpu_has_mpu_property
=
1003 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1005 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1006 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1007 * the right value for that particular CPU type, and we don't want
1008 * to override that with an incorrect constant value.
1010 static Property arm_cpu_pmsav7_dregion_property
=
1011 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1013 qdev_prop_uint32
, uint32_t);
1015 static void arm_get_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1016 void *opaque
, Error
**errp
)
1018 ARMCPU
*cpu
= ARM_CPU(obj
);
1020 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1023 static void arm_set_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1024 void *opaque
, Error
**errp
)
1026 ARMCPU
*cpu
= ARM_CPU(obj
);
1028 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1031 void arm_cpu_post_init(Object
*obj
)
1033 ARMCPU
*cpu
= ARM_CPU(obj
);
1035 /* M profile implies PMSA. We have to do this here rather than
1036 * in realize with the other feature-implication checks because
1037 * we look at the PMSA bit to see if we should add some properties.
1039 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1040 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1042 /* Similarly for the VFP feature bits */
1043 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP4
)) {
1044 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1046 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP3
)) {
1047 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1050 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1051 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1052 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
1056 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1057 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
1061 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1062 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
1066 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1067 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1068 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1070 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
1073 #ifndef CONFIG_USER_ONLY
1074 object_property_add_link(obj
, "secure-memory",
1076 (Object
**)&cpu
->secure_memory
,
1077 qdev_prop_allow_set_link_before_realize
,
1078 OBJ_PROP_LINK_STRONG
,
1083 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1084 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
1088 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1089 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
1094 * Allow user to turn off VFP and Neon support, but only for TCG --
1095 * KVM does not currently allow us to lie to the guest about its
1096 * ID/feature registers, so the guest always sees what the host has.
1098 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1099 cpu
->has_vfp
= true;
1100 if (!kvm_enabled()) {
1101 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
,
1106 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1107 cpu
->has_neon
= true;
1108 if (!kvm_enabled()) {
1109 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
,
1114 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1115 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1116 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
,
1120 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1121 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
1123 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1124 qdev_property_add_static(DEVICE(obj
),
1125 &arm_cpu_pmsav7_dregion_property
,
1130 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1131 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1132 qdev_prop_allow_set_link_before_realize
,
1133 OBJ_PROP_LINK_STRONG
,
1136 * M profile: initial value of the Secure VTOR. We can't just use
1137 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1138 * the property to be set after realize.
1140 object_property_add(obj
, "init-svtor", "uint32",
1141 arm_get_init_svtor
, arm_set_init_svtor
,
1142 NULL
, NULL
, &error_abort
);
1145 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
1149 static void arm_cpu_finalizefn(Object
*obj
)
1151 ARMCPU
*cpu
= ARM_CPU(obj
);
1152 ARMELChangeHook
*hook
, *next
;
1154 g_hash_table_destroy(cpu
->cp_regs
);
1156 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1157 QLIST_REMOVE(hook
, node
);
1160 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1161 QLIST_REMOVE(hook
, node
);
1164 #ifndef CONFIG_USER_ONLY
1165 if (cpu
->pmu_timer
) {
1166 timer_del(cpu
->pmu_timer
);
1167 timer_deinit(cpu
->pmu_timer
);
1168 timer_free(cpu
->pmu_timer
);
1173 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1175 CPUState
*cs
= CPU(dev
);
1176 ARMCPU
*cpu
= ARM_CPU(dev
);
1177 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1178 CPUARMState
*env
= &cpu
->env
;
1180 Error
*local_err
= NULL
;
1181 bool no_aa32
= false;
1183 /* If we needed to query the host kernel for the CPU features
1184 * then it's possible that might have failed in the initfn, but
1185 * this is the first point where we can report it.
1187 if (cpu
->host_cpu_probe_failed
) {
1188 if (!kvm_enabled()) {
1189 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1191 error_setg(errp
, "Failed to retrieve host CPU features");
1196 #ifndef CONFIG_USER_ONLY
1197 /* The NVIC and M-profile CPU are two halves of a single piece of
1198 * hardware; trying to use one without the other is a command line
1199 * error and will result in segfaults if not caught here.
1201 if (arm_feature(env
, ARM_FEATURE_M
)) {
1203 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1208 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1213 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
1214 arm_gt_ptimer_cb
, cpu
);
1215 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
1216 arm_gt_vtimer_cb
, cpu
);
1217 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
1218 arm_gt_htimer_cb
, cpu
);
1219 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
1220 arm_gt_stimer_cb
, cpu
);
1223 cpu_exec_realizefn(cs
, &local_err
);
1224 if (local_err
!= NULL
) {
1225 error_propagate(errp
, local_err
);
1229 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1230 cpu
->has_vfp
!= cpu
->has_neon
) {
1232 * This is an architectural requirement for AArch64; AArch32 is
1233 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1236 "AArch64 CPUs must have both VFP and Neon or neither");
1240 if (!cpu
->has_vfp
) {
1244 unset_feature(env
, ARM_FEATURE_VFP
);
1245 unset_feature(env
, ARM_FEATURE_VFP3
);
1246 unset_feature(env
, ARM_FEATURE_VFP4
);
1248 t
= cpu
->isar
.id_aa64isar1
;
1249 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1250 cpu
->isar
.id_aa64isar1
= t
;
1252 t
= cpu
->isar
.id_aa64pfr0
;
1253 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1254 cpu
->isar
.id_aa64pfr0
= t
;
1256 u
= cpu
->isar
.id_isar6
;
1257 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1258 cpu
->isar
.id_isar6
= u
;
1260 u
= cpu
->isar
.mvfr0
;
1261 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1262 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1263 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1264 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1265 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1266 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1267 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1268 cpu
->isar
.mvfr0
= u
;
1270 u
= cpu
->isar
.mvfr1
;
1271 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1272 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1273 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1274 cpu
->isar
.mvfr1
= u
;
1276 u
= cpu
->isar
.mvfr2
;
1277 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1278 cpu
->isar
.mvfr2
= u
;
1281 if (!cpu
->has_neon
) {
1285 unset_feature(env
, ARM_FEATURE_NEON
);
1287 t
= cpu
->isar
.id_aa64isar0
;
1288 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1289 cpu
->isar
.id_aa64isar0
= t
;
1291 t
= cpu
->isar
.id_aa64isar1
;
1292 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1293 cpu
->isar
.id_aa64isar1
= t
;
1295 t
= cpu
->isar
.id_aa64pfr0
;
1296 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1297 cpu
->isar
.id_aa64pfr0
= t
;
1299 u
= cpu
->isar
.id_isar5
;
1300 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1301 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1302 cpu
->isar
.id_isar5
= u
;
1304 u
= cpu
->isar
.id_isar6
;
1305 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1306 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1307 cpu
->isar
.id_isar6
= u
;
1309 u
= cpu
->isar
.mvfr1
;
1310 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1311 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1312 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1313 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1314 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1315 cpu
->isar
.mvfr1
= u
;
1317 u
= cpu
->isar
.mvfr2
;
1318 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1319 cpu
->isar
.mvfr2
= u
;
1322 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1326 t
= cpu
->isar
.id_aa64isar0
;
1327 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1328 cpu
->isar
.id_aa64isar0
= t
;
1330 t
= cpu
->isar
.id_aa64isar1
;
1331 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1332 cpu
->isar
.id_aa64isar1
= t
;
1334 u
= cpu
->isar
.mvfr0
;
1335 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1336 cpu
->isar
.mvfr0
= u
;
1339 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1342 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1344 u
= cpu
->isar
.id_isar1
;
1345 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1346 cpu
->isar
.id_isar1
= u
;
1348 u
= cpu
->isar
.id_isar2
;
1349 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1350 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1351 cpu
->isar
.id_isar2
= u
;
1353 u
= cpu
->isar
.id_isar3
;
1354 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1355 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1356 cpu
->isar
.id_isar3
= u
;
1359 /* Some features automatically imply others: */
1360 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1361 if (arm_feature(env
, ARM_FEATURE_M
)) {
1362 set_feature(env
, ARM_FEATURE_V7
);
1364 set_feature(env
, ARM_FEATURE_V7VE
);
1369 * There exist AArch64 cpus without AArch32 support. When KVM
1370 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1371 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1373 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1374 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1377 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1378 /* v7 Virtualization Extensions. In real hardware this implies
1379 * EL2 and also the presence of the Security Extensions.
1380 * For QEMU, for backwards-compatibility we implement some
1381 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1382 * include the various other features that V7VE implies.
1383 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1384 * Security Extensions is ARM_FEATURE_EL3.
1386 assert(no_aa32
|| cpu_isar_feature(arm_div
, cpu
));
1387 set_feature(env
, ARM_FEATURE_LPAE
);
1388 set_feature(env
, ARM_FEATURE_V7
);
1390 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1391 set_feature(env
, ARM_FEATURE_VAPA
);
1392 set_feature(env
, ARM_FEATURE_THUMB2
);
1393 set_feature(env
, ARM_FEATURE_MPIDR
);
1394 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1395 set_feature(env
, ARM_FEATURE_V6K
);
1397 set_feature(env
, ARM_FEATURE_V6
);
1400 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1401 * non-EL3 configs. This is needed by some legacy boards.
1403 set_feature(env
, ARM_FEATURE_VBAR
);
1405 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1406 set_feature(env
, ARM_FEATURE_V6
);
1407 set_feature(env
, ARM_FEATURE_MVFR
);
1409 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1410 set_feature(env
, ARM_FEATURE_V5
);
1411 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1412 assert(no_aa32
|| cpu_isar_feature(jazelle
, cpu
));
1413 set_feature(env
, ARM_FEATURE_AUXCR
);
1416 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1417 set_feature(env
, ARM_FEATURE_V4T
);
1419 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1420 set_feature(env
, ARM_FEATURE_V7MP
);
1421 set_feature(env
, ARM_FEATURE_PXN
);
1423 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1424 set_feature(env
, ARM_FEATURE_CBAR
);
1426 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1427 !arm_feature(env
, ARM_FEATURE_M
)) {
1428 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1432 * We rely on no XScale CPU having VFP so we can use the same bits in the
1433 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1435 assert(!(arm_feature(env
, ARM_FEATURE_VFP
) &&
1436 arm_feature(env
, ARM_FEATURE_XSCALE
)));
1438 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1439 !arm_feature(env
, ARM_FEATURE_M
) &&
1440 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1441 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1446 /* For CPUs which might have tiny 1K pages, or which have an
1447 * MPU and might have small region sizes, stick with 1K pages.
1451 if (!set_preferred_target_page_bits(pagebits
)) {
1452 /* This can only ever happen for hotplugging a CPU, or if
1453 * the board code incorrectly creates a CPU which it has
1454 * promised via minimum_page_size that it will not.
1456 error_setg(errp
, "This CPU requires a smaller page size than the "
1461 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1462 * We don't support setting cluster ID ([16..23]) (known as Aff2
1463 * in later ARM ARM versions), or any of the higher affinity level fields,
1464 * so these bits always RAZ.
1466 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1467 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1468 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1471 if (cpu
->reset_hivecs
) {
1472 cpu
->reset_sctlr
|= (1 << 13);
1476 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1477 cpu
->reset_sctlr
|= SCTLR_EE
;
1479 cpu
->reset_sctlr
|= SCTLR_B
;
1483 if (!cpu
->has_el3
) {
1484 /* If the has_el3 CPU property is disabled then we need to disable the
1487 unset_feature(env
, ARM_FEATURE_EL3
);
1489 /* Disable the security extension feature bits in the processor feature
1490 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1492 cpu
->id_pfr1
&= ~0xf0;
1493 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1496 if (!cpu
->has_el2
) {
1497 unset_feature(env
, ARM_FEATURE_EL2
);
1500 if (!cpu
->has_pmu
) {
1501 unset_feature(env
, ARM_FEATURE_PMU
);
1503 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1506 if (!kvm_enabled()) {
1507 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1508 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1511 #ifndef CONFIG_USER_ONLY
1512 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1516 cpu
->id_aa64dfr0
&= ~0xf00;
1517 cpu
->id_dfr0
&= ~(0xf << 24);
1522 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1523 /* Disable the hypervisor feature bits in the processor feature
1524 * registers if we don't have EL2. These are id_pfr1[15:12] and
1525 * id_aa64pfr0_el1[11:8].
1527 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1528 cpu
->id_pfr1
&= ~0xf000;
1531 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1532 * to false or by setting pmsav7-dregion to 0.
1534 if (!cpu
->has_mpu
) {
1535 cpu
->pmsav7_dregion
= 0;
1537 if (cpu
->pmsav7_dregion
== 0) {
1538 cpu
->has_mpu
= false;
1541 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1542 arm_feature(env
, ARM_FEATURE_V7
)) {
1543 uint32_t nr
= cpu
->pmsav7_dregion
;
1546 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1551 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1553 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1554 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1555 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1556 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1557 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1560 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1561 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1562 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1567 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1568 uint32_t nr
= cpu
->sau_sregion
;
1571 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1576 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1577 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1581 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1582 set_feature(env
, ARM_FEATURE_VBAR
);
1585 register_cp_regs_for_features(cpu
);
1586 arm_cpu_register_gdb_regs_for_features(cpu
);
1588 init_cpreg_list(cpu
);
1590 #ifndef CONFIG_USER_ONLY
1591 MachineState
*ms
= MACHINE(qdev_get_machine());
1592 unsigned int smp_cpus
= ms
->smp
.cpus
;
1594 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1597 if (!cpu
->secure_memory
) {
1598 cpu
->secure_memory
= cs
->memory
;
1600 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1601 cpu
->secure_memory
);
1605 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1607 /* No core_count specified, default to smp_cpus. */
1608 if (cpu
->core_count
== -1) {
1609 cpu
->core_count
= smp_cpus
;
1616 acc
->parent_realize(dev
, errp
);
1619 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1624 const char *cpunamestr
;
1626 cpuname
= g_strsplit(cpu_model
, ",", 1);
1627 cpunamestr
= cpuname
[0];
1628 #ifdef CONFIG_USER_ONLY
1629 /* For backwards compatibility usermode emulation allows "-cpu any",
1630 * which has the same semantics as "-cpu max".
1632 if (!strcmp(cpunamestr
, "any")) {
1636 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1637 oc
= object_class_by_name(typename
);
1638 g_strfreev(cpuname
);
1640 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1641 object_class_is_abstract(oc
)) {
1647 /* CPU models. These are not needed for the AArch64 linux-user build. */
1648 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1650 static void arm926_initfn(Object
*obj
)
1652 ARMCPU
*cpu
= ARM_CPU(obj
);
1654 cpu
->dtb_compatible
= "arm,arm926";
1655 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1656 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1657 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1658 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1659 cpu
->midr
= 0x41069265;
1660 cpu
->reset_fpsid
= 0x41011090;
1661 cpu
->ctr
= 0x1dd20d2;
1662 cpu
->reset_sctlr
= 0x00090078;
1665 * ARMv5 does not have the ID_ISAR registers, but we can still
1666 * set the field to indicate Jazelle support within QEMU.
1668 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1670 * Similarly, we need to set MVFR0 fields to enable double precision
1671 * and short vector support even though ARMv5 doesn't have this register.
1673 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1674 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1677 static void arm946_initfn(Object
*obj
)
1679 ARMCPU
*cpu
= ARM_CPU(obj
);
1681 cpu
->dtb_compatible
= "arm,arm946";
1682 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1683 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1684 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1685 cpu
->midr
= 0x41059461;
1686 cpu
->ctr
= 0x0f004006;
1687 cpu
->reset_sctlr
= 0x00000078;
1690 static void arm1026_initfn(Object
*obj
)
1692 ARMCPU
*cpu
= ARM_CPU(obj
);
1694 cpu
->dtb_compatible
= "arm,arm1026";
1695 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1696 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1697 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1698 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1699 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1700 cpu
->midr
= 0x4106a262;
1701 cpu
->reset_fpsid
= 0x410110a0;
1702 cpu
->ctr
= 0x1dd20d2;
1703 cpu
->reset_sctlr
= 0x00090078;
1704 cpu
->reset_auxcr
= 1;
1707 * ARMv5 does not have the ID_ISAR registers, but we can still
1708 * set the field to indicate Jazelle support within QEMU.
1710 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1712 * Similarly, we need to set MVFR0 fields to enable double precision
1713 * and short vector support even though ARMv5 doesn't have this register.
1715 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1716 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1719 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1720 ARMCPRegInfo ifar
= {
1721 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1723 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1726 define_one_arm_cp_reg(cpu
, &ifar
);
1730 static void arm1136_r2_initfn(Object
*obj
)
1732 ARMCPU
*cpu
= ARM_CPU(obj
);
1733 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1734 * older core than plain "arm1136". In particular this does not
1735 * have the v6K features.
1736 * These ID register values are correct for 1136 but may be wrong
1737 * for 1136_r2 (in particular r0p2 does not actually implement most
1738 * of the ID registers).
1741 cpu
->dtb_compatible
= "arm,arm1136";
1742 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1743 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1744 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1745 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1746 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1747 cpu
->midr
= 0x4107b362;
1748 cpu
->reset_fpsid
= 0x410120b4;
1749 cpu
->isar
.mvfr0
= 0x11111111;
1750 cpu
->isar
.mvfr1
= 0x00000000;
1751 cpu
->ctr
= 0x1dd20d2;
1752 cpu
->reset_sctlr
= 0x00050078;
1753 cpu
->id_pfr0
= 0x111;
1757 cpu
->id_mmfr0
= 0x01130003;
1758 cpu
->id_mmfr1
= 0x10030302;
1759 cpu
->id_mmfr2
= 0x01222110;
1760 cpu
->isar
.id_isar0
= 0x00140011;
1761 cpu
->isar
.id_isar1
= 0x12002111;
1762 cpu
->isar
.id_isar2
= 0x11231111;
1763 cpu
->isar
.id_isar3
= 0x01102131;
1764 cpu
->isar
.id_isar4
= 0x141;
1765 cpu
->reset_auxcr
= 7;
1768 static void arm1136_initfn(Object
*obj
)
1770 ARMCPU
*cpu
= ARM_CPU(obj
);
1772 cpu
->dtb_compatible
= "arm,arm1136";
1773 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1774 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1775 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1776 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1777 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1778 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1779 cpu
->midr
= 0x4117b363;
1780 cpu
->reset_fpsid
= 0x410120b4;
1781 cpu
->isar
.mvfr0
= 0x11111111;
1782 cpu
->isar
.mvfr1
= 0x00000000;
1783 cpu
->ctr
= 0x1dd20d2;
1784 cpu
->reset_sctlr
= 0x00050078;
1785 cpu
->id_pfr0
= 0x111;
1789 cpu
->id_mmfr0
= 0x01130003;
1790 cpu
->id_mmfr1
= 0x10030302;
1791 cpu
->id_mmfr2
= 0x01222110;
1792 cpu
->isar
.id_isar0
= 0x00140011;
1793 cpu
->isar
.id_isar1
= 0x12002111;
1794 cpu
->isar
.id_isar2
= 0x11231111;
1795 cpu
->isar
.id_isar3
= 0x01102131;
1796 cpu
->isar
.id_isar4
= 0x141;
1797 cpu
->reset_auxcr
= 7;
1800 static void arm1176_initfn(Object
*obj
)
1802 ARMCPU
*cpu
= ARM_CPU(obj
);
1804 cpu
->dtb_compatible
= "arm,arm1176";
1805 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1806 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1807 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1808 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1809 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1810 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1811 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1812 cpu
->midr
= 0x410fb767;
1813 cpu
->reset_fpsid
= 0x410120b5;
1814 cpu
->isar
.mvfr0
= 0x11111111;
1815 cpu
->isar
.mvfr1
= 0x00000000;
1816 cpu
->ctr
= 0x1dd20d2;
1817 cpu
->reset_sctlr
= 0x00050078;
1818 cpu
->id_pfr0
= 0x111;
1819 cpu
->id_pfr1
= 0x11;
1820 cpu
->id_dfr0
= 0x33;
1822 cpu
->id_mmfr0
= 0x01130003;
1823 cpu
->id_mmfr1
= 0x10030302;
1824 cpu
->id_mmfr2
= 0x01222100;
1825 cpu
->isar
.id_isar0
= 0x0140011;
1826 cpu
->isar
.id_isar1
= 0x12002111;
1827 cpu
->isar
.id_isar2
= 0x11231121;
1828 cpu
->isar
.id_isar3
= 0x01102131;
1829 cpu
->isar
.id_isar4
= 0x01141;
1830 cpu
->reset_auxcr
= 7;
1833 static void arm11mpcore_initfn(Object
*obj
)
1835 ARMCPU
*cpu
= ARM_CPU(obj
);
1837 cpu
->dtb_compatible
= "arm,arm11mpcore";
1838 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1839 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1840 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1841 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1842 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1843 cpu
->midr
= 0x410fb022;
1844 cpu
->reset_fpsid
= 0x410120b4;
1845 cpu
->isar
.mvfr0
= 0x11111111;
1846 cpu
->isar
.mvfr1
= 0x00000000;
1847 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1848 cpu
->id_pfr0
= 0x111;
1852 cpu
->id_mmfr0
= 0x01100103;
1853 cpu
->id_mmfr1
= 0x10020302;
1854 cpu
->id_mmfr2
= 0x01222000;
1855 cpu
->isar
.id_isar0
= 0x00100011;
1856 cpu
->isar
.id_isar1
= 0x12002111;
1857 cpu
->isar
.id_isar2
= 0x11221011;
1858 cpu
->isar
.id_isar3
= 0x01102131;
1859 cpu
->isar
.id_isar4
= 0x141;
1860 cpu
->reset_auxcr
= 1;
1863 static void cortex_m0_initfn(Object
*obj
)
1865 ARMCPU
*cpu
= ARM_CPU(obj
);
1866 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1867 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1869 cpu
->midr
= 0x410cc200;
1872 static void cortex_m3_initfn(Object
*obj
)
1874 ARMCPU
*cpu
= ARM_CPU(obj
);
1875 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1876 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1877 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1878 cpu
->midr
= 0x410fc231;
1879 cpu
->pmsav7_dregion
= 8;
1880 cpu
->id_pfr0
= 0x00000030;
1881 cpu
->id_pfr1
= 0x00000200;
1882 cpu
->id_dfr0
= 0x00100000;
1883 cpu
->id_afr0
= 0x00000000;
1884 cpu
->id_mmfr0
= 0x00000030;
1885 cpu
->id_mmfr1
= 0x00000000;
1886 cpu
->id_mmfr2
= 0x00000000;
1887 cpu
->id_mmfr3
= 0x00000000;
1888 cpu
->isar
.id_isar0
= 0x01141110;
1889 cpu
->isar
.id_isar1
= 0x02111000;
1890 cpu
->isar
.id_isar2
= 0x21112231;
1891 cpu
->isar
.id_isar3
= 0x01111110;
1892 cpu
->isar
.id_isar4
= 0x01310102;
1893 cpu
->isar
.id_isar5
= 0x00000000;
1894 cpu
->isar
.id_isar6
= 0x00000000;
1897 static void cortex_m4_initfn(Object
*obj
)
1899 ARMCPU
*cpu
= ARM_CPU(obj
);
1901 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1902 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1903 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1904 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1905 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1906 cpu
->midr
= 0x410fc240; /* r0p0 */
1907 cpu
->pmsav7_dregion
= 8;
1908 cpu
->isar
.mvfr0
= 0x10110021;
1909 cpu
->isar
.mvfr1
= 0x11000011;
1910 cpu
->isar
.mvfr2
= 0x00000000;
1911 cpu
->id_pfr0
= 0x00000030;
1912 cpu
->id_pfr1
= 0x00000200;
1913 cpu
->id_dfr0
= 0x00100000;
1914 cpu
->id_afr0
= 0x00000000;
1915 cpu
->id_mmfr0
= 0x00000030;
1916 cpu
->id_mmfr1
= 0x00000000;
1917 cpu
->id_mmfr2
= 0x00000000;
1918 cpu
->id_mmfr3
= 0x00000000;
1919 cpu
->isar
.id_isar0
= 0x01141110;
1920 cpu
->isar
.id_isar1
= 0x02111000;
1921 cpu
->isar
.id_isar2
= 0x21112231;
1922 cpu
->isar
.id_isar3
= 0x01111110;
1923 cpu
->isar
.id_isar4
= 0x01310102;
1924 cpu
->isar
.id_isar5
= 0x00000000;
1925 cpu
->isar
.id_isar6
= 0x00000000;
1928 static void cortex_m33_initfn(Object
*obj
)
1930 ARMCPU
*cpu
= ARM_CPU(obj
);
1932 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1933 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1934 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1935 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
1936 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1937 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1938 cpu
->midr
= 0x410fd213; /* r0p3 */
1939 cpu
->pmsav7_dregion
= 16;
1940 cpu
->sau_sregion
= 8;
1941 cpu
->isar
.mvfr0
= 0x10110021;
1942 cpu
->isar
.mvfr1
= 0x11000011;
1943 cpu
->isar
.mvfr2
= 0x00000040;
1944 cpu
->id_pfr0
= 0x00000030;
1945 cpu
->id_pfr1
= 0x00000210;
1946 cpu
->id_dfr0
= 0x00200000;
1947 cpu
->id_afr0
= 0x00000000;
1948 cpu
->id_mmfr0
= 0x00101F40;
1949 cpu
->id_mmfr1
= 0x00000000;
1950 cpu
->id_mmfr2
= 0x01000000;
1951 cpu
->id_mmfr3
= 0x00000000;
1952 cpu
->isar
.id_isar0
= 0x01101110;
1953 cpu
->isar
.id_isar1
= 0x02212000;
1954 cpu
->isar
.id_isar2
= 0x20232232;
1955 cpu
->isar
.id_isar3
= 0x01111131;
1956 cpu
->isar
.id_isar4
= 0x01310132;
1957 cpu
->isar
.id_isar5
= 0x00000000;
1958 cpu
->isar
.id_isar6
= 0x00000000;
1959 cpu
->clidr
= 0x00000000;
1960 cpu
->ctr
= 0x8000c000;
1963 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1965 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1966 CPUClass
*cc
= CPU_CLASS(oc
);
1969 #ifndef CONFIG_USER_ONLY
1970 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1973 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1976 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1977 /* Dummy the TCM region regs for the moment */
1978 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1979 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1980 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1981 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1982 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1983 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1987 static void cortex_r5_initfn(Object
*obj
)
1989 ARMCPU
*cpu
= ARM_CPU(obj
);
1991 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1992 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1993 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1994 cpu
->midr
= 0x411fc153; /* r1p3 */
1995 cpu
->id_pfr0
= 0x0131;
1996 cpu
->id_pfr1
= 0x001;
1997 cpu
->id_dfr0
= 0x010400;
1999 cpu
->id_mmfr0
= 0x0210030;
2000 cpu
->id_mmfr1
= 0x00000000;
2001 cpu
->id_mmfr2
= 0x01200000;
2002 cpu
->id_mmfr3
= 0x0211;
2003 cpu
->isar
.id_isar0
= 0x02101111;
2004 cpu
->isar
.id_isar1
= 0x13112111;
2005 cpu
->isar
.id_isar2
= 0x21232141;
2006 cpu
->isar
.id_isar3
= 0x01112131;
2007 cpu
->isar
.id_isar4
= 0x0010142;
2008 cpu
->isar
.id_isar5
= 0x0;
2009 cpu
->isar
.id_isar6
= 0x0;
2010 cpu
->mp_is_up
= true;
2011 cpu
->pmsav7_dregion
= 16;
2012 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
2015 static void cortex_r5f_initfn(Object
*obj
)
2017 ARMCPU
*cpu
= ARM_CPU(obj
);
2019 cortex_r5_initfn(obj
);
2020 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2021 cpu
->isar
.mvfr0
= 0x10110221;
2022 cpu
->isar
.mvfr1
= 0x00000011;
2025 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
2026 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
2027 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2028 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2029 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2033 static void cortex_a8_initfn(Object
*obj
)
2035 ARMCPU
*cpu
= ARM_CPU(obj
);
2037 cpu
->dtb_compatible
= "arm,cortex-a8";
2038 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2039 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2040 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2041 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2042 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2043 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2044 cpu
->midr
= 0x410fc080;
2045 cpu
->reset_fpsid
= 0x410330c0;
2046 cpu
->isar
.mvfr0
= 0x11110222;
2047 cpu
->isar
.mvfr1
= 0x00011111;
2048 cpu
->ctr
= 0x82048004;
2049 cpu
->reset_sctlr
= 0x00c50078;
2050 cpu
->id_pfr0
= 0x1031;
2051 cpu
->id_pfr1
= 0x11;
2052 cpu
->id_dfr0
= 0x400;
2054 cpu
->id_mmfr0
= 0x31100003;
2055 cpu
->id_mmfr1
= 0x20000000;
2056 cpu
->id_mmfr2
= 0x01202000;
2057 cpu
->id_mmfr3
= 0x11;
2058 cpu
->isar
.id_isar0
= 0x00101111;
2059 cpu
->isar
.id_isar1
= 0x12112111;
2060 cpu
->isar
.id_isar2
= 0x21232031;
2061 cpu
->isar
.id_isar3
= 0x11112131;
2062 cpu
->isar
.id_isar4
= 0x00111142;
2063 cpu
->dbgdidr
= 0x15141000;
2064 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
2065 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
2066 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
2067 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
2068 cpu
->reset_auxcr
= 2;
2069 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
2072 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
2073 /* power_control should be set to maximum latency. Again,
2074 * default to 0 and set by private hook
2076 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2077 .access
= PL1_RW
, .resetvalue
= 0,
2078 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
2079 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
2080 .access
= PL1_RW
, .resetvalue
= 0,
2081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
2082 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
2083 .access
= PL1_RW
, .resetvalue
= 0,
2084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
2085 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2086 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2087 /* TLB lockdown control */
2088 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
2089 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2090 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
2091 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2092 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
2093 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2094 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
2095 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2096 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
2097 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2101 static void cortex_a9_initfn(Object
*obj
)
2103 ARMCPU
*cpu
= ARM_CPU(obj
);
2105 cpu
->dtb_compatible
= "arm,cortex-a9";
2106 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2107 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2108 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2109 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2110 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2111 /* Note that A9 supports the MP extensions even for
2112 * A9UP and single-core A9MP (which are both different
2113 * and valid configurations; we don't model A9UP).
2115 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2116 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
2117 cpu
->midr
= 0x410fc090;
2118 cpu
->reset_fpsid
= 0x41033090;
2119 cpu
->isar
.mvfr0
= 0x11110222;
2120 cpu
->isar
.mvfr1
= 0x01111111;
2121 cpu
->ctr
= 0x80038003;
2122 cpu
->reset_sctlr
= 0x00c50078;
2123 cpu
->id_pfr0
= 0x1031;
2124 cpu
->id_pfr1
= 0x11;
2125 cpu
->id_dfr0
= 0x000;
2127 cpu
->id_mmfr0
= 0x00100103;
2128 cpu
->id_mmfr1
= 0x20000000;
2129 cpu
->id_mmfr2
= 0x01230000;
2130 cpu
->id_mmfr3
= 0x00002111;
2131 cpu
->isar
.id_isar0
= 0x00101111;
2132 cpu
->isar
.id_isar1
= 0x13112111;
2133 cpu
->isar
.id_isar2
= 0x21232041;
2134 cpu
->isar
.id_isar3
= 0x11112131;
2135 cpu
->isar
.id_isar4
= 0x00111142;
2136 cpu
->dbgdidr
= 0x35141000;
2137 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
2138 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
2139 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
2140 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
2143 #ifndef CONFIG_USER_ONLY
2144 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2146 MachineState
*ms
= MACHINE(qdev_get_machine());
2148 /* Linux wants the number of processors from here.
2149 * Might as well set the interrupt-controller bit too.
2151 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2155 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2156 #ifndef CONFIG_USER_ONLY
2157 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2158 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2159 .writefn
= arm_cp_write_ignore
, },
2161 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2162 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2166 static void cortex_a7_initfn(Object
*obj
)
2168 ARMCPU
*cpu
= ARM_CPU(obj
);
2170 cpu
->dtb_compatible
= "arm,cortex-a7";
2171 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2172 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2173 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2174 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2175 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2176 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2177 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2178 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2179 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2180 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2181 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2182 cpu
->midr
= 0x410fc075;
2183 cpu
->reset_fpsid
= 0x41023075;
2184 cpu
->isar
.mvfr0
= 0x10110222;
2185 cpu
->isar
.mvfr1
= 0x11111111;
2186 cpu
->ctr
= 0x84448003;
2187 cpu
->reset_sctlr
= 0x00c50078;
2188 cpu
->id_pfr0
= 0x00001131;
2189 cpu
->id_pfr1
= 0x00011011;
2190 cpu
->id_dfr0
= 0x02010555;
2191 cpu
->id_afr0
= 0x00000000;
2192 cpu
->id_mmfr0
= 0x10101105;
2193 cpu
->id_mmfr1
= 0x40000000;
2194 cpu
->id_mmfr2
= 0x01240000;
2195 cpu
->id_mmfr3
= 0x02102211;
2196 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2197 * table 4-41 gives 0x02101110, which includes the arm div insns.
2199 cpu
->isar
.id_isar0
= 0x02101110;
2200 cpu
->isar
.id_isar1
= 0x13112111;
2201 cpu
->isar
.id_isar2
= 0x21232041;
2202 cpu
->isar
.id_isar3
= 0x11112131;
2203 cpu
->isar
.id_isar4
= 0x10011142;
2204 cpu
->dbgdidr
= 0x3515f005;
2205 cpu
->clidr
= 0x0a200023;
2206 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2207 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2208 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2209 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2212 static void cortex_a15_initfn(Object
*obj
)
2214 ARMCPU
*cpu
= ARM_CPU(obj
);
2216 cpu
->dtb_compatible
= "arm,cortex-a15";
2217 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2218 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2219 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2220 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2221 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2222 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2223 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2224 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2225 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2226 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2227 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2228 cpu
->midr
= 0x412fc0f1;
2229 cpu
->reset_fpsid
= 0x410430f0;
2230 cpu
->isar
.mvfr0
= 0x10110222;
2231 cpu
->isar
.mvfr1
= 0x11111111;
2232 cpu
->ctr
= 0x8444c004;
2233 cpu
->reset_sctlr
= 0x00c50078;
2234 cpu
->id_pfr0
= 0x00001131;
2235 cpu
->id_pfr1
= 0x00011011;
2236 cpu
->id_dfr0
= 0x02010555;
2237 cpu
->id_afr0
= 0x00000000;
2238 cpu
->id_mmfr0
= 0x10201105;
2239 cpu
->id_mmfr1
= 0x20000000;
2240 cpu
->id_mmfr2
= 0x01240000;
2241 cpu
->id_mmfr3
= 0x02102211;
2242 cpu
->isar
.id_isar0
= 0x02101110;
2243 cpu
->isar
.id_isar1
= 0x13112111;
2244 cpu
->isar
.id_isar2
= 0x21232041;
2245 cpu
->isar
.id_isar3
= 0x11112131;
2246 cpu
->isar
.id_isar4
= 0x10011142;
2247 cpu
->dbgdidr
= 0x3515f021;
2248 cpu
->clidr
= 0x0a200023;
2249 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2250 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2251 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2252 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2255 static void ti925t_initfn(Object
*obj
)
2257 ARMCPU
*cpu
= ARM_CPU(obj
);
2258 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
2259 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
2260 cpu
->midr
= ARM_CPUID_TI925T
;
2261 cpu
->ctr
= 0x5109149;
2262 cpu
->reset_sctlr
= 0x00000070;
2265 static void sa1100_initfn(Object
*obj
)
2267 ARMCPU
*cpu
= ARM_CPU(obj
);
2269 cpu
->dtb_compatible
= "intel,sa1100";
2270 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2271 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2272 cpu
->midr
= 0x4401A11B;
2273 cpu
->reset_sctlr
= 0x00000070;
2276 static void sa1110_initfn(Object
*obj
)
2278 ARMCPU
*cpu
= ARM_CPU(obj
);
2279 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2280 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2281 cpu
->midr
= 0x6901B119;
2282 cpu
->reset_sctlr
= 0x00000070;
2285 static void pxa250_initfn(Object
*obj
)
2287 ARMCPU
*cpu
= ARM_CPU(obj
);
2289 cpu
->dtb_compatible
= "marvell,xscale";
2290 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2291 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2292 cpu
->midr
= 0x69052100;
2293 cpu
->ctr
= 0xd172172;
2294 cpu
->reset_sctlr
= 0x00000078;
2297 static void pxa255_initfn(Object
*obj
)
2299 ARMCPU
*cpu
= ARM_CPU(obj
);
2301 cpu
->dtb_compatible
= "marvell,xscale";
2302 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2303 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2304 cpu
->midr
= 0x69052d00;
2305 cpu
->ctr
= 0xd172172;
2306 cpu
->reset_sctlr
= 0x00000078;
2309 static void pxa260_initfn(Object
*obj
)
2311 ARMCPU
*cpu
= ARM_CPU(obj
);
2313 cpu
->dtb_compatible
= "marvell,xscale";
2314 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2315 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2316 cpu
->midr
= 0x69052903;
2317 cpu
->ctr
= 0xd172172;
2318 cpu
->reset_sctlr
= 0x00000078;
2321 static void pxa261_initfn(Object
*obj
)
2323 ARMCPU
*cpu
= ARM_CPU(obj
);
2325 cpu
->dtb_compatible
= "marvell,xscale";
2326 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2327 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2328 cpu
->midr
= 0x69052d05;
2329 cpu
->ctr
= 0xd172172;
2330 cpu
->reset_sctlr
= 0x00000078;
2333 static void pxa262_initfn(Object
*obj
)
2335 ARMCPU
*cpu
= ARM_CPU(obj
);
2337 cpu
->dtb_compatible
= "marvell,xscale";
2338 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2339 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2340 cpu
->midr
= 0x69052d06;
2341 cpu
->ctr
= 0xd172172;
2342 cpu
->reset_sctlr
= 0x00000078;
2345 static void pxa270a0_initfn(Object
*obj
)
2347 ARMCPU
*cpu
= ARM_CPU(obj
);
2349 cpu
->dtb_compatible
= "marvell,xscale";
2350 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2351 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2352 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2353 cpu
->midr
= 0x69054110;
2354 cpu
->ctr
= 0xd172172;
2355 cpu
->reset_sctlr
= 0x00000078;
2358 static void pxa270a1_initfn(Object
*obj
)
2360 ARMCPU
*cpu
= ARM_CPU(obj
);
2362 cpu
->dtb_compatible
= "marvell,xscale";
2363 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2364 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2365 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2366 cpu
->midr
= 0x69054111;
2367 cpu
->ctr
= 0xd172172;
2368 cpu
->reset_sctlr
= 0x00000078;
2371 static void pxa270b0_initfn(Object
*obj
)
2373 ARMCPU
*cpu
= ARM_CPU(obj
);
2375 cpu
->dtb_compatible
= "marvell,xscale";
2376 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2377 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2378 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2379 cpu
->midr
= 0x69054112;
2380 cpu
->ctr
= 0xd172172;
2381 cpu
->reset_sctlr
= 0x00000078;
2384 static void pxa270b1_initfn(Object
*obj
)
2386 ARMCPU
*cpu
= ARM_CPU(obj
);
2388 cpu
->dtb_compatible
= "marvell,xscale";
2389 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2390 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2391 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2392 cpu
->midr
= 0x69054113;
2393 cpu
->ctr
= 0xd172172;
2394 cpu
->reset_sctlr
= 0x00000078;
2397 static void pxa270c0_initfn(Object
*obj
)
2399 ARMCPU
*cpu
= ARM_CPU(obj
);
2401 cpu
->dtb_compatible
= "marvell,xscale";
2402 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2403 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2404 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2405 cpu
->midr
= 0x69054114;
2406 cpu
->ctr
= 0xd172172;
2407 cpu
->reset_sctlr
= 0x00000078;
2410 static void pxa270c5_initfn(Object
*obj
)
2412 ARMCPU
*cpu
= ARM_CPU(obj
);
2414 cpu
->dtb_compatible
= "marvell,xscale";
2415 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2416 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2417 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2418 cpu
->midr
= 0x69054117;
2419 cpu
->ctr
= 0xd172172;
2420 cpu
->reset_sctlr
= 0x00000078;
2423 #ifndef TARGET_AARCH64
2424 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2425 * otherwise, a CPU with as many features enabled as our emulation supports.
2426 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2427 * this only needs to handle 32 bits.
2429 static void arm_max_initfn(Object
*obj
)
2431 ARMCPU
*cpu
= ARM_CPU(obj
);
2433 if (kvm_enabled()) {
2434 kvm_arm_set_cpu_features_from_host(cpu
);
2436 cortex_a15_initfn(obj
);
2438 /* old-style VFP short-vector support */
2439 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2441 #ifdef CONFIG_USER_ONLY
2442 /* We don't set these in system emulation mode for the moment,
2443 * since we don't correctly set (all of) the ID registers to
2446 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2450 t
= cpu
->isar
.id_isar5
;
2451 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2452 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2453 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2454 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2455 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2456 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2457 cpu
->isar
.id_isar5
= t
;
2459 t
= cpu
->isar
.id_isar6
;
2460 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2461 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2462 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2463 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2464 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2465 cpu
->isar
.id_isar6
= t
;
2467 t
= cpu
->isar
.mvfr1
;
2468 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 2); /* v8.0 FP support */
2469 cpu
->isar
.mvfr1
= t
;
2471 t
= cpu
->isar
.mvfr2
;
2472 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2473 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2474 cpu
->isar
.mvfr2
= t
;
2477 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2485 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2489 void (*initfn
)(Object
*obj
);
2490 void (*class_init
)(ObjectClass
*oc
, void *data
);
2493 static const ARMCPUInfo arm_cpus
[] = {
2494 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2495 { .name
= "arm926", .initfn
= arm926_initfn
},
2496 { .name
= "arm946", .initfn
= arm946_initfn
},
2497 { .name
= "arm1026", .initfn
= arm1026_initfn
},
2498 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2499 * older core than plain "arm1136". In particular this does not
2500 * have the v6K features.
2502 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
2503 { .name
= "arm1136", .initfn
= arm1136_initfn
},
2504 { .name
= "arm1176", .initfn
= arm1176_initfn
},
2505 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
2506 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
2507 .class_init
= arm_v7m_class_init
},
2508 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
2509 .class_init
= arm_v7m_class_init
},
2510 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
2511 .class_init
= arm_v7m_class_init
},
2512 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2513 .class_init
= arm_v7m_class_init
},
2514 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2515 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2516 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2517 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2518 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2519 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2520 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2521 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2522 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2523 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2524 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2525 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2526 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2527 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2528 /* "pxa270" is an alias for "pxa270-a0" */
2529 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2530 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2531 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2532 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2533 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2534 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2535 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2536 #ifndef TARGET_AARCH64
2537 { .name
= "max", .initfn
= arm_max_initfn
},
2539 #ifdef CONFIG_USER_ONLY
2540 { .name
= "any", .initfn
= arm_max_initfn
},
2546 static Property arm_cpu_properties
[] = {
2547 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2548 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2549 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2550 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2551 mp_affinity
, ARM64_AFFINITY_INVALID
),
2552 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2553 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2554 DEFINE_PROP_END_OF_LIST()
2557 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2559 ARMCPU
*cpu
= ARM_CPU(cs
);
2560 CPUARMState
*env
= &cpu
->env
;
2562 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2563 return g_strdup("iwmmxt");
2565 return g_strdup("arm");
2568 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2570 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2571 CPUClass
*cc
= CPU_CLASS(acc
);
2572 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2574 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2575 &acc
->parent_realize
);
2576 dc
->props
= arm_cpu_properties
;
2578 acc
->parent_reset
= cc
->reset
;
2579 cc
->reset
= arm_cpu_reset
;
2581 cc
->class_by_name
= arm_cpu_class_by_name
;
2582 cc
->has_work
= arm_cpu_has_work
;
2583 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2584 cc
->dump_state
= arm_cpu_dump_state
;
2585 cc
->set_pc
= arm_cpu_set_pc
;
2586 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2587 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2588 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2589 #ifndef CONFIG_USER_ONLY
2590 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2591 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2592 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2593 cc
->vmsd
= &vmstate_arm_cpu
;
2594 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2595 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2596 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2598 cc
->gdb_num_core_regs
= 26;
2599 cc
->gdb_core_xml_file
= "arm-core.xml";
2600 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2601 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2602 cc
->gdb_stop_before_watchpoint
= true;
2603 cc
->disas_set_info
= arm_disas_set_info
;
2605 cc
->tcg_initialize
= arm_translate_init
;
2606 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2607 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2608 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2609 #if !defined(CONFIG_USER_ONLY)
2610 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2611 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2612 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2613 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2618 static void arm_host_initfn(Object
*obj
)
2620 ARMCPU
*cpu
= ARM_CPU(obj
);
2622 kvm_arm_set_cpu_features_from_host(cpu
);
2623 arm_cpu_post_init(obj
);
2626 static const TypeInfo host_arm_cpu_type_info
= {
2627 .name
= TYPE_ARM_HOST_CPU
,
2628 #ifdef TARGET_AARCH64
2629 .parent
= TYPE_AARCH64_CPU
,
2631 .parent
= TYPE_ARM_CPU
,
2633 .instance_init
= arm_host_initfn
,
2638 static void arm_cpu_instance_init(Object
*obj
)
2640 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2642 acc
->info
->initfn(obj
);
2643 arm_cpu_post_init(obj
);
2646 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2648 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2653 static void cpu_register(const ARMCPUInfo
*info
)
2655 TypeInfo type_info
= {
2656 .parent
= TYPE_ARM_CPU
,
2657 .instance_size
= sizeof(ARMCPU
),
2658 .instance_init
= arm_cpu_instance_init
,
2659 .class_size
= sizeof(ARMCPUClass
),
2660 .class_init
= info
->class_init
?: cpu_register_class_init
,
2661 .class_data
= (void *)info
,
2664 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2665 type_register(&type_info
);
2666 g_free((void *)type_info
.name
);
2669 static const TypeInfo arm_cpu_type_info
= {
2670 .name
= TYPE_ARM_CPU
,
2672 .instance_size
= sizeof(ARMCPU
),
2673 .instance_init
= arm_cpu_initfn
,
2674 .instance_finalize
= arm_cpu_finalizefn
,
2676 .class_size
= sizeof(ARMCPUClass
),
2677 .class_init
= arm_cpu_class_init
,
2680 static const TypeInfo idau_interface_type_info
= {
2681 .name
= TYPE_IDAU_INTERFACE
,
2682 .parent
= TYPE_INTERFACE
,
2683 .class_size
= sizeof(IDAUInterfaceClass
),
2686 static void arm_cpu_register_types(void)
2688 const ARMCPUInfo
*info
= arm_cpus
;
2690 type_register_static(&arm_cpu_type_info
);
2691 type_register_static(&idau_interface_type_info
);
2693 while (info
->name
) {
2699 type_register_static(&host_arm_cpu_type_info
);
2703 type_init(arm_cpu_register_types
)