include/hw/arm/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HW_ARM_OMAP_H
  21 #define HW_ARM_OMAP_H
  22
  23 #include "exec/memory.h"
  24 #include "hw/irq.h"
  25 #include "hw/input/tsc2xxx.h"
  26 #include "target/arm/cpu-qom.h"
  27 #include "qemu/log.h"
  28
  29 # define OMAP_EMIFS_BASE        0x00000000
  30 # define OMAP2_Q0_BASE          0x00000000
  31 # define OMAP_CS0_BASE          0x00000000
  32 # define OMAP_CS1_BASE          0x04000000
  33 # define OMAP_CS2_BASE          0x08000000
  34 # define OMAP_CS3_BASE          0x0c000000
  35 # define OMAP_EMIFF_BASE        0x10000000
  36 # define OMAP_IMIF_BASE         0x20000000
  37 # define OMAP_LOCALBUS_BASE     0x30000000
  38 # define OMAP2_Q1_BASE          0x40000000
  39 # define OMAP2_L4_BASE          0x48000000
  40 # define OMAP2_SRAM_BASE        0x40200000
  41 # define OMAP2_L3_BASE          0x68000000
  42 # define OMAP2_Q2_BASE          0x80000000
  43 # define OMAP2_Q3_BASE          0xc0000000
  44 # define OMAP_MPUI_BASE         0xe1000000
  45
  46 # define OMAP730_SRAM_SIZE      0x00032000
  47 # define OMAP15XX_SRAM_SIZE     0x00030000
  48 # define OMAP16XX_SRAM_SIZE     0x00004000
  49 # define OMAP1611_SRAM_SIZE     0x0003e800
  50 # define OMAP242X_SRAM_SIZE     0x000a0000
  51 # define OMAP243X_SRAM_SIZE     0x00010000
  52 # define OMAP_CS0_SIZE          0x04000000
  53 # define OMAP_CS1_SIZE          0x04000000
  54 # define OMAP_CS2_SIZE          0x04000000
  55 # define OMAP_CS3_SIZE          0x04000000
  56
  57 /* omap_clk.c */
  58 struct omap_mpu_state_s;
  59 typedef struct clk *omap_clk;
  60 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  61 void omap_clk_init(struct omap_mpu_state_s *mpu);
  62 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  63 void omap_clk_get(omap_clk clk);
  64 void omap_clk_put(omap_clk clk);
  65 void omap_clk_onoff(omap_clk clk, int on);
  66 void omap_clk_canidle(omap_clk clk, int can);
  67 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  68 int64_t omap_clk_getrate(omap_clk clk);
  69 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  70
  71 /* OMAP2 l4 Interconnect */
  72 struct omap_l4_s;
  73 struct omap_l4_region_s {
  74     hwaddr offset;
  75     size_t size;
  76     int access;
  77 };
  78 struct omap_l4_agent_info_s {
  79     int ta;
  80     int region;
  81     int regions;
  82     int ta_region;
  83 };
  84 struct omap_target_agent_s {
  85     MemoryRegion iomem;
  86     struct omap_l4_s *bus;
  87     int regions;
  88     const struct omap_l4_region_s *start;
  89     hwaddr base;
  90     uint32_t component;
  91     uint32_t control;
  92     uint32_t status;
  93 };
  94 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
  95                                hwaddr base, int ta_num);
  96
  97 struct omap_target_agent_s;
  98 struct omap_target_agent_s *omap_l4ta_get(
  99     struct omap_l4_s *bus,
 100     const struct omap_l4_region_s *regions,
 101     const struct omap_l4_agent_info_s *agents,
 102     int cs);
 103 hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
 104                                          int region, MemoryRegion *mr);
 105 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
 106                                        int region);
 107 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
 108                                        int region);
 109
 110 /* OMAP2 SDRAM controller */
 111 struct omap_sdrc_s;
 112 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
 113                                    hwaddr base);
 114 void omap_sdrc_reset(struct omap_sdrc_s *s);
 115
 116 /* OMAP2 general purpose memory controller */
 117 struct omap_gpmc_s;
 118 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
 119                                    hwaddr base,
 120                                    qemu_irq irq, qemu_irq drq);
 121 void omap_gpmc_reset(struct omap_gpmc_s *s);
 122 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
 123 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
 124
 125 /*
 126  * Common IRQ numbers for level 1 interrupt handler
 127  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
 128  */
 129 # define OMAP_INT_CAMERA                1
 130 # define OMAP_INT_FIQ                   3
 131 # define OMAP_INT_RTDX                  6
 132 # define OMAP_INT_DSP_MMU_ABORT         7
 133 # define OMAP_INT_HOST                  8
 134 # define OMAP_INT_ABORT                 9
 135 # define OMAP_INT_BRIDGE_PRIV           13
 136 # define OMAP_INT_GPIO_BANK1            14
 137 # define OMAP_INT_UART3                 15
 138 # define OMAP_INT_TIMER3                16
 139 # define OMAP_INT_DMA_CH0_6             19
 140 # define OMAP_INT_DMA_CH1_7             20
 141 # define OMAP_INT_DMA_CH2_8             21
 142 # define OMAP_INT_DMA_CH3               22
 143 # define OMAP_INT_DMA_CH4               23
 144 # define OMAP_INT_DMA_CH5               24
 145 # define OMAP_INT_DMA_LCD               25
 146 # define OMAP_INT_TIMER1                26
 147 # define OMAP_INT_WD_TIMER              27
 148 # define OMAP_INT_BRIDGE_PUB            28
 149 # define OMAP_INT_TIMER2                30
 150 # define OMAP_INT_LCD_CTRL              31
 151
 152 /*
 153  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
 154  */
 155 # define OMAP_INT_15XX_IH2_IRQ          0
 156 # define OMAP_INT_15XX_LB_MMU           17
 157 # define OMAP_INT_15XX_LOCAL_BUS        29
 158
 159 /*
 160  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
 161  */
 162 # define OMAP_INT_1510_SPI_TX           4
 163 # define OMAP_INT_1510_SPI_RX           5
 164 # define OMAP_INT_1510_DSP_MAILBOX1     10
 165 # define OMAP_INT_1510_DSP_MAILBOX2     11
 166
 167 /*
 168  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 169  */
 170 # define OMAP_INT_310_McBSP2_TX         4
 171 # define OMAP_INT_310_McBSP2_RX         5
 172 # define OMAP_INT_310_HSB_MAILBOX1      12
 173 # define OMAP_INT_310_HSAB_MMU          18
 174
 175 /*
 176  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 177  */
 178 # define OMAP_INT_1610_IH2_IRQ          0
 179 # define OMAP_INT_1610_IH2_FIQ          2
 180 # define OMAP_INT_1610_McBSP2_TX        4
 181 # define OMAP_INT_1610_McBSP2_RX        5
 182 # define OMAP_INT_1610_DSP_MAILBOX1     10
 183 # define OMAP_INT_1610_DSP_MAILBOX2     11
 184 # define OMAP_INT_1610_LCD_LINE         12
 185 # define OMAP_INT_1610_GPTIMER1         17
 186 # define OMAP_INT_1610_GPTIMER2         18
 187 # define OMAP_INT_1610_SSR_FIFO_0       29
 188
 189 /*
 190  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 191  */
 192 # define OMAP_INT_730_IH2_FIQ           0
 193 # define OMAP_INT_730_IH2_IRQ           1
 194 # define OMAP_INT_730_USB_NON_ISO       2
 195 # define OMAP_INT_730_USB_ISO           3
 196 # define OMAP_INT_730_ICR               4
 197 # define OMAP_INT_730_EAC               5
 198 # define OMAP_INT_730_GPIO_BANK1        6
 199 # define OMAP_INT_730_GPIO_BANK2        7
 200 # define OMAP_INT_730_GPIO_BANK3        8
 201 # define OMAP_INT_730_McBSP2TX          10
 202 # define OMAP_INT_730_McBSP2RX          11
 203 # define OMAP_INT_730_McBSP2RX_OVF      12
 204 # define OMAP_INT_730_LCD_LINE          14
 205 # define OMAP_INT_730_GSM_PROTECT       15
 206 # define OMAP_INT_730_TIMER3            16
 207 # define OMAP_INT_730_GPIO_BANK5        17
 208 # define OMAP_INT_730_GPIO_BANK6        18
 209 # define OMAP_INT_730_SPGIO_WR          29
 210
 211 /*
 212  * Common IRQ numbers for level 2 interrupt handler
 213  */
 214 # define OMAP_INT_KEYBOARD              1
 215 # define OMAP_INT_uWireTX               2
 216 # define OMAP_INT_uWireRX               3
 217 # define OMAP_INT_I2C                   4
 218 # define OMAP_INT_MPUIO                 5
 219 # define OMAP_INT_USB_HHC_1             6
 220 # define OMAP_INT_McBSP3TX              10
 221 # define OMAP_INT_McBSP3RX              11
 222 # define OMAP_INT_McBSP1TX              12
 223 # define OMAP_INT_McBSP1RX              13
 224 # define OMAP_INT_UART1                 14
 225 # define OMAP_INT_UART2                 15
 226 # define OMAP_INT_USB_W2FC              20
 227 # define OMAP_INT_1WIRE                 21
 228 # define OMAP_INT_OS_TIMER              22
 229 # define OMAP_INT_OQN                   23
 230 # define OMAP_INT_GAUGE_32K             24
 231 # define OMAP_INT_RTC_TIMER             25
 232 # define OMAP_INT_RTC_ALARM             26
 233 # define OMAP_INT_DSP_MMU               28
 234
 235 /*
 236  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 237  */
 238 # define OMAP_INT_1510_BT_MCSI1TX       16
 239 # define OMAP_INT_1510_BT_MCSI1RX       17
 240 # define OMAP_INT_1510_SoSSI_MATCH      19
 241 # define OMAP_INT_1510_MEM_STICK        27
 242 # define OMAP_INT_1510_COM_SPI_RO       31
 243
 244 /*
 245  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 246  */
 247 # define OMAP_INT_310_FAC               0
 248 # define OMAP_INT_310_USB_HHC_2         7
 249 # define OMAP_INT_310_MCSI1_FE          16
 250 # define OMAP_INT_310_MCSI2_FE          17
 251 # define OMAP_INT_310_USB_W2FC_ISO      29
 252 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 253 # define OMAP_INT_310_McBSP2RX_OF       31
 254
 255 /*
 256  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 257  */
 258 # define OMAP_INT_1610_FAC              0
 259 # define OMAP_INT_1610_USB_HHC_2        7
 260 # define OMAP_INT_1610_USB_OTG          8
 261 # define OMAP_INT_1610_SoSSI            9
 262 # define OMAP_INT_1610_BT_MCSI1TX       16
 263 # define OMAP_INT_1610_BT_MCSI1RX       17
 264 # define OMAP_INT_1610_SoSSI_MATCH      19
 265 # define OMAP_INT_1610_MEM_STICK        27
 266 # define OMAP_INT_1610_McBSP2RX_OF      31
 267 # define OMAP_INT_1610_STI              32
 268 # define OMAP_INT_1610_STI_WAKEUP       33
 269 # define OMAP_INT_1610_GPTIMER3         34
 270 # define OMAP_INT_1610_GPTIMER4         35
 271 # define OMAP_INT_1610_GPTIMER5         36
 272 # define OMAP_INT_1610_GPTIMER6         37
 273 # define OMAP_INT_1610_GPTIMER7         38
 274 # define OMAP_INT_1610_GPTIMER8         39
 275 # define OMAP_INT_1610_GPIO_BANK2       40
 276 # define OMAP_INT_1610_GPIO_BANK3       41
 277 # define OMAP_INT_1610_MMC2             42
 278 # define OMAP_INT_1610_CF               43
 279 # define OMAP_INT_1610_WAKE_UP_REQ      46
 280 # define OMAP_INT_1610_GPIO_BANK4       48
 281 # define OMAP_INT_1610_SPI              49
 282 # define OMAP_INT_1610_DMA_CH6          53
 283 # define OMAP_INT_1610_DMA_CH7          54
 284 # define OMAP_INT_1610_DMA_CH8          55
 285 # define OMAP_INT_1610_DMA_CH9          56
 286 # define OMAP_INT_1610_DMA_CH10         57
 287 # define OMAP_INT_1610_DMA_CH11         58
 288 # define OMAP_INT_1610_DMA_CH12         59
 289 # define OMAP_INT_1610_DMA_CH13         60
 290 # define OMAP_INT_1610_DMA_CH14         61
 291 # define OMAP_INT_1610_DMA_CH15         62
 292 # define OMAP_INT_1610_NAND             63
 293
 294 /*
 295  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 296  */
 297 # define OMAP_INT_730_HW_ERRORS         0
 298 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 299 # define OMAP_INT_730_CFCD              2
 300 # define OMAP_INT_730_CFIREQ            3
 301 # define OMAP_INT_730_I2C               4
 302 # define OMAP_INT_730_PCC               5
 303 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 304 # define OMAP_INT_730_SPI_100K_1        7
 305 # define OMAP_INT_730_SYREN_SPI         8
 306 # define OMAP_INT_730_VLYNQ             9
 307 # define OMAP_INT_730_GPIO_BANK4        10
 308 # define OMAP_INT_730_McBSP1TX          11
 309 # define OMAP_INT_730_McBSP1RX          12
 310 # define OMAP_INT_730_McBSP1RX_OF       13
 311 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 312 # define OMAP_INT_730_UART_MODEM_1      15
 313 # define OMAP_INT_730_MCSI              16
 314 # define OMAP_INT_730_uWireTX           17
 315 # define OMAP_INT_730_uWireRX           18
 316 # define OMAP_INT_730_SMC_CD            19
 317 # define OMAP_INT_730_SMC_IREQ          20
 318 # define OMAP_INT_730_HDQ_1WIRE         21
 319 # define OMAP_INT_730_TIMER32K          22
 320 # define OMAP_INT_730_MMC_SDIO          23
 321 # define OMAP_INT_730_UPLD              24
 322 # define OMAP_INT_730_USB_HHC_1         27
 323 # define OMAP_INT_730_USB_HHC_2         28
 324 # define OMAP_INT_730_USB_GENI          29
 325 # define OMAP_INT_730_USB_OTG           30
 326 # define OMAP_INT_730_CAMERA_IF         31
 327 # define OMAP_INT_730_RNG               32
 328 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 329 # define OMAP_INT_730_DBB_RF_EN         34
 330 # define OMAP_INT_730_MPUIO_KEYPAD      35
 331 # define OMAP_INT_730_SHA1_MD5          36
 332 # define OMAP_INT_730_SPI_100K_2        37
 333 # define OMAP_INT_730_RNG_IDLE          38
 334 # define OMAP_INT_730_MPUIO             39
 335 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 336 # define OMAP_INT_730_LLPC_OE_FALLING   41
 337 # define OMAP_INT_730_LLPC_OE_RISING    42
 338 # define OMAP_INT_730_LLPC_VSYNC        43
 339 # define OMAP_INT_730_WAKE_UP_REQ       46
 340 # define OMAP_INT_730_DMA_CH6           53
 341 # define OMAP_INT_730_DMA_CH7           54
 342 # define OMAP_INT_730_DMA_CH8           55
 343 # define OMAP_INT_730_DMA_CH9           56
 344 # define OMAP_INT_730_DMA_CH10          57
 345 # define OMAP_INT_730_DMA_CH11          58
 346 # define OMAP_INT_730_DMA_CH12          59
 347 # define OMAP_INT_730_DMA_CH13          60
 348 # define OMAP_INT_730_DMA_CH14          61
 349 # define OMAP_INT_730_DMA_CH15          62
 350 # define OMAP_INT_730_NAND              63
 351
 352 /*
 353  * OMAP-24xx common IRQ numbers
 354  */
 355 # define OMAP_INT_24XX_STI              4
 356 # define OMAP_INT_24XX_SYS_NIRQ         7
 357 # define OMAP_INT_24XX_L3_IRQ           10
 358 # define OMAP_INT_24XX_PRCM_MPU_IRQ     11
 359 # define OMAP_INT_24XX_SDMA_IRQ0        12
 360 # define OMAP_INT_24XX_SDMA_IRQ1        13
 361 # define OMAP_INT_24XX_SDMA_IRQ2        14
 362 # define OMAP_INT_24XX_SDMA_IRQ3        15
 363 # define OMAP_INT_243X_MCBSP2_IRQ       16
 364 # define OMAP_INT_243X_MCBSP3_IRQ       17
 365 # define OMAP_INT_243X_MCBSP4_IRQ       18
 366 # define OMAP_INT_243X_MCBSP5_IRQ       19
 367 # define OMAP_INT_24XX_GPMC_IRQ         20
 368 # define OMAP_INT_24XX_GUFFAW_IRQ       21
 369 # define OMAP_INT_24XX_IVA_IRQ          22
 370 # define OMAP_INT_24XX_EAC_IRQ          23
 371 # define OMAP_INT_24XX_CAM_IRQ          24
 372 # define OMAP_INT_24XX_DSS_IRQ          25
 373 # define OMAP_INT_24XX_MAIL_U0_MPU      26
 374 # define OMAP_INT_24XX_DSP_UMA          27
 375 # define OMAP_INT_24XX_DSP_MMU          28
 376 # define OMAP_INT_24XX_GPIO_BANK1       29
 377 # define OMAP_INT_24XX_GPIO_BANK2       30
 378 # define OMAP_INT_24XX_GPIO_BANK3       31
 379 # define OMAP_INT_24XX_GPIO_BANK4       32
 380 # define OMAP_INT_243X_GPIO_BANK5       33
 381 # define OMAP_INT_24XX_MAIL_U3_MPU      34
 382 # define OMAP_INT_24XX_WDT3             35
 383 # define OMAP_INT_24XX_WDT4             36
 384 # define OMAP_INT_24XX_GPTIMER1         37
 385 # define OMAP_INT_24XX_GPTIMER2         38
 386 # define OMAP_INT_24XX_GPTIMER3         39
 387 # define OMAP_INT_24XX_GPTIMER4         40
 388 # define OMAP_INT_24XX_GPTIMER5         41
 389 # define OMAP_INT_24XX_GPTIMER6         42
 390 # define OMAP_INT_24XX_GPTIMER7         43
 391 # define OMAP_INT_24XX_GPTIMER8         44
 392 # define OMAP_INT_24XX_GPTIMER9         45
 393 # define OMAP_INT_24XX_GPTIMER10        46
 394 # define OMAP_INT_24XX_GPTIMER11        47
 395 # define OMAP_INT_24XX_GPTIMER12        48
 396 # define OMAP_INT_24XX_PKA_IRQ          50
 397 # define OMAP_INT_24XX_SHA1MD5_IRQ      51
 398 # define OMAP_INT_24XX_RNG_IRQ          52
 399 # define OMAP_INT_24XX_MG_IRQ           53
 400 # define OMAP_INT_24XX_I2C1_IRQ         56
 401 # define OMAP_INT_24XX_I2C2_IRQ         57
 402 # define OMAP_INT_24XX_MCBSP1_IRQ_TX    59
 403 # define OMAP_INT_24XX_MCBSP1_IRQ_RX    60
 404 # define OMAP_INT_24XX_MCBSP2_IRQ_TX    62
 405 # define OMAP_INT_24XX_MCBSP2_IRQ_RX    63
 406 # define OMAP_INT_243X_MCBSP1_IRQ       64
 407 # define OMAP_INT_24XX_MCSPI1_IRQ       65
 408 # define OMAP_INT_24XX_MCSPI2_IRQ       66
 409 # define OMAP_INT_24XX_SSI1_IRQ0        67
 410 # define OMAP_INT_24XX_SSI1_IRQ1        68
 411 # define OMAP_INT_24XX_SSI2_IRQ0        69
 412 # define OMAP_INT_24XX_SSI2_IRQ1        70
 413 # define OMAP_INT_24XX_SSI_GDD_IRQ      71
 414 # define OMAP_INT_24XX_UART1_IRQ        72
 415 # define OMAP_INT_24XX_UART2_IRQ        73
 416 # define OMAP_INT_24XX_UART3_IRQ        74
 417 # define OMAP_INT_24XX_USB_IRQ_GEN      75
 418 # define OMAP_INT_24XX_USB_IRQ_NISO     76
 419 # define OMAP_INT_24XX_USB_IRQ_ISO      77
 420 # define OMAP_INT_24XX_USB_IRQ_HGEN     78
 421 # define OMAP_INT_24XX_USB_IRQ_HSOF     79
 422 # define OMAP_INT_24XX_USB_IRQ_OTG      80
 423 # define OMAP_INT_24XX_VLYNQ_IRQ        81
 424 # define OMAP_INT_24XX_MMC_IRQ          83
 425 # define OMAP_INT_24XX_MS_IRQ           84
 426 # define OMAP_INT_24XX_FAC_IRQ          85
 427 # define OMAP_INT_24XX_MCSPI3_IRQ       91
 428 # define OMAP_INT_243X_HS_USB_MC        92
 429 # define OMAP_INT_243X_HS_USB_DMA       93
 430 # define OMAP_INT_243X_CARKIT           94
 431 # define OMAP_INT_34XX_GPTIMER12        95
 432
 433 /* omap_dma.c */
 434 enum omap_dma_model {
 435     omap_dma_3_0,
 436     omap_dma_3_1,
 437     omap_dma_3_2,
 438     omap_dma_4,
 439 };
 440
 441 struct soc_dma_s;
 442 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
 443                 MemoryRegion *sysmem,
 444                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 445                 enum omap_dma_model model);
 446 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
 447                 MemoryRegion *sysmem,
 448                 struct omap_mpu_state_s *mpu, int fifo,
 449                 int chans, omap_clk iclk, omap_clk fclk);
 450 void omap_dma_reset(struct soc_dma_s *s);
 451
 452 struct dma_irq_map {
 453     int ih;
 454     int intr;
 455 };
 456
 457 /* Only used in OMAP DMA 3.x gigacells */
 458 enum omap_dma_port {
 459     emiff = 0,
 460     emifs,
 461     imif,       /* omap16xx: ocp_t1 */
 462     tipb,
 463     local,      /* omap16xx: ocp_t2 */
 464     tipb_mpui,
 465     __omap_dma_port_last,
 466 };
 467
 468 typedef enum {
 469     constant = 0,
 470     post_incremented,
 471     single_index,
 472     double_index,
 473 } omap_dma_addressing_t;
 474
 475 /* Only used in OMAP DMA 3.x gigacells */
 476 struct omap_dma_lcd_channel_s {
 477     enum omap_dma_port src;
 478     hwaddr src_f1_top;
 479     hwaddr src_f1_bottom;
 480     hwaddr src_f2_top;
 481     hwaddr src_f2_bottom;
 482
 483     /* Used in OMAP DMA 3.2 gigacell */
 484     unsigned char brust_f1;
 485     unsigned char pack_f1;
 486     unsigned char data_type_f1;
 487     unsigned char brust_f2;
 488     unsigned char pack_f2;
 489     unsigned char data_type_f2;
 490     unsigned char end_prog;
 491     unsigned char repeat;
 492     unsigned char auto_init;
 493     unsigned char priority;
 494     unsigned char fs;
 495     unsigned char running;
 496     unsigned char bs;
 497     unsigned char omap_3_1_compatible_disable;
 498     unsigned char dst;
 499     unsigned char lch_type;
 500     int16_t element_index_f1;
 501     int16_t element_index_f2;
 502     int32_t frame_index_f1;
 503     int32_t frame_index_f2;
 504     uint16_t elements_f1;
 505     uint16_t frames_f1;
 506     uint16_t elements_f2;
 507     uint16_t frames_f2;
 508     omap_dma_addressing_t mode_f1;
 509     omap_dma_addressing_t mode_f2;
 510
 511     /* Destination port is fixed.  */
 512     int interrupts;
 513     int condition;
 514     int dual;
 515
 516     int current_frame;
 517     hwaddr phys_framebuffer[2];
 518     qemu_irq irq;
 519     struct omap_mpu_state_s *mpu;
 520 } *omap_dma_get_lcdch(struct soc_dma_s *s);
 521
 522 /*
 523  * DMA request numbers for OMAP1
 524  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 525  */
 526 # define OMAP_DMA_NO_DEVICE             0
 527 # define OMAP_DMA_MCSI1_TX              1
 528 # define OMAP_DMA_MCSI1_RX              2
 529 # define OMAP_DMA_I2C_RX                3
 530 # define OMAP_DMA_I2C_TX                4
 531 # define OMAP_DMA_EXT_NDMA_REQ0         5
 532 # define OMAP_DMA_EXT_NDMA_REQ1         6
 533 # define OMAP_DMA_UWIRE_TX              7
 534 # define OMAP_DMA_MCBSP1_TX             8
 535 # define OMAP_DMA_MCBSP1_RX             9
 536 # define OMAP_DMA_MCBSP3_TX             10
 537 # define OMAP_DMA_MCBSP3_RX             11
 538 # define OMAP_DMA_UART1_TX              12
 539 # define OMAP_DMA_UART1_RX              13
 540 # define OMAP_DMA_UART2_TX              14
 541 # define OMAP_DMA_UART2_RX              15
 542 # define OMAP_DMA_MCBSP2_TX             16
 543 # define OMAP_DMA_MCBSP2_RX             17
 544 # define OMAP_DMA_UART3_TX              18
 545 # define OMAP_DMA_UART3_RX              19
 546 # define OMAP_DMA_CAMERA_IF_RX          20
 547 # define OMAP_DMA_MMC_TX                21
 548 # define OMAP_DMA_MMC_RX                22
 549 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 550 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 551 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 552 # define OMAP_DMA_USB_W2FC_RX0          26
 553 # define OMAP_DMA_USB_W2FC_RX1          27
 554 # define OMAP_DMA_USB_W2FC_RX2          28
 555 # define OMAP_DMA_USB_W2FC_TX0          29
 556 # define OMAP_DMA_USB_W2FC_TX1          30
 557 # define OMAP_DMA_USB_W2FC_TX2          31
 558
 559 /* These are only for 1610 */
 560 # define OMAP_DMA_CRYPTO_DES_IN         32
 561 # define OMAP_DMA_SPI_TX                33
 562 # define OMAP_DMA_SPI_RX                34
 563 # define OMAP_DMA_CRYPTO_HASH           35
 564 # define OMAP_DMA_CCP_ATTN              36
 565 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 566 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 567 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 568 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 569 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 570 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 571 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 572 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 573 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 574 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 575 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 576 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 577 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 578 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 579 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 580 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 581 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 582 # define OMAP_DMA_MMC2_TX               54
 583 # define OMAP_DMA_MMC2_RX               55
 584 # define OMAP_DMA_CRYPTO_DES_OUT        56
 585
 586 /*
 587  * DMA request numbers for the OMAP2
 588  */
 589 # define OMAP24XX_DMA_NO_DEVICE         0
 590 # define OMAP24XX_DMA_XTI_DMA           1       /* Not in OMAP2420 */
 591 # define OMAP24XX_DMA_EXT_DMAREQ0       2
 592 # define OMAP24XX_DMA_EXT_DMAREQ1       3
 593 # define OMAP24XX_DMA_GPMC              4
 594 # define OMAP24XX_DMA_GFX               5       /* Not in OMAP2420 */
 595 # define OMAP24XX_DMA_DSS               6
 596 # define OMAP24XX_DMA_VLYNQ_TX          7       /* Not in OMAP2420 */
 597 # define OMAP24XX_DMA_CWT               8       /* Not in OMAP2420 */
 598 # define OMAP24XX_DMA_AES_TX            9       /* Not in OMAP2420 */
 599 # define OMAP24XX_DMA_AES_RX            10      /* Not in OMAP2420 */
 600 # define OMAP24XX_DMA_DES_TX            11      /* Not in OMAP2420 */
 601 # define OMAP24XX_DMA_DES_RX            12      /* Not in OMAP2420 */
 602 # define OMAP24XX_DMA_SHA1MD5_RX        13      /* Not in OMAP2420 */
 603 # define OMAP24XX_DMA_EXT_DMAREQ2       14
 604 # define OMAP24XX_DMA_EXT_DMAREQ3       15
 605 # define OMAP24XX_DMA_EXT_DMAREQ4       16
 606 # define OMAP24XX_DMA_EAC_AC_RD         17
 607 # define OMAP24XX_DMA_EAC_AC_WR         18
 608 # define OMAP24XX_DMA_EAC_MD_UL_RD      19
 609 # define OMAP24XX_DMA_EAC_MD_UL_WR      20
 610 # define OMAP24XX_DMA_EAC_MD_DL_RD      21
 611 # define OMAP24XX_DMA_EAC_MD_DL_WR      22
 612 # define OMAP24XX_DMA_EAC_BT_UL_RD      23
 613 # define OMAP24XX_DMA_EAC_BT_UL_WR      24
 614 # define OMAP24XX_DMA_EAC_BT_DL_RD      25
 615 # define OMAP24XX_DMA_EAC_BT_DL_WR      26
 616 # define OMAP24XX_DMA_I2C1_TX           27
 617 # define OMAP24XX_DMA_I2C1_RX           28
 618 # define OMAP24XX_DMA_I2C2_TX           29
 619 # define OMAP24XX_DMA_I2C2_RX           30
 620 # define OMAP24XX_DMA_MCBSP1_TX         31
 621 # define OMAP24XX_DMA_MCBSP1_RX         32
 622 # define OMAP24XX_DMA_MCBSP2_TX         33
 623 # define OMAP24XX_DMA_MCBSP2_RX         34
 624 # define OMAP24XX_DMA_SPI1_TX0          35
 625 # define OMAP24XX_DMA_SPI1_RX0          36
 626 # define OMAP24XX_DMA_SPI1_TX1          37
 627 # define OMAP24XX_DMA_SPI1_RX1          38
 628 # define OMAP24XX_DMA_SPI1_TX2          39
 629 # define OMAP24XX_DMA_SPI1_RX2          40
 630 # define OMAP24XX_DMA_SPI1_TX3          41
 631 # define OMAP24XX_DMA_SPI1_RX3          42
 632 # define OMAP24XX_DMA_SPI2_TX0          43
 633 # define OMAP24XX_DMA_SPI2_RX0          44
 634 # define OMAP24XX_DMA_SPI2_TX1          45
 635 # define OMAP24XX_DMA_SPI2_RX1          46
 636
 637 # define OMAP24XX_DMA_UART1_TX          49
 638 # define OMAP24XX_DMA_UART1_RX          50
 639 # define OMAP24XX_DMA_UART2_TX          51
 640 # define OMAP24XX_DMA_UART2_RX          52
 641 # define OMAP24XX_DMA_UART3_TX          53
 642 # define OMAP24XX_DMA_UART3_RX          54
 643 # define OMAP24XX_DMA_USB_W2FC_TX0      55
 644 # define OMAP24XX_DMA_USB_W2FC_RX0      56
 645 # define OMAP24XX_DMA_USB_W2FC_TX1      57
 646 # define OMAP24XX_DMA_USB_W2FC_RX1      58
 647 # define OMAP24XX_DMA_USB_W2FC_TX2      59
 648 # define OMAP24XX_DMA_USB_W2FC_RX2      60
 649 # define OMAP24XX_DMA_MMC1_TX           61
 650 # define OMAP24XX_DMA_MMC1_RX           62
 651 # define OMAP24XX_DMA_MS                63      /* Not in OMAP2420 */
 652 # define OMAP24XX_DMA_EXT_DMAREQ5       64
 653
 654 /* omap[123].c */
 655 /* OMAP2 gp timer */
 656 struct omap_gp_timer_s;
 657 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
 658                 qemu_irq irq, omap_clk fclk, omap_clk iclk);
 659 void omap_gp_timer_reset(struct omap_gp_timer_s *s);
 660
 661 /* OMAP2 sysctimer */
 662 struct omap_synctimer_s;
 663 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
 664                 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
 665 void omap_synctimer_reset(struct omap_synctimer_s *s);
 666
 667 struct omap_uart_s;
 668 struct omap_uart_s *omap_uart_init(hwaddr base,
 669                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 670                 qemu_irq txdma, qemu_irq rxdma,
 671                 const char *label, Chardev *chr);
 672 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
 673                 struct omap_target_agent_s *ta,
 674                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 675                 qemu_irq txdma, qemu_irq rxdma,
 676                 const char *label, Chardev *chr);
 677 void omap_uart_reset(struct omap_uart_s *s);
 678 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
 679
 680 struct omap_mpuio_s;
 681 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 682 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 683 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 684
 685 struct omap_uwire_s;
 686 void omap_uwire_attach(struct omap_uwire_s *s,
 687                 uWireSlave *slave, int chipselect);
 688
 689 /* OMAP2 spi */
 690 struct omap_mcspi_s;
 691 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
 692                 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
 693 void omap_mcspi_attach(struct omap_mcspi_s *s,
 694                 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
 695                 int chipselect);
 696 void omap_mcspi_reset(struct omap_mcspi_s *s);
 697
 698 struct I2SCodec {
 699     void *opaque;
 700
 701     /* The CPU can call this if it is generating the clock signal on the
 702      * i2s port.  The CODEC can ignore it if it is set up as a clock
 703      * master and generates its own clock.  */
 704     void (*set_rate)(void *opaque, int in, int out);
 705
 706     void (*tx_swallow)(void *opaque);
 707     qemu_irq rx_swallow;
 708     qemu_irq tx_start;
 709
 710     int tx_rate;
 711     int cts;
 712     int rx_rate;
 713     int rts;
 714
 715     struct i2s_fifo_s {
 716         uint8_t *fifo;
 717         int len;
 718         int start;
 719         int size;
 720     } in, out;
 721 };
 722 struct omap_mcbsp_s;
 723 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
 724
 725 void omap_tap_init(struct omap_target_agent_s *ta,
 726                 struct omap_mpu_state_s *mpu);
 727
 728 /* omap_lcdc.c */
 729 struct omap_lcd_panel_s;
 730 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 731 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
 732                                         hwaddr base,
 733                                         qemu_irq irq,
 734                                         struct omap_dma_lcd_channel_s *dma,
 735                                         omap_clk clk);
 736
 737 /* omap_dss.c */
 738 struct rfbi_chip_s {
 739     void *opaque;
 740     void (*write)(void *opaque, int dc, uint16_t value);
 741     void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
 742     uint16_t (*read)(void *opaque, int dc);
 743 };
 744 struct omap_dss_s;
 745 void omap_dss_reset(struct omap_dss_s *s);
 746 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 747                 MemoryRegion *sysmem,
 748                 hwaddr l3_base,
 749                 qemu_irq irq, qemu_irq drq,
 750                 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
 751                 omap_clk ick1, omap_clk ick2);
 752 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
 753
 754 /* omap_mmc.c */
 755 struct omap_mmc_s;
 756 struct omap_mmc_s *omap_mmc_init(hwaddr base,
 757                 MemoryRegion *sysmem,
 758                 BlockBackend *blk,
 759                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 760 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 761                 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
 762                 omap_clk fclk, omap_clk iclk);
 763 void omap_mmc_reset(struct omap_mmc_s *s);
 764 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
 765 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
 766
 767 /* omap_i2c.c */
 768 I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
 769
 770 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 771 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 772 # define cpu_is_omap1610(cpu)           (cpu->mpu_model == omap1610)
 773 # define cpu_is_omap1710(cpu)           (cpu->mpu_model == omap1710)
 774 # define cpu_is_omap2410(cpu)           (cpu->mpu_model == omap2410)
 775 # define cpu_is_omap2420(cpu)           (cpu->mpu_model == omap2420)
 776 # define cpu_is_omap2430(cpu)           (cpu->mpu_model == omap2430)
 777 # define cpu_is_omap3430(cpu)           (cpu->mpu_model == omap3430)
 778 # define cpu_is_omap3630(cpu)           (cpu->mpu_model == omap3630)
 779
 780 # define cpu_is_omap15xx(cpu)           \
 781         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 782 # define cpu_is_omap16xx(cpu)           \
 783         (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
 784 # define cpu_is_omap24xx(cpu)           \
 785         (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
 786
 787 # define cpu_class_omap1(cpu)           \
 788         (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
 789 # define cpu_class_omap2(cpu)           cpu_is_omap24xx(cpu)
 790 # define cpu_class_omap3(cpu) \
 791         (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
 792
 793 struct omap_mpu_state_s {
 794     enum omap_mpu_model {
 795         omap310,
 796         omap1510,
 797         omap1610,
 798         omap1710,
 799         omap2410,
 800         omap2420,
 801         omap2422,
 802         omap2423,
 803         omap2430,
 804         omap3430,
 805         omap3630,
 806     } mpu_model;
 807
 808     ARMCPU *cpu;
 809
 810     qemu_irq *drq;
 811
 812     qemu_irq wakeup;
 813
 814     MemoryRegion ulpd_pm_iomem;
 815     MemoryRegion pin_cfg_iomem;
 816     MemoryRegion id_iomem;
 817     MemoryRegion id_iomem_e18;
 818     MemoryRegion id_iomem_ed4;
 819     MemoryRegion id_iomem_e20;
 820     MemoryRegion mpui_iomem;
 821     MemoryRegion tcmi_iomem;
 822     MemoryRegion clkm_iomem;
 823     MemoryRegion clkdsp_iomem;
 824     MemoryRegion mpui_io_iomem;
 825     MemoryRegion tap_iomem;
 826     MemoryRegion imif_ram;
 827     MemoryRegion emiff_ram;
 828     MemoryRegion sdram;
 829     MemoryRegion sram;
 830
 831     struct omap_dma_port_if_s {
 832         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 833                         hwaddr offset);
 834         void (*write[3])(struct omap_mpu_state_s *s,
 835                         hwaddr offset, uint32_t value);
 836         int (*addr_valid)(struct omap_mpu_state_s *s,
 837                         hwaddr addr);
 838     } port[__omap_dma_port_last];
 839
 840     unsigned long sdram_size;
 841     unsigned long sram_size;
 842
 843     /* MPUI-TIPB peripherals */
 844     struct omap_uart_s *uart[3];
 845
 846     DeviceState *gpio;
 847
 848     struct omap_mcbsp_s *mcbsp1;
 849     struct omap_mcbsp_s *mcbsp3;
 850
 851     /* MPU public TIPB peripherals */
 852     struct omap_32khz_timer_s *os_timer;
 853
 854     struct omap_mmc_s *mmc;
 855
 856     struct omap_mpuio_s *mpuio;
 857
 858     struct omap_uwire_s *microwire;
 859
 860     struct omap_pwl_s *pwl;
 861     struct omap_pwt_s *pwt;
 862     DeviceState *i2c[2];
 863
 864     struct omap_rtc_s *rtc;
 865
 866     struct omap_mcbsp_s *mcbsp2;
 867
 868     struct omap_lpg_s *led[2];
 869
 870     /* MPU private TIPB peripherals */
 871     DeviceState *ih[2];
 872
 873     struct soc_dma_s *dma;
 874
 875     struct omap_mpu_timer_s *timer[3];
 876     struct omap_watchdog_timer_s *wdt;
 877
 878     struct omap_lcd_panel_s *lcd;
 879
 880     uint32_t ulpd_pm_regs[21];
 881     int64_t ulpd_gauge_start;
 882
 883     uint32_t func_mux_ctrl[14];
 884     uint32_t comp_mode_ctrl[1];
 885     uint32_t pull_dwn_ctrl[4];
 886     uint32_t gate_inh_ctrl[1];
 887     uint32_t voltage_ctrl[1];
 888     uint32_t test_dbg_ctrl[1];
 889     uint32_t mod_conf_ctrl[1];
 890     int compat1509;
 891
 892     uint32_t mpui_ctrl;
 893
 894     struct omap_tipb_bridge_s *private_tipb;
 895     struct omap_tipb_bridge_s *public_tipb;
 896
 897     uint32_t tcmi_regs[17];
 898
 899     struct dpll_ctl_s *dpll[3];
 900
 901     omap_clk clks;
 902     struct {
 903         int cold_start;
 904         int clocking_scheme;
 905         uint16_t arm_ckctl;
 906         uint16_t arm_idlect1;
 907         uint16_t arm_idlect2;
 908         uint16_t arm_ewupct;
 909         uint16_t arm_rstct1;
 910         uint16_t arm_rstct2;
 911         uint16_t arm_ckout1;
 912         int dpll1_mode;
 913         uint16_t dsp_idlect1;
 914         uint16_t dsp_idlect2;
 915         uint16_t dsp_rstct2;
 916     } clkm;
 917
 918     /* OMAP2-only peripherals */
 919     struct omap_l4_s *l4;
 920
 921     struct omap_gp_timer_s *gptimer[12];
 922     struct omap_synctimer_s *synctimer;
 923
 924     struct omap_prcm_s *prcm;
 925     struct omap_sdrc_s *sdrc;
 926     struct omap_gpmc_s *gpmc;
 927     struct omap_sysctl_s *sysc;
 928
 929     struct omap_mcspi_s *mcspi[2];
 930
 931     struct omap_dss_s *dss;
 932
 933     struct omap_eac_s *eac;
 934 };
 935
 936 /* omap1.c */
 937 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
 938                 unsigned long sdram_size,
 939                 const char *core);
 940
 941 /* omap2.c */
 942 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
 943                 unsigned long sdram_size,
 944                 const char *core);
 945
 946 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
 947 void omap_badwidth_write8(void *opaque, hwaddr addr,
 948                 uint32_t value);
 949 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
 950 void omap_badwidth_write16(void *opaque, hwaddr addr,
 951                 uint32_t value);
 952 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
 953 void omap_badwidth_write32(void *opaque, hwaddr addr,
 954                 uint32_t value);
 955
 956 void omap_mpu_wakeup(void *opaque, int irq, int req);
 957
 958 # define OMAP_BAD_REG(paddr)            \
 959         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
 960                       __func__, paddr)
 961 # define OMAP_RO_REG(paddr)             \
 962         qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
 963                                        HWADDR_PRIx "\n", \
 964                       __func__, paddr)
 965
 966 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
 967    (Board-specifc tags are not here)  */
 968 #define OMAP_TAG_CLOCK          0x4f01
 969 #define OMAP_TAG_MMC            0x4f02
 970 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 971 #define OMAP_TAG_USB            0x4f04
 972 #define OMAP_TAG_LCD            0x4f05
 973 #define OMAP_TAG_GPIO_SWITCH    0x4f06
 974 #define OMAP_TAG_UART           0x4f07
 975 #define OMAP_TAG_FBMEM          0x4f08
 976 #define OMAP_TAG_STI_CONSOLE    0x4f09
 977 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
 978 #define OMAP_TAG_PARTITION      0x4f0b
 979 #define OMAP_TAG_TEA5761        0x4f10
 980 #define OMAP_TAG_TMP105         0x4f11
 981 #define OMAP_TAG_BOOT_REASON    0x4f80
 982 #define OMAP_TAG_FLASH_PART_STR 0x4f81
 983 #define OMAP_TAG_VERSION_STR    0x4f82
 984
 985 enum {
 986     OMAP_GPIOSW_TYPE_COVER      = 0 << 4,
 987     OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
 988     OMAP_GPIOSW_TYPE_ACTIVITY   = 2 << 4,
 989 };
 990
 991 #define OMAP_GPIOSW_INVERTED    0x0001
 992 #define OMAP_GPIOSW_OUTPUT      0x0002
 993
 994 # define OMAP_MPUI_REG_MASK             0x000007ff
 995
 996 #endif