2 * QEMU PowerPC XIVE interrupt controller model
5 * The POWER9 processor comes with a new interrupt controller, called
6 * XIVE as "eXternal Interrupt Virtualization Engine".
8 * = Overall architecture
11 * XIVE Interrupt Controller
12 * +------------------------------------+ IPIs
13 * | +---------+ +---------+ +--------+ | +-------+
14 * | |VC | |CQ | |PC |----> | CORES |
15 * | | esb | | | | |----> | |
16 * | | eas | | Bridge | | tctx |----> | |
17 * | |SC end | | | | nvt | | | |
18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
19 * | RAM | +------------------|-----------------+ | | |
22 * | | +--------------------v------------------------v-v-v--+ other
23 * | <--+ Power Bus +--> chips
24 * | esb | +---------+-----------------------+------------------+
26 * | end | +--|------+ |
27 * | nvt | +----+----+ | +----+----+
28 * +------+ |SC | | |SC |
30 * | PQ-bits | | | PQ-bits |
31 * | local |-+ | in VC |
32 * +---------+ +---------+
35 * SC: Source Controller (aka. IVSE)
36 * VC: Virtualization Controller (aka. IVRE)
37 * PC: Presentation Controller (aka. IVPE)
38 * CQ: Common Queue (Bridge)
40 * PQ-bits: 2 bits source state machine (P:pending Q:queued)
41 * esb: Event State Buffer (Array of PQ bits in an IVSE)
42 * eas: Event Assignment Structure
43 * end: Event Notification Descriptor
44 * nvt: Notification Virtual Target
45 * tctx: Thread interrupt Context
48 * The XIVE IC is composed of three sub-engines :
50 * - Interrupt Virtualization Source Engine (IVSE), or Source
51 * Controller (SC). These are found in PCI PHBs, in the PSI host
52 * bridge controller, but also inside the main controller for the
53 * core IPIs and other sub-chips (NX, CAP, NPU) of the
54 * chip/processor. They are configured to feed the IVRE with events.
56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
57 * Controller (VC). Its job is to match an event source with an
58 * Event Notification Descriptor (END).
60 * - Interrupt Virtualization Presentation Engine (IVPE) or
61 * Presentation Controller (PC). It maintains the interrupt context
62 * state of each thread and handles the delivery of the external
63 * exception to the thread.
65 * In XIVE 1.0, the sub-engines used to be referred as:
67 * SC Source Controller
68 * VC Virtualization Controller
69 * PC Presentation Controller
70 * CQ Common Queue (PowerBUS Bridge)
73 * = XIVE internal tables
75 * Each of the sub-engines uses a set of tables to redirect exceptions
76 * from event sources to CPU threads.
80 * or +------>|entries|
85 * +-------------------------------------------------+
87 * Hypervisor +------+ +---+--+ +---+--+ +------+
88 * Memory | ESB | | EAT | | ENDT | | NVTT |
89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+
92 * +-------------------------------------------------+
95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+
96 * | | | | | | | | | | tctx| |Thread|
97 * IPI or --> | + v + v + v |---| + .. |-----> |
98 * HW events --> | | | | | |
99 * IVSE | IVRE | | IVPE | +------+
100 * +---------------------------------+ +-------+
104 * The IVSE have a 2-bits state machine, P for pending and Q for queued,
105 * for each source that allows events to be triggered. They are stored in
106 * an Event State Buffer (ESB) array and can be controlled by MMIOs.
108 * If the event is let through, the IVRE looks up in the Event Assignment
109 * Structure (EAS) table for an Event Notification Descriptor (END)
110 * configured for the source. Each Event Notification Descriptor defines
111 * a notification path to a CPU and an in-memory Event Queue, in which
112 * will be enqueued an EQ data for the OS to pull.
114 * The IVPE determines if a Notification Virtual Target (NVT) can
115 * handle the event by scanning the thread contexts of the VCPUs
116 * dispatched on the processor HW threads. It maintains the state of
117 * the thread interrupt context (TCTX) of each thread in a NVT table.
121 * Description In XIVE 1.0, used to be referred as
123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry
124 * EAT Event Assignment Table IVT Interrupt Virt. Table
125 * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table
126 * EQ Event Queue same
127 * ESB Event State Buffer SBE State Bit Entry
128 * NVT Notif. Virtual Target VPD Virtual Processor Desc.
129 * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table
130 * TCTX Thread interrupt Context
133 * Copyright (c) 2017-2018, IBM Corporation.
135 * This code is licensed under the GPL version 2 or later. See the
136 * COPYING file in the top-level directory.
143 #include "hw/qdev-core.h"
146 * XIVE Fabric (Interface between Source and Router)
149 typedef struct XiveNotifier
{
153 #define TYPE_XIVE_NOTIFIER "xive-notifier"
154 #define XIVE_NOTIFIER(obj) \
155 OBJECT_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
156 #define XIVE_NOTIFIER_CLASS(klass) \
157 OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER)
158 #define XIVE_NOTIFIER_GET_CLASS(obj) \
159 OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER)
161 typedef struct XiveNotifierClass
{
162 InterfaceClass parent
;
163 void (*notify
)(XiveNotifier
*xn
, uint32_t lisn
);
167 * XIVE Interrupt Source
170 #define TYPE_XIVE_SOURCE "xive-source"
171 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE)
174 * XIVE Interrupt Source characteristics, which define how the ESB are
177 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
178 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
180 typedef struct XiveSource
{
186 unsigned long *lsi_map
;
188 /* PQ bits and LSI assertion bit */
191 /* ESB memory region */
194 MemoryRegion esb_mmio
;
200 * ESB MMIO setting. Can be one page, for both source triggering and
201 * source management, or two different pages. See below for magic
204 #define XIVE_ESB_4K 12 /* PSI HB only */
205 #define XIVE_ESB_4K_2PAGE 13
206 #define XIVE_ESB_64K 16
207 #define XIVE_ESB_64K_2PAGE 17
209 static inline bool xive_source_esb_has_2page(XiveSource
*xsrc
)
211 return xsrc
->esb_shift
== XIVE_ESB_64K_2PAGE
||
212 xsrc
->esb_shift
== XIVE_ESB_4K_2PAGE
;
215 /* The trigger page is always the first/even page */
216 static inline hwaddr
xive_source_esb_page(XiveSource
*xsrc
, uint32_t srcno
)
218 assert(srcno
< xsrc
->nr_irqs
);
219 return (1ull << xsrc
->esb_shift
) * srcno
;
222 /* In a two pages ESB MMIO setting, the odd page is for management */
223 static inline hwaddr
xive_source_esb_mgmt(XiveSource
*xsrc
, int srcno
)
225 hwaddr addr
= xive_source_esb_page(xsrc
, srcno
);
227 if (xive_source_esb_has_2page(xsrc
)) {
228 addr
+= (1 << (xsrc
->esb_shift
- 1));
235 * Each interrupt source has a 2-bit state machine which can be
236 * controlled by MMIO. P indicates that an interrupt is pending (has
237 * been sent to a queue and is waiting for an EOI). Q indicates that
238 * the interrupt has been triggered while pending.
240 * This acts as a coalescing mechanism in order to guarantee that a
241 * given interrupt only occurs at most once in a queue.
243 * When doing an EOI, the Q bit will indicate if the interrupt
244 * needs to be re-triggered.
246 #define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */
247 #define XIVE_ESB_VAL_P 0x2
248 #define XIVE_ESB_VAL_Q 0x1
250 #define XIVE_ESB_RESET 0x0
251 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P
252 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
253 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q
256 * "magic" Event State Buffer (ESB) MMIO offsets.
258 * The following offsets into the ESB MMIO allow to read or manipulate
259 * the PQ bits. They must be used with an 8-byte load instruction.
260 * They all return the previous state of the interrupt (atomically).
262 * Additionally, some ESB pages support doing an EOI via a store and
263 * some ESBs support doing a trigger via a separate trigger page.
265 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
266 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
267 #define XIVE_ESB_GET 0x800 /* Load */
268 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
269 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
270 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
271 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
273 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
);
274 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
);
276 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
,
279 static inline qemu_irq
xive_source_qirq(XiveSource
*xsrc
, uint32_t srcno
)
281 assert(srcno
< xsrc
->nr_irqs
);
282 return xsrc
->qirqs
[srcno
];
285 static inline bool xive_source_irq_is_lsi(XiveSource
*xsrc
, uint32_t srcno
)
287 assert(srcno
< xsrc
->nr_irqs
);
288 return test_bit(srcno
, xsrc
->lsi_map
);
291 static inline void xive_source_irq_set(XiveSource
*xsrc
, uint32_t srcno
,
294 assert(srcno
< xsrc
->nr_irqs
);
296 bitmap_set(xsrc
->lsi_map
, srcno
, 1);
300 #endif /* PPC_XIVE_H */