hw/timer/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/timer.h"
  27 #include "hw/irq.h"
  28 #include "hw/ptimer.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/sysbus.h"
  31 #include "migration/vmstate.h"
  32 #include "trace.h"
  33 #include "qemu/main-loop.h"
  34 #include "qemu/module.h"
  35
  36 /*
  37  * Registers of hardware timer in sun4m.
  38  *
  39  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  40  * produced as NCR89C105. See
  41  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  42  *
  43  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  44  * are zero. Bit 31 is 1 when count has been reached.
  45  *
  46  * Per-CPU timers interrupt local CPU, system timer uses normal
  47  * interrupt routing.
  48  *
  49  */
  50
  51 #define MAX_CPUS 16
  52
  53 typedef struct CPUTimerState {
  54     qemu_irq irq;
  55     ptimer_state *timer;
  56     uint32_t count, counthigh, reached;
  57     /* processor only */
  58     uint32_t run;
  59     uint64_t limit;
  60 } CPUTimerState;
  61
  62 #define TYPE_SLAVIO_TIMER "slavio_timer"
  63 #define SLAVIO_TIMER(obj) \
  64     OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER)
  65
  66 typedef struct SLAVIO_TIMERState {
  67     SysBusDevice parent_obj;
  68
  69     uint32_t num_cpus;
  70     uint32_t cputimer_mode;
  71     CPUTimerState cputimer[MAX_CPUS + 1];
  72 } SLAVIO_TIMERState;
  73
  74 typedef struct TimerContext {
  75     MemoryRegion iomem;
  76     SLAVIO_TIMERState *s;
  77     unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
  78 } TimerContext;
  79
  80 #define SYS_TIMER_SIZE 0x14
  81 #define CPU_TIMER_SIZE 0x10
  82
  83 #define TIMER_LIMIT         0
  84 #define TIMER_COUNTER       1
  85 #define TIMER_COUNTER_NORST 2
  86 #define TIMER_STATUS        3
  87 #define TIMER_MODE          4
  88
  89 #define TIMER_COUNT_MASK32 0xfffffe00
  90 #define TIMER_LIMIT_MASK32 0x7fffffff
  91 #define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  92 #define TIMER_MAX_COUNT32  0x7ffffe00ULL
  93 #define TIMER_REACHED      0x80000000
  94 #define TIMER_PERIOD       500ULL // 500ns
  95 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
  96 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
  97
  98 static int slavio_timer_is_user(TimerContext *tc)
  99 {
 100     SLAVIO_TIMERState *s = tc->s;
 101     unsigned int timer_index = tc->timer_index;
 102
 103     return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
 104 }
 105
 106 // Update count, set irq, update expire_time
 107 // Convert from ptimer countdown units
 108 static void slavio_timer_get_out(CPUTimerState *t)
 109 {
 110     uint64_t count, limit;
 111
 112     if (t->limit == 0) { /* free-run system or processor counter */
 113         limit = TIMER_MAX_COUNT32;
 114     } else {
 115         limit = t->limit;
 116     }
 117     count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
 118
 119     trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
 120     t->count = count & TIMER_COUNT_MASK32;
 121     t->counthigh = count >> 32;
 122 }
 123
 124 // timer callback
 125 static void slavio_timer_irq(void *opaque)
 126 {
 127     TimerContext *tc = opaque;
 128     SLAVIO_TIMERState *s = tc->s;
 129     CPUTimerState *t = &s->cputimer[tc->timer_index];
 130
 131     slavio_timer_get_out(t);
 132     trace_slavio_timer_irq(t->counthigh, t->count);
 133     /* if limit is 0 (free-run), there will be no match */
 134     if (t->limit != 0) {
 135         t->reached = TIMER_REACHED;
 136     }
 137     /* there is no interrupt if user timer or free-run */
 138     if (!slavio_timer_is_user(tc) && t->limit != 0) {
 139         qemu_irq_raise(t->irq);
 140     }
 141 }
 142
 143 static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
 144                                        unsigned size)
 145 {
 146     TimerContext *tc = opaque;
 147     SLAVIO_TIMERState *s = tc->s;
 148     uint32_t saddr, ret;
 149     unsigned int timer_index = tc->timer_index;
 150     CPUTimerState *t = &s->cputimer[timer_index];
 151
 152     saddr = addr >> 2;
 153     switch (saddr) {
 154     case TIMER_LIMIT:
 155         // read limit (system counter mode) or read most signifying
 156         // part of counter (user mode)
 157         if (slavio_timer_is_user(tc)) {
 158             // read user timer MSW
 159             slavio_timer_get_out(t);
 160             ret = t->counthigh | t->reached;
 161         } else {
 162             // read limit
 163             // clear irq
 164             qemu_irq_lower(t->irq);
 165             t->reached = 0;
 166             ret = t->limit & TIMER_LIMIT_MASK32;
 167         }
 168         break;
 169     case TIMER_COUNTER:
 170         // read counter and reached bit (system mode) or read lsbits
 171         // of counter (user mode)
 172         slavio_timer_get_out(t);
 173         if (slavio_timer_is_user(tc)) { // read user timer LSW
 174             ret = t->count & TIMER_MAX_COUNT64;
 175         } else { // read limit
 176             ret = (t->count & TIMER_MAX_COUNT32) |
 177                 t->reached;
 178         }
 179         break;
 180     case TIMER_STATUS:
 181         // only available in processor counter/timer
 182         // read start/stop status
 183         if (timer_index > 0) {
 184             ret = t->run;
 185         } else {
 186             ret = 0;
 187         }
 188         break;
 189     case TIMER_MODE:
 190         // only available in system counter
 191         // read user/system mode
 192         ret = s->cputimer_mode;
 193         break;
 194     default:
 195         trace_slavio_timer_mem_readl_invalid(addr);
 196         ret = 0;
 197         break;
 198     }
 199     trace_slavio_timer_mem_readl(addr, ret);
 200     return ret;
 201 }
 202
 203 static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
 204                                     uint64_t val, unsigned size)
 205 {
 206     TimerContext *tc = opaque;
 207     SLAVIO_TIMERState *s = tc->s;
 208     uint32_t saddr;
 209     unsigned int timer_index = tc->timer_index;
 210     CPUTimerState *t = &s->cputimer[timer_index];
 211
 212     trace_slavio_timer_mem_writel(addr, val);
 213     saddr = addr >> 2;
 214     switch (saddr) {
 215     case TIMER_LIMIT:
 216         if (slavio_timer_is_user(tc)) {
 217             uint64_t count;
 218
 219             // set user counter MSW, reset counter
 220             t->limit = TIMER_MAX_COUNT64;
 221             t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
 222             t->reached = 0;
 223             count = ((uint64_t)t->counthigh << 32) | t->count;
 224             trace_slavio_timer_mem_writel_limit(timer_index, count);
 225             ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 226         } else {
 227             // set limit, reset counter
 228             qemu_irq_lower(t->irq);
 229             t->limit = val & TIMER_MAX_COUNT32;
 230             if (t->limit == 0) { /* free-run */
 231                 ptimer_set_limit(t->timer,
 232                                  LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 233             } else {
 234                 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
 235             }
 236         }
 237         break;
 238     case TIMER_COUNTER:
 239         if (slavio_timer_is_user(tc)) {
 240             uint64_t count;
 241
 242             // set user counter LSW, reset counter
 243             t->limit = TIMER_MAX_COUNT64;
 244             t->count = val & TIMER_MAX_COUNT64;
 245             t->reached = 0;
 246             count = ((uint64_t)t->counthigh) << 32 | t->count;
 247             trace_slavio_timer_mem_writel_limit(timer_index, count);
 248             ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 249         } else {
 250             trace_slavio_timer_mem_writel_counter_invalid();
 251         }
 252         break;
 253     case TIMER_COUNTER_NORST:
 254         // set limit without resetting counter
 255         t->limit = val & TIMER_MAX_COUNT32;
 256         if (t->limit == 0) { /* free-run */
 257             ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
 258         } else {
 259             ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
 260         }
 261         break;
 262     case TIMER_STATUS:
 263         if (slavio_timer_is_user(tc)) {
 264             // start/stop user counter
 265             if (val & 1) {
 266                 trace_slavio_timer_mem_writel_status_start(timer_index);
 267                 ptimer_run(t->timer, 0);
 268             } else {
 269                 trace_slavio_timer_mem_writel_status_stop(timer_index);
 270                 ptimer_stop(t->timer);
 271             }
 272         }
 273         t->run = val & 1;
 274         break;
 275     case TIMER_MODE:
 276         if (timer_index == 0) {
 277             unsigned int i;
 278
 279             for (i = 0; i < s->num_cpus; i++) {
 280                 unsigned int processor = 1 << i;
 281                 CPUTimerState *curr_timer = &s->cputimer[i + 1];
 282
 283                 // check for a change in timer mode for this processor
 284                 if ((val & processor) != (s->cputimer_mode & processor)) {
 285                     if (val & processor) { // counter -> user timer
 286                         qemu_irq_lower(curr_timer->irq);
 287                         // counters are always running
 288                         if (!curr_timer->run) {
 289                             ptimer_stop(curr_timer->timer);
 290                         }
 291                         // user timer limit is always the same
 292                         curr_timer->limit = TIMER_MAX_COUNT64;
 293                         ptimer_set_limit(curr_timer->timer,
 294                                          LIMIT_TO_PERIODS(curr_timer->limit),
 295                                          1);
 296                         // set this processors user timer bit in config
 297                         // register
 298                         s->cputimer_mode |= processor;
 299                         trace_slavio_timer_mem_writel_mode_user(timer_index);
 300                     } else { // user timer -> counter
 301                         // start the counter
 302                         ptimer_run(curr_timer->timer, 0);
 303                         // clear this processors user timer bit in config
 304                         // register
 305                         s->cputimer_mode &= ~processor;
 306                         trace_slavio_timer_mem_writel_mode_counter(timer_index);
 307                     }
 308                 }
 309             }
 310         } else {
 311             trace_slavio_timer_mem_writel_mode_invalid();
 312         }
 313         break;
 314     default:
 315         trace_slavio_timer_mem_writel_invalid(addr);
 316         break;
 317     }
 318 }
 319
 320 static const MemoryRegionOps slavio_timer_mem_ops = {
 321     .read = slavio_timer_mem_readl,
 322     .write = slavio_timer_mem_writel,
 323     .endianness = DEVICE_NATIVE_ENDIAN,
 324     .valid = {
 325         .min_access_size = 4,
 326         .max_access_size = 4,
 327     },
 328 };
 329
 330 static const VMStateDescription vmstate_timer = {
 331     .name ="timer",
 332     .version_id = 3,
 333     .minimum_version_id = 3,
 334     .fields = (VMStateField[]) {
 335         VMSTATE_UINT64(limit, CPUTimerState),
 336         VMSTATE_UINT32(count, CPUTimerState),
 337         VMSTATE_UINT32(counthigh, CPUTimerState),
 338         VMSTATE_UINT32(reached, CPUTimerState),
 339         VMSTATE_UINT32(run    , CPUTimerState),
 340         VMSTATE_PTIMER(timer, CPUTimerState),
 341         VMSTATE_END_OF_LIST()
 342     }
 343 };
 344
 345 static const VMStateDescription vmstate_slavio_timer = {
 346     .name ="slavio_timer",
 347     .version_id = 3,
 348     .minimum_version_id = 3,
 349     .fields = (VMStateField[]) {
 350         VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
 351                              vmstate_timer, CPUTimerState),
 352         VMSTATE_END_OF_LIST()
 353     }
 354 };
 355
 356 static void slavio_timer_reset(DeviceState *d)
 357 {
 358     SLAVIO_TIMERState *s = SLAVIO_TIMER(d);
 359     unsigned int i;
 360     CPUTimerState *curr_timer;
 361
 362     for (i = 0; i <= MAX_CPUS; i++) {
 363         curr_timer = &s->cputimer[i];
 364         curr_timer->limit = 0;
 365         curr_timer->count = 0;
 366         curr_timer->reached = 0;
 367         if (i <= s->num_cpus) {
 368             ptimer_set_limit(curr_timer->timer,
 369                              LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 370             ptimer_run(curr_timer->timer, 0);
 371             curr_timer->run = 1;
 372         }
 373     }
 374     s->cputimer_mode = 0;
 375 }
 376
 377 static void slavio_timer_init(Object *obj)
 378 {
 379     SLAVIO_TIMERState *s = SLAVIO_TIMER(obj);
 380     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 381     QEMUBH *bh;
 382     unsigned int i;
 383     TimerContext *tc;
 384
 385     for (i = 0; i <= MAX_CPUS; i++) {
 386         uint64_t size;
 387         char timer_name[20];
 388
 389         tc = g_malloc0(sizeof(TimerContext));
 390         tc->s = s;
 391         tc->timer_index = i;
 392
 393         bh = qemu_bh_new(slavio_timer_irq, tc);
 394         s->cputimer[i].timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
 395         ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
 396
 397         size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
 398         snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
 399         memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc,
 400                               timer_name, size);
 401         sysbus_init_mmio(dev, &tc->iomem);
 402
 403         sysbus_init_irq(dev, &s->cputimer[i].irq);
 404     }
 405 }
 406
 407 static Property slavio_timer_properties[] = {
 408     DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
 409     DEFINE_PROP_END_OF_LIST(),
 410 };
 411
 412 static void slavio_timer_class_init(ObjectClass *klass, void *data)
 413 {
 414     DeviceClass *dc = DEVICE_CLASS(klass);
 415
 416     dc->reset = slavio_timer_reset;
 417     dc->vmsd = &vmstate_slavio_timer;
 418     dc->props = slavio_timer_properties;
 419 }
 420
 421 static const TypeInfo slavio_timer_info = {
 422     .name          = TYPE_SLAVIO_TIMER,
 423     .parent        = TYPE_SYS_BUS_DEVICE,
 424     .instance_size = sizeof(SLAVIO_TIMERState),
 425     .instance_init = slavio_timer_init,
 426     .class_init    = slavio_timer_class_init,
 427 };
 428
 429 static void slavio_timer_register_types(void)
 430 {
 431     type_register_static(&slavio_timer_info);
 432 }
 433
 434 type_init(slavio_timer_register_types)