target-i386/monitor.c

   1 /*
   2  * QEMU monitor
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "cpu.h"
  25 #include "monitor/monitor.h"
  26 #include "monitor/hmp-target.h"
  27 #include "hmp.h"
  28
  29
  30 static void print_pte(Monitor *mon, hwaddr addr,
  31                       hwaddr pte,
  32                       hwaddr mask)
  33 {
  34 #ifdef TARGET_X86_64
  35     if (addr & (1ULL << 47)) {
  36         addr |= -1LL << 48;
  37     }
  38 #endif
  39     monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
  40                    " %c%c%c%c%c%c%c%c%c\n",
  41                    addr,
  42                    pte & mask,
  43                    pte & PG_NX_MASK ? 'X' : '-',
  44                    pte & PG_GLOBAL_MASK ? 'G' : '-',
  45                    pte & PG_PSE_MASK ? 'P' : '-',
  46                    pte & PG_DIRTY_MASK ? 'D' : '-',
  47                    pte & PG_ACCESSED_MASK ? 'A' : '-',
  48                    pte & PG_PCD_MASK ? 'C' : '-',
  49                    pte & PG_PWT_MASK ? 'T' : '-',
  50                    pte & PG_USER_MASK ? 'U' : '-',
  51                    pte & PG_RW_MASK ? 'W' : '-');
  52 }
  53
  54 static void tlb_info_32(Monitor *mon, CPUArchState *env)
  55 {
  56     unsigned int l1, l2;
  57     uint32_t pgd, pde, pte;
  58
  59     pgd = env->cr[3] & ~0xfff;
  60     for(l1 = 0; l1 < 1024; l1++) {
  61         cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
  62         pde = le32_to_cpu(pde);
  63         if (pde & PG_PRESENT_MASK) {
  64             if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
  65                 /* 4M pages */
  66                 print_pte(mon, (l1 << 22), pde, ~((1 << 21) - 1));
  67             } else {
  68                 for(l2 = 0; l2 < 1024; l2++) {
  69                     cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
  70                     pte = le32_to_cpu(pte);
  71                     if (pte & PG_PRESENT_MASK) {
  72                         print_pte(mon, (l1 << 22) + (l2 << 12),
  73                                   pte & ~PG_PSE_MASK,
  74                                   ~0xfff);
  75                     }
  76                 }
  77             }
  78         }
  79     }
  80 }
  81
  82 static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
  83 {
  84     unsigned int l1, l2, l3;
  85     uint64_t pdpe, pde, pte;
  86     uint64_t pdp_addr, pd_addr, pt_addr;
  87
  88     pdp_addr = env->cr[3] & ~0x1f;
  89     for (l1 = 0; l1 < 4; l1++) {
  90         cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
  91         pdpe = le64_to_cpu(pdpe);
  92         if (pdpe & PG_PRESENT_MASK) {
  93             pd_addr = pdpe & 0x3fffffffff000ULL;
  94             for (l2 = 0; l2 < 512; l2++) {
  95                 cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
  96                 pde = le64_to_cpu(pde);
  97                 if (pde & PG_PRESENT_MASK) {
  98                     if (pde & PG_PSE_MASK) {
  99                         /* 2M pages with PAE, CR4.PSE is ignored */
 100                         print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
 101                                   ~((hwaddr)(1 << 20) - 1));
 102                     } else {
 103                         pt_addr = pde & 0x3fffffffff000ULL;
 104                         for (l3 = 0; l3 < 512; l3++) {
 105                             cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
 106                             pte = le64_to_cpu(pte);
 107                             if (pte & PG_PRESENT_MASK) {
 108                                 print_pte(mon, (l1 << 30 ) + (l2 << 21)
 109                                           + (l3 << 12),
 110                                           pte & ~PG_PSE_MASK,
 111                                           ~(hwaddr)0xfff);
 112                             }
 113                         }
 114                     }
 115                 }
 116             }
 117         }
 118     }
 119 }
 120
 121 #ifdef TARGET_X86_64
 122 static void tlb_info_64(Monitor *mon, CPUArchState *env)
 123 {
 124     uint64_t l1, l2, l3, l4;
 125     uint64_t pml4e, pdpe, pde, pte;
 126     uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr;
 127
 128     pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
 129     for (l1 = 0; l1 < 512; l1++) {
 130         cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
 131         pml4e = le64_to_cpu(pml4e);
 132         if (pml4e & PG_PRESENT_MASK) {
 133             pdp_addr = pml4e & 0x3fffffffff000ULL;
 134             for (l2 = 0; l2 < 512; l2++) {
 135                 cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
 136                 pdpe = le64_to_cpu(pdpe);
 137                 if (pdpe & PG_PRESENT_MASK) {
 138                     if (pdpe & PG_PSE_MASK) {
 139                         /* 1G pages, CR4.PSE is ignored */
 140                         print_pte(mon, (l1 << 39) + (l2 << 30), pdpe,
 141                                   0x3ffffc0000000ULL);
 142                     } else {
 143                         pd_addr = pdpe & 0x3fffffffff000ULL;
 144                         for (l3 = 0; l3 < 512; l3++) {
 145                             cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
 146                             pde = le64_to_cpu(pde);
 147                             if (pde & PG_PRESENT_MASK) {
 148                                 if (pde & PG_PSE_MASK) {
 149                                     /* 2M pages, CR4.PSE is ignored */
 150                                     print_pte(mon, (l1 << 39) + (l2 << 30) +
 151                                               (l3 << 21), pde,
 152                                               0x3ffffffe00000ULL);
 153                                 } else {
 154                                     pt_addr = pde & 0x3fffffffff000ULL;
 155                                     for (l4 = 0; l4 < 512; l4++) {
 156                                         cpu_physical_memory_read(pt_addr
 157                                                                  + l4 * 8,
 158                                                                  &pte, 8);
 159                                         pte = le64_to_cpu(pte);
 160                                         if (pte & PG_PRESENT_MASK) {
 161                                             print_pte(mon, (l1 << 39) +
 162                                                       (l2 << 30) +
 163                                                       (l3 << 21) + (l4 << 12),
 164                                                       pte & ~PG_PSE_MASK,
 165                                                       0x3fffffffff000ULL);
 166                                         }
 167                                     }
 168                                 }
 169                             }
 170                         }
 171                     }
 172                 }
 173             }
 174         }
 175     }
 176 }
 177 #endif /* TARGET_X86_64 */
 178
 179 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
 180 {
 181     CPUArchState *env;
 182
 183     env = mon_get_cpu_env();
 184
 185     if (!(env->cr[0] & CR0_PG_MASK)) {
 186         monitor_printf(mon, "PG disabled\n");
 187         return;
 188     }
 189     if (env->cr[4] & CR4_PAE_MASK) {
 190 #ifdef TARGET_X86_64
 191         if (env->hflags & HF_LMA_MASK) {
 192             tlb_info_64(mon, env);
 193         } else
 194 #endif
 195         {
 196             tlb_info_pae32(mon, env);
 197         }
 198     } else {
 199         tlb_info_32(mon, env);
 200     }
 201 }
 202
 203 static void mem_print(Monitor *mon, hwaddr *pstart,
 204                       int *plast_prot,
 205                       hwaddr end, int prot)
 206 {
 207     int prot1;
 208     prot1 = *plast_prot;
 209     if (prot != prot1) {
 210         if (*pstart != -1) {
 211             monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
 212                            TARGET_FMT_plx " %c%c%c\n",
 213                            *pstart, end, end - *pstart,
 214                            prot1 & PG_USER_MASK ? 'u' : '-',
 215                            'r',
 216                            prot1 & PG_RW_MASK ? 'w' : '-');
 217         }
 218         if (prot != 0)
 219             *pstart = end;
 220         else
 221             *pstart = -1;
 222         *plast_prot = prot;
 223     }
 224 }
 225
 226 static void mem_info_32(Monitor *mon, CPUArchState *env)
 227 {
 228     unsigned int l1, l2;
 229     int prot, last_prot;
 230     uint32_t pgd, pde, pte;
 231     hwaddr start, end;
 232
 233     pgd = env->cr[3] & ~0xfff;
 234     last_prot = 0;
 235     start = -1;
 236     for(l1 = 0; l1 < 1024; l1++) {
 237         cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
 238         pde = le32_to_cpu(pde);
 239         end = l1 << 22;
 240         if (pde & PG_PRESENT_MASK) {
 241             if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
 242                 prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
 243                 mem_print(mon, &start, &last_prot, end, prot);
 244             } else {
 245                 for(l2 = 0; l2 < 1024; l2++) {
 246                     cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
 247                     pte = le32_to_cpu(pte);
 248                     end = (l1 << 22) + (l2 << 12);
 249                     if (pte & PG_PRESENT_MASK) {
 250                         prot = pte & pde &
 251                             (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
 252                     } else {
 253                         prot = 0;
 254                     }
 255                     mem_print(mon, &start, &last_prot, end, prot);
 256                 }
 257             }
 258         } else {
 259             prot = 0;
 260             mem_print(mon, &start, &last_prot, end, prot);
 261         }
 262     }
 263     /* Flush last range */
 264     mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
 265 }
 266
 267 static void mem_info_pae32(Monitor *mon, CPUArchState *env)
 268 {
 269     unsigned int l1, l2, l3;
 270     int prot, last_prot;
 271     uint64_t pdpe, pde, pte;
 272     uint64_t pdp_addr, pd_addr, pt_addr;
 273     hwaddr start, end;
 274
 275     pdp_addr = env->cr[3] & ~0x1f;
 276     last_prot = 0;
 277     start = -1;
 278     for (l1 = 0; l1 < 4; l1++) {
 279         cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
 280         pdpe = le64_to_cpu(pdpe);
 281         end = l1 << 30;
 282         if (pdpe & PG_PRESENT_MASK) {
 283             pd_addr = pdpe & 0x3fffffffff000ULL;
 284             for (l2 = 0; l2 < 512; l2++) {
 285                 cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
 286                 pde = le64_to_cpu(pde);
 287                 end = (l1 << 30) + (l2 << 21);
 288                 if (pde & PG_PRESENT_MASK) {
 289                     if (pde & PG_PSE_MASK) {
 290                         prot = pde & (PG_USER_MASK | PG_RW_MASK |
 291                                       PG_PRESENT_MASK);
 292                         mem_print(mon, &start, &last_prot, end, prot);
 293                     } else {
 294                         pt_addr = pde & 0x3fffffffff000ULL;
 295                         for (l3 = 0; l3 < 512; l3++) {
 296                             cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
 297                             pte = le64_to_cpu(pte);
 298                             end = (l1 << 30) + (l2 << 21) + (l3 << 12);
 299                             if (pte & PG_PRESENT_MASK) {
 300                                 prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
 301                                                     PG_PRESENT_MASK);
 302                             } else {
 303                                 prot = 0;
 304                             }
 305                             mem_print(mon, &start, &last_prot, end, prot);
 306                         }
 307                     }
 308                 } else {
 309                     prot = 0;
 310                     mem_print(mon, &start, &last_prot, end, prot);
 311                 }
 312             }
 313         } else {
 314             prot = 0;
 315             mem_print(mon, &start, &last_prot, end, prot);
 316         }
 317     }
 318     /* Flush last range */
 319     mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
 320 }
 321
 322
 323 #ifdef TARGET_X86_64
 324 static void mem_info_64(Monitor *mon, CPUArchState *env)
 325 {
 326     int prot, last_prot;
 327     uint64_t l1, l2, l3, l4;
 328     uint64_t pml4e, pdpe, pde, pte;
 329     uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end;
 330
 331     pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
 332     last_prot = 0;
 333     start = -1;
 334     for (l1 = 0; l1 < 512; l1++) {
 335         cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
 336         pml4e = le64_to_cpu(pml4e);
 337         end = l1 << 39;
 338         if (pml4e & PG_PRESENT_MASK) {
 339             pdp_addr = pml4e & 0x3fffffffff000ULL;
 340             for (l2 = 0; l2 < 512; l2++) {
 341                 cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
 342                 pdpe = le64_to_cpu(pdpe);
 343                 end = (l1 << 39) + (l2 << 30);
 344                 if (pdpe & PG_PRESENT_MASK) {
 345                     if (pdpe & PG_PSE_MASK) {
 346                         prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
 347                                        PG_PRESENT_MASK);
 348                         prot &= pml4e;
 349                         mem_print(mon, &start, &last_prot, end, prot);
 350                     } else {
 351                         pd_addr = pdpe & 0x3fffffffff000ULL;
 352                         for (l3 = 0; l3 < 512; l3++) {
 353                             cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
 354                             pde = le64_to_cpu(pde);
 355                             end = (l1 << 39) + (l2 << 30) + (l3 << 21);
 356                             if (pde & PG_PRESENT_MASK) {
 357                                 if (pde & PG_PSE_MASK) {
 358                                     prot = pde & (PG_USER_MASK | PG_RW_MASK |
 359                                                   PG_PRESENT_MASK);
 360                                     prot &= pml4e & pdpe;
 361                                     mem_print(mon, &start, &last_prot, end, prot);
 362                                 } else {
 363                                     pt_addr = pde & 0x3fffffffff000ULL;
 364                                     for (l4 = 0; l4 < 512; l4++) {
 365                                         cpu_physical_memory_read(pt_addr
 366                                                                  + l4 * 8,
 367                                                                  &pte, 8);
 368                                         pte = le64_to_cpu(pte);
 369                                         end = (l1 << 39) + (l2 << 30) +
 370                                             (l3 << 21) + (l4 << 12);
 371                                         if (pte & PG_PRESENT_MASK) {
 372                                             prot = pte & (PG_USER_MASK | PG_RW_MASK |
 373                                                           PG_PRESENT_MASK);
 374                                             prot &= pml4e & pdpe & pde;
 375                                         } else {
 376                                             prot = 0;
 377                                         }
 378                                         mem_print(mon, &start, &last_prot, end, prot);
 379                                     }
 380                                 }
 381                             } else {
 382                                 prot = 0;
 383                                 mem_print(mon, &start, &last_prot, end, prot);
 384                             }
 385                         }
 386                     }
 387                 } else {
 388                     prot = 0;
 389                     mem_print(mon, &start, &last_prot, end, prot);
 390                 }
 391             }
 392         } else {
 393             prot = 0;
 394             mem_print(mon, &start, &last_prot, end, prot);
 395         }
 396     }
 397     /* Flush last range */
 398     mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
 399 }
 400 #endif /* TARGET_X86_64 */
 401
 402 void hmp_info_mem(Monitor *mon, const QDict *qdict)
 403 {
 404     CPUArchState *env;
 405
 406     env = mon_get_cpu_env();
 407
 408     if (!(env->cr[0] & CR0_PG_MASK)) {
 409         monitor_printf(mon, "PG disabled\n");
 410         return;
 411     }
 412     if (env->cr[4] & CR4_PAE_MASK) {
 413 #ifdef TARGET_X86_64
 414         if (env->hflags & HF_LMA_MASK) {
 415             mem_info_64(mon, env);
 416         } else
 417 #endif
 418         {
 419             mem_info_pae32(mon, env);
 420         }
 421     } else {
 422         mem_info_32(mon, env);
 423     }
 424 }
 425
 426 void hmp_mce(Monitor *mon, const QDict *qdict)
 427 {
 428     X86CPU *cpu;
 429     CPUState *cs;
 430     int cpu_index = qdict_get_int(qdict, "cpu_index");
 431     int bank = qdict_get_int(qdict, "bank");
 432     uint64_t status = qdict_get_int(qdict, "status");
 433     uint64_t mcg_status = qdict_get_int(qdict, "mcg_status");
 434     uint64_t addr = qdict_get_int(qdict, "addr");
 435     uint64_t misc = qdict_get_int(qdict, "misc");
 436     int flags = MCE_INJECT_UNCOND_AO;
 437
 438     if (qdict_get_try_bool(qdict, "broadcast", false)) {
 439         flags |= MCE_INJECT_BROADCAST;
 440     }
 441     cs = qemu_get_cpu(cpu_index);
 442     if (cs != NULL) {
 443         cpu = X86_CPU(cs);
 444         cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
 445                            flags);
 446     }
 447 }
 448
 449 static target_long monitor_get_pc(const struct MonitorDef *md, int val)
 450 {
 451     CPUArchState *env = mon_get_cpu_env();
 452     return env->eip + env->segs[R_CS].base;
 453 }
 454
 455 const MonitorDef monitor_defs[] = {
 456 #define SEG(name, seg) \
 457     { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
 458     { name ".base", offsetof(CPUX86State, segs[seg].base) },\
 459     { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
 460
 461     { "eax", offsetof(CPUX86State, regs[0]) },
 462     { "ecx", offsetof(CPUX86State, regs[1]) },
 463     { "edx", offsetof(CPUX86State, regs[2]) },
 464     { "ebx", offsetof(CPUX86State, regs[3]) },
 465     { "esp|sp", offsetof(CPUX86State, regs[4]) },
 466     { "ebp|fp", offsetof(CPUX86State, regs[5]) },
 467     { "esi", offsetof(CPUX86State, regs[6]) },
 468     { "edi", offsetof(CPUX86State, regs[7]) },
 469 #ifdef TARGET_X86_64
 470     { "r8", offsetof(CPUX86State, regs[8]) },
 471     { "r9", offsetof(CPUX86State, regs[9]) },
 472     { "r10", offsetof(CPUX86State, regs[10]) },
 473     { "r11", offsetof(CPUX86State, regs[11]) },
 474     { "r12", offsetof(CPUX86State, regs[12]) },
 475     { "r13", offsetof(CPUX86State, regs[13]) },
 476     { "r14", offsetof(CPUX86State, regs[14]) },
 477     { "r15", offsetof(CPUX86State, regs[15]) },
 478 #endif
 479     { "eflags", offsetof(CPUX86State, eflags) },
 480     { "eip", offsetof(CPUX86State, eip) },
 481     SEG("cs", R_CS)
 482     SEG("ds", R_DS)
 483     SEG("es", R_ES)
 484     SEG("ss", R_SS)
 485     SEG("fs", R_FS)
 486     SEG("gs", R_GS)
 487     { "pc", 0, monitor_get_pc, },
 488     { NULL },
 489 };
 490
 491 const MonitorDef *target_monitor_defs(void)
 492 {
 493     return monitor_defs;
 494 }