vfio: Change polarity of our no-mmap option
[qemu/ar7.git] / target-i386 / cpu.h
blob5231e8c300d856805ea10b5cb0701c77639abbaa
1 /*
2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef CPU_I386_H
20 #define CPU_I386_H
22 #include "config.h"
23 #include "qemu-common.h"
24 #include "standard-headers/asm-x86/hyperv.h"
26 #ifdef TARGET_X86_64
27 #define TARGET_LONG_BITS 64
28 #else
29 #define TARGET_LONG_BITS 32
30 #endif
32 /* Maximum instruction code size */
33 #define TARGET_MAX_INSN_SIZE 16
35 /* support for self modifying code even if the modified instruction is
36 close to the modifying instruction */
37 #define TARGET_HAS_PRECISE_SMC
39 #ifdef TARGET_X86_64
40 #define ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
42 #else
43 #define ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
45 #endif
47 #define CPUArchState struct CPUX86State
49 #include "exec/cpu-defs.h"
51 #include "fpu/softfloat.h"
53 #define R_EAX 0
54 #define R_ECX 1
55 #define R_EDX 2
56 #define R_EBX 3
57 #define R_ESP 4
58 #define R_EBP 5
59 #define R_ESI 6
60 #define R_EDI 7
62 #define R_AL 0
63 #define R_CL 1
64 #define R_DL 2
65 #define R_BL 3
66 #define R_AH 4
67 #define R_CH 5
68 #define R_DH 6
69 #define R_BH 7
71 #define R_ES 0
72 #define R_CS 1
73 #define R_SS 2
74 #define R_DS 3
75 #define R_FS 4
76 #define R_GS 5
78 /* segment descriptor fields */
79 #define DESC_G_MASK (1 << 23)
80 #define DESC_B_SHIFT 22
81 #define DESC_B_MASK (1 << DESC_B_SHIFT)
82 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
83 #define DESC_L_MASK (1 << DESC_L_SHIFT)
84 #define DESC_AVL_MASK (1 << 20)
85 #define DESC_P_MASK (1 << 15)
86 #define DESC_DPL_SHIFT 13
87 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
88 #define DESC_S_MASK (1 << 12)
89 #define DESC_TYPE_SHIFT 8
90 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
91 #define DESC_A_MASK (1 << 8)
93 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
94 #define DESC_C_MASK (1 << 10) /* code: conforming */
95 #define DESC_R_MASK (1 << 9) /* code: readable */
97 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
98 #define DESC_W_MASK (1 << 9) /* data: writable */
100 #define DESC_TSS_BUSY_MASK (1 << 9)
102 /* eflags masks */
103 #define CC_C 0x0001
104 #define CC_P 0x0004
105 #define CC_A 0x0010
106 #define CC_Z 0x0040
107 #define CC_S 0x0080
108 #define CC_O 0x0800
110 #define TF_SHIFT 8
111 #define IOPL_SHIFT 12
112 #define VM_SHIFT 17
114 #define TF_MASK 0x00000100
115 #define IF_MASK 0x00000200
116 #define DF_MASK 0x00000400
117 #define IOPL_MASK 0x00003000
118 #define NT_MASK 0x00004000
119 #define RF_MASK 0x00010000
120 #define VM_MASK 0x00020000
121 #define AC_MASK 0x00040000
122 #define VIF_MASK 0x00080000
123 #define VIP_MASK 0x00100000
124 #define ID_MASK 0x00200000
126 /* hidden flags - used internally by qemu to represent additional cpu
127 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
128 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
129 positions to ease oring with eflags. */
130 /* current cpl */
131 #define HF_CPL_SHIFT 0
132 /* true if soft mmu is being used */
133 #define HF_SOFTMMU_SHIFT 2
134 /* true if hardware interrupts must be disabled for next instruction */
135 #define HF_INHIBIT_IRQ_SHIFT 3
136 /* 16 or 32 segments */
137 #define HF_CS32_SHIFT 4
138 #define HF_SS32_SHIFT 5
139 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
140 #define HF_ADDSEG_SHIFT 6
141 /* copy of CR0.PE (protected mode) */
142 #define HF_PE_SHIFT 7
143 #define HF_TF_SHIFT 8 /* must be same as eflags */
144 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
145 #define HF_EM_SHIFT 10
146 #define HF_TS_SHIFT 11
147 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
148 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
149 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
150 #define HF_RF_SHIFT 16 /* must be same as eflags */
151 #define HF_VM_SHIFT 17 /* must be same as eflags */
152 #define HF_AC_SHIFT 18 /* must be same as eflags */
153 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
154 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
155 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
156 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
157 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
159 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
160 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
161 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
162 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
163 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
164 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
165 #define HF_PE_MASK (1 << HF_PE_SHIFT)
166 #define HF_TF_MASK (1 << HF_TF_SHIFT)
167 #define HF_MP_MASK (1 << HF_MP_SHIFT)
168 #define HF_EM_MASK (1 << HF_EM_SHIFT)
169 #define HF_TS_MASK (1 << HF_TS_SHIFT)
170 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
171 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
172 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
173 #define HF_RF_MASK (1 << HF_RF_SHIFT)
174 #define HF_VM_MASK (1 << HF_VM_SHIFT)
175 #define HF_AC_MASK (1 << HF_AC_SHIFT)
176 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
177 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
178 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
179 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
180 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
182 /* hflags2 */
184 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
185 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
186 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
187 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
188 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
190 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
191 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
192 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
193 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
194 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
196 #define CR0_PE_SHIFT 0
197 #define CR0_MP_SHIFT 1
199 #define CR0_PE_MASK (1U << 0)
200 #define CR0_MP_MASK (1U << 1)
201 #define CR0_EM_MASK (1U << 2)
202 #define CR0_TS_MASK (1U << 3)
203 #define CR0_ET_MASK (1U << 4)
204 #define CR0_NE_MASK (1U << 5)
205 #define CR0_WP_MASK (1U << 16)
206 #define CR0_AM_MASK (1U << 18)
207 #define CR0_PG_MASK (1U << 31)
209 #define CR4_VME_MASK (1U << 0)
210 #define CR4_PVI_MASK (1U << 1)
211 #define CR4_TSD_MASK (1U << 2)
212 #define CR4_DE_MASK (1U << 3)
213 #define CR4_PSE_MASK (1U << 4)
214 #define CR4_PAE_MASK (1U << 5)
215 #define CR4_MCE_MASK (1U << 6)
216 #define CR4_PGE_MASK (1U << 7)
217 #define CR4_PCE_MASK (1U << 8)
218 #define CR4_OSFXSR_SHIFT 9
219 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
220 #define CR4_OSXMMEXCPT_MASK (1U << 10)
221 #define CR4_VMXE_MASK (1U << 13)
222 #define CR4_SMXE_MASK (1U << 14)
223 #define CR4_FSGSBASE_MASK (1U << 16)
224 #define CR4_PCIDE_MASK (1U << 17)
225 #define CR4_OSXSAVE_MASK (1U << 18)
226 #define CR4_SMEP_MASK (1U << 20)
227 #define CR4_SMAP_MASK (1U << 21)
229 #define DR6_BD (1 << 13)
230 #define DR6_BS (1 << 14)
231 #define DR6_BT (1 << 15)
232 #define DR6_FIXED_1 0xffff0ff0
234 #define DR7_GD (1 << 13)
235 #define DR7_TYPE_SHIFT 16
236 #define DR7_LEN_SHIFT 18
237 #define DR7_FIXED_1 0x00000400
238 #define DR7_LOCAL_BP_MASK 0x55
239 #define DR7_MAX_BP 4
240 #define DR7_TYPE_BP_INST 0x0
241 #define DR7_TYPE_DATA_WR 0x1
242 #define DR7_TYPE_IO_RW 0x2
243 #define DR7_TYPE_DATA_RW 0x3
245 #define PG_PRESENT_BIT 0
246 #define PG_RW_BIT 1
247 #define PG_USER_BIT 2
248 #define PG_PWT_BIT 3
249 #define PG_PCD_BIT 4
250 #define PG_ACCESSED_BIT 5
251 #define PG_DIRTY_BIT 6
252 #define PG_PSE_BIT 7
253 #define PG_GLOBAL_BIT 8
254 #define PG_PSE_PAT_BIT 12
255 #define PG_NX_BIT 63
257 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
258 #define PG_RW_MASK (1 << PG_RW_BIT)
259 #define PG_USER_MASK (1 << PG_USER_BIT)
260 #define PG_PWT_MASK (1 << PG_PWT_BIT)
261 #define PG_PCD_MASK (1 << PG_PCD_BIT)
262 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
263 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
264 #define PG_PSE_MASK (1 << PG_PSE_BIT)
265 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
266 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
267 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
268 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
269 #define PG_HI_USER_MASK 0x7ff0000000000000LL
270 #define PG_NX_MASK (1LL << PG_NX_BIT)
272 #define PG_ERROR_W_BIT 1
274 #define PG_ERROR_P_MASK 0x01
275 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
276 #define PG_ERROR_U_MASK 0x04
277 #define PG_ERROR_RSVD_MASK 0x08
278 #define PG_ERROR_I_D_MASK 0x10
280 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
281 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
283 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
284 #define MCE_BANKS_DEF 10
286 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
287 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
288 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
290 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
291 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
292 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
293 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
294 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
295 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
296 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
297 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
298 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
300 /* MISC register defines */
301 #define MCM_ADDR_SEGOFF 0 /* segment offset */
302 #define MCM_ADDR_LINEAR 1 /* linear address */
303 #define MCM_ADDR_PHYS 2 /* physical address */
304 #define MCM_ADDR_MEM 3 /* memory address */
305 #define MCM_ADDR_GENERIC 7 /* generic */
307 #define MSR_IA32_TSC 0x10
308 #define MSR_IA32_APICBASE 0x1b
309 #define MSR_IA32_APICBASE_BSP (1<<8)
310 #define MSR_IA32_APICBASE_ENABLE (1<<11)
311 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
312 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
313 #define MSR_TSC_ADJUST 0x0000003b
314 #define MSR_IA32_TSCDEADLINE 0x6e0
316 #define MSR_P6_PERFCTR0 0xc1
318 #define MSR_IA32_SMBASE 0x9e
319 #define MSR_MTRRcap 0xfe
320 #define MSR_MTRRcap_VCNT 8
321 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
322 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
324 #define MSR_IA32_SYSENTER_CS 0x174
325 #define MSR_IA32_SYSENTER_ESP 0x175
326 #define MSR_IA32_SYSENTER_EIP 0x176
328 #define MSR_MCG_CAP 0x179
329 #define MSR_MCG_STATUS 0x17a
330 #define MSR_MCG_CTL 0x17b
332 #define MSR_P6_EVNTSEL0 0x186
334 #define MSR_IA32_PERF_STATUS 0x198
336 #define MSR_IA32_MISC_ENABLE 0x1a0
337 /* Indicates good rep/movs microcode on some processors: */
338 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
340 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
341 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
343 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
345 #define MSR_MTRRfix64K_00000 0x250
346 #define MSR_MTRRfix16K_80000 0x258
347 #define MSR_MTRRfix16K_A0000 0x259
348 #define MSR_MTRRfix4K_C0000 0x268
349 #define MSR_MTRRfix4K_C8000 0x269
350 #define MSR_MTRRfix4K_D0000 0x26a
351 #define MSR_MTRRfix4K_D8000 0x26b
352 #define MSR_MTRRfix4K_E0000 0x26c
353 #define MSR_MTRRfix4K_E8000 0x26d
354 #define MSR_MTRRfix4K_F0000 0x26e
355 #define MSR_MTRRfix4K_F8000 0x26f
357 #define MSR_PAT 0x277
359 #define MSR_MTRRdefType 0x2ff
361 #define MSR_CORE_PERF_FIXED_CTR0 0x309
362 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
363 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
364 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
365 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
366 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
367 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
369 #define MSR_MC0_CTL 0x400
370 #define MSR_MC0_STATUS 0x401
371 #define MSR_MC0_ADDR 0x402
372 #define MSR_MC0_MISC 0x403
374 #define MSR_EFER 0xc0000080
376 #define MSR_EFER_SCE (1 << 0)
377 #define MSR_EFER_LME (1 << 8)
378 #define MSR_EFER_LMA (1 << 10)
379 #define MSR_EFER_NXE (1 << 11)
380 #define MSR_EFER_SVME (1 << 12)
381 #define MSR_EFER_FFXSR (1 << 14)
383 #define MSR_STAR 0xc0000081
384 #define MSR_LSTAR 0xc0000082
385 #define MSR_CSTAR 0xc0000083
386 #define MSR_FMASK 0xc0000084
387 #define MSR_FSBASE 0xc0000100
388 #define MSR_GSBASE 0xc0000101
389 #define MSR_KERNELGSBASE 0xc0000102
390 #define MSR_TSC_AUX 0xc0000103
392 #define MSR_VM_HSAVE_PA 0xc0010117
394 #define MSR_IA32_BNDCFGS 0x00000d90
395 #define MSR_IA32_XSS 0x00000da0
397 #define XSTATE_FP (1ULL << 0)
398 #define XSTATE_SSE (1ULL << 1)
399 #define XSTATE_YMM (1ULL << 2)
400 #define XSTATE_BNDREGS (1ULL << 3)
401 #define XSTATE_BNDCSR (1ULL << 4)
402 #define XSTATE_OPMASK (1ULL << 5)
403 #define XSTATE_ZMM_Hi256 (1ULL << 6)
404 #define XSTATE_Hi16_ZMM (1ULL << 7)
407 /* CPUID feature words */
408 typedef enum FeatureWord {
409 FEAT_1_EDX, /* CPUID[1].EDX */
410 FEAT_1_ECX, /* CPUID[1].ECX */
411 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
412 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
413 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
414 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
415 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
416 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
417 FEAT_SVM, /* CPUID[8000_000A].EDX */
418 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
419 FEAT_6_EAX, /* CPUID[6].EAX */
420 FEATURE_WORDS,
421 } FeatureWord;
423 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
425 /* cpuid_features bits */
426 #define CPUID_FP87 (1U << 0)
427 #define CPUID_VME (1U << 1)
428 #define CPUID_DE (1U << 2)
429 #define CPUID_PSE (1U << 3)
430 #define CPUID_TSC (1U << 4)
431 #define CPUID_MSR (1U << 5)
432 #define CPUID_PAE (1U << 6)
433 #define CPUID_MCE (1U << 7)
434 #define CPUID_CX8 (1U << 8)
435 #define CPUID_APIC (1U << 9)
436 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
437 #define CPUID_MTRR (1U << 12)
438 #define CPUID_PGE (1U << 13)
439 #define CPUID_MCA (1U << 14)
440 #define CPUID_CMOV (1U << 15)
441 #define CPUID_PAT (1U << 16)
442 #define CPUID_PSE36 (1U << 17)
443 #define CPUID_PN (1U << 18)
444 #define CPUID_CLFLUSH (1U << 19)
445 #define CPUID_DTS (1U << 21)
446 #define CPUID_ACPI (1U << 22)
447 #define CPUID_MMX (1U << 23)
448 #define CPUID_FXSR (1U << 24)
449 #define CPUID_SSE (1U << 25)
450 #define CPUID_SSE2 (1U << 26)
451 #define CPUID_SS (1U << 27)
452 #define CPUID_HT (1U << 28)
453 #define CPUID_TM (1U << 29)
454 #define CPUID_IA64 (1U << 30)
455 #define CPUID_PBE (1U << 31)
457 #define CPUID_EXT_SSE3 (1U << 0)
458 #define CPUID_EXT_PCLMULQDQ (1U << 1)
459 #define CPUID_EXT_DTES64 (1U << 2)
460 #define CPUID_EXT_MONITOR (1U << 3)
461 #define CPUID_EXT_DSCPL (1U << 4)
462 #define CPUID_EXT_VMX (1U << 5)
463 #define CPUID_EXT_SMX (1U << 6)
464 #define CPUID_EXT_EST (1U << 7)
465 #define CPUID_EXT_TM2 (1U << 8)
466 #define CPUID_EXT_SSSE3 (1U << 9)
467 #define CPUID_EXT_CID (1U << 10)
468 #define CPUID_EXT_FMA (1U << 12)
469 #define CPUID_EXT_CX16 (1U << 13)
470 #define CPUID_EXT_XTPR (1U << 14)
471 #define CPUID_EXT_PDCM (1U << 15)
472 #define CPUID_EXT_PCID (1U << 17)
473 #define CPUID_EXT_DCA (1U << 18)
474 #define CPUID_EXT_SSE41 (1U << 19)
475 #define CPUID_EXT_SSE42 (1U << 20)
476 #define CPUID_EXT_X2APIC (1U << 21)
477 #define CPUID_EXT_MOVBE (1U << 22)
478 #define CPUID_EXT_POPCNT (1U << 23)
479 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
480 #define CPUID_EXT_AES (1U << 25)
481 #define CPUID_EXT_XSAVE (1U << 26)
482 #define CPUID_EXT_OSXSAVE (1U << 27)
483 #define CPUID_EXT_AVX (1U << 28)
484 #define CPUID_EXT_F16C (1U << 29)
485 #define CPUID_EXT_RDRAND (1U << 30)
486 #define CPUID_EXT_HYPERVISOR (1U << 31)
488 #define CPUID_EXT2_FPU (1U << 0)
489 #define CPUID_EXT2_VME (1U << 1)
490 #define CPUID_EXT2_DE (1U << 2)
491 #define CPUID_EXT2_PSE (1U << 3)
492 #define CPUID_EXT2_TSC (1U << 4)
493 #define CPUID_EXT2_MSR (1U << 5)
494 #define CPUID_EXT2_PAE (1U << 6)
495 #define CPUID_EXT2_MCE (1U << 7)
496 #define CPUID_EXT2_CX8 (1U << 8)
497 #define CPUID_EXT2_APIC (1U << 9)
498 #define CPUID_EXT2_SYSCALL (1U << 11)
499 #define CPUID_EXT2_MTRR (1U << 12)
500 #define CPUID_EXT2_PGE (1U << 13)
501 #define CPUID_EXT2_MCA (1U << 14)
502 #define CPUID_EXT2_CMOV (1U << 15)
503 #define CPUID_EXT2_PAT (1U << 16)
504 #define CPUID_EXT2_PSE36 (1U << 17)
505 #define CPUID_EXT2_MP (1U << 19)
506 #define CPUID_EXT2_NX (1U << 20)
507 #define CPUID_EXT2_MMXEXT (1U << 22)
508 #define CPUID_EXT2_MMX (1U << 23)
509 #define CPUID_EXT2_FXSR (1U << 24)
510 #define CPUID_EXT2_FFXSR (1U << 25)
511 #define CPUID_EXT2_PDPE1GB (1U << 26)
512 #define CPUID_EXT2_RDTSCP (1U << 27)
513 #define CPUID_EXT2_LM (1U << 29)
514 #define CPUID_EXT2_3DNOWEXT (1U << 30)
515 #define CPUID_EXT2_3DNOW (1U << 31)
517 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
518 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
519 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
520 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
521 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
522 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
523 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
524 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
525 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
526 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
528 #define CPUID_EXT3_LAHF_LM (1U << 0)
529 #define CPUID_EXT3_CMP_LEG (1U << 1)
530 #define CPUID_EXT3_SVM (1U << 2)
531 #define CPUID_EXT3_EXTAPIC (1U << 3)
532 #define CPUID_EXT3_CR8LEG (1U << 4)
533 #define CPUID_EXT3_ABM (1U << 5)
534 #define CPUID_EXT3_SSE4A (1U << 6)
535 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
536 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
537 #define CPUID_EXT3_OSVW (1U << 9)
538 #define CPUID_EXT3_IBS (1U << 10)
539 #define CPUID_EXT3_XOP (1U << 11)
540 #define CPUID_EXT3_SKINIT (1U << 12)
541 #define CPUID_EXT3_WDT (1U << 13)
542 #define CPUID_EXT3_LWP (1U << 15)
543 #define CPUID_EXT3_FMA4 (1U << 16)
544 #define CPUID_EXT3_TCE (1U << 17)
545 #define CPUID_EXT3_NODEID (1U << 19)
546 #define CPUID_EXT3_TBM (1U << 21)
547 #define CPUID_EXT3_TOPOEXT (1U << 22)
548 #define CPUID_EXT3_PERFCORE (1U << 23)
549 #define CPUID_EXT3_PERFNB (1U << 24)
551 #define CPUID_SVM_NPT (1U << 0)
552 #define CPUID_SVM_LBRV (1U << 1)
553 #define CPUID_SVM_SVMLOCK (1U << 2)
554 #define CPUID_SVM_NRIPSAVE (1U << 3)
555 #define CPUID_SVM_TSCSCALE (1U << 4)
556 #define CPUID_SVM_VMCBCLEAN (1U << 5)
557 #define CPUID_SVM_FLUSHASID (1U << 6)
558 #define CPUID_SVM_DECODEASSIST (1U << 7)
559 #define CPUID_SVM_PAUSEFILTER (1U << 10)
560 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
562 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
563 #define CPUID_7_0_EBX_BMI1 (1U << 3)
564 #define CPUID_7_0_EBX_HLE (1U << 4)
565 #define CPUID_7_0_EBX_AVX2 (1U << 5)
566 #define CPUID_7_0_EBX_SMEP (1U << 7)
567 #define CPUID_7_0_EBX_BMI2 (1U << 8)
568 #define CPUID_7_0_EBX_ERMS (1U << 9)
569 #define CPUID_7_0_EBX_INVPCID (1U << 10)
570 #define CPUID_7_0_EBX_RTM (1U << 11)
571 #define CPUID_7_0_EBX_MPX (1U << 14)
572 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
573 #define CPUID_7_0_EBX_RDSEED (1U << 18)
574 #define CPUID_7_0_EBX_ADX (1U << 19)
575 #define CPUID_7_0_EBX_SMAP (1U << 20)
576 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
577 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
578 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
580 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
581 #define CPUID_XSAVE_XSAVEC (1U << 1)
582 #define CPUID_XSAVE_XGETBV1 (1U << 2)
583 #define CPUID_XSAVE_XSAVES (1U << 3)
585 #define CPUID_6_EAX_ARAT (1U << 2)
587 /* CPUID[0x80000007].EDX flags: */
588 #define CPUID_APM_INVTSC (1U << 8)
590 #define CPUID_VENDOR_SZ 12
592 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
593 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
594 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
595 #define CPUID_VENDOR_INTEL "GenuineIntel"
597 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
598 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
599 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
600 #define CPUID_VENDOR_AMD "AuthenticAMD"
602 #define CPUID_VENDOR_VIA "CentaurHauls"
604 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
605 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
607 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
608 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
609 #endif
611 #define EXCP00_DIVZ 0
612 #define EXCP01_DB 1
613 #define EXCP02_NMI 2
614 #define EXCP03_INT3 3
615 #define EXCP04_INTO 4
616 #define EXCP05_BOUND 5
617 #define EXCP06_ILLOP 6
618 #define EXCP07_PREX 7
619 #define EXCP08_DBLE 8
620 #define EXCP09_XERR 9
621 #define EXCP0A_TSS 10
622 #define EXCP0B_NOSEG 11
623 #define EXCP0C_STACK 12
624 #define EXCP0D_GPF 13
625 #define EXCP0E_PAGE 14
626 #define EXCP10_COPR 16
627 #define EXCP11_ALGN 17
628 #define EXCP12_MCHK 18
630 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
631 for syscall instruction */
633 /* i386-specific interrupt pending bits. */
634 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
635 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
636 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
637 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
638 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
639 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
640 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
642 /* Use a clearer name for this. */
643 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
645 typedef enum {
646 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
647 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
649 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
650 CC_OP_MULW,
651 CC_OP_MULL,
652 CC_OP_MULQ,
654 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
655 CC_OP_ADDW,
656 CC_OP_ADDL,
657 CC_OP_ADDQ,
659 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
660 CC_OP_ADCW,
661 CC_OP_ADCL,
662 CC_OP_ADCQ,
664 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
665 CC_OP_SUBW,
666 CC_OP_SUBL,
667 CC_OP_SUBQ,
669 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
670 CC_OP_SBBW,
671 CC_OP_SBBL,
672 CC_OP_SBBQ,
674 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
675 CC_OP_LOGICW,
676 CC_OP_LOGICL,
677 CC_OP_LOGICQ,
679 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
680 CC_OP_INCW,
681 CC_OP_INCL,
682 CC_OP_INCQ,
684 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
685 CC_OP_DECW,
686 CC_OP_DECL,
687 CC_OP_DECQ,
689 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
690 CC_OP_SHLW,
691 CC_OP_SHLL,
692 CC_OP_SHLQ,
694 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
695 CC_OP_SARW,
696 CC_OP_SARL,
697 CC_OP_SARQ,
699 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
700 CC_OP_BMILGW,
701 CC_OP_BMILGL,
702 CC_OP_BMILGQ,
704 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
705 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
706 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
708 CC_OP_CLR, /* Z set, all other flags clear. */
710 CC_OP_NB,
711 } CCOp;
713 typedef struct SegmentCache {
714 uint32_t selector;
715 target_ulong base;
716 uint32_t limit;
717 uint32_t flags;
718 } SegmentCache;
720 typedef union {
721 uint8_t _b[64];
722 uint16_t _w[32];
723 uint32_t _l[16];
724 uint64_t _q[8];
725 float32 _s[16];
726 float64 _d[8];
727 } XMMReg; /* really zmm */
729 typedef union {
730 uint8_t _b[8];
731 uint16_t _w[4];
732 uint32_t _l[2];
733 float32 _s[2];
734 uint64_t q;
735 } MMXReg;
737 typedef struct BNDReg {
738 uint64_t lb;
739 uint64_t ub;
740 } BNDReg;
742 typedef struct BNDCSReg {
743 uint64_t cfgu;
744 uint64_t sts;
745 } BNDCSReg;
747 #ifdef HOST_WORDS_BIGENDIAN
748 #define XMM_B(n) _b[63 - (n)]
749 #define XMM_W(n) _w[31 - (n)]
750 #define XMM_L(n) _l[15 - (n)]
751 #define XMM_S(n) _s[15 - (n)]
752 #define XMM_Q(n) _q[7 - (n)]
753 #define XMM_D(n) _d[7 - (n)]
755 #define MMX_B(n) _b[7 - (n)]
756 #define MMX_W(n) _w[3 - (n)]
757 #define MMX_L(n) _l[1 - (n)]
758 #define MMX_S(n) _s[1 - (n)]
759 #else
760 #define XMM_B(n) _b[n]
761 #define XMM_W(n) _w[n]
762 #define XMM_L(n) _l[n]
763 #define XMM_S(n) _s[n]
764 #define XMM_Q(n) _q[n]
765 #define XMM_D(n) _d[n]
767 #define MMX_B(n) _b[n]
768 #define MMX_W(n) _w[n]
769 #define MMX_L(n) _l[n]
770 #define MMX_S(n) _s[n]
771 #endif
772 #define MMX_Q(n) q
774 typedef union {
775 floatx80 d __attribute__((aligned(16)));
776 MMXReg mmx;
777 } FPReg;
779 typedef struct {
780 uint64_t base;
781 uint64_t mask;
782 } MTRRVar;
784 #define CPU_NB_REGS64 16
785 #define CPU_NB_REGS32 8
787 #ifdef TARGET_X86_64
788 #define CPU_NB_REGS CPU_NB_REGS64
789 #else
790 #define CPU_NB_REGS CPU_NB_REGS32
791 #endif
793 #define MAX_FIXED_COUNTERS 3
794 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
796 #define NB_MMU_MODES 3
798 #define NB_OPMASK_REGS 8
800 typedef enum TPRAccess {
801 TPR_ACCESS_READ,
802 TPR_ACCESS_WRITE,
803 } TPRAccess;
805 typedef struct CPUX86State {
806 /* standard registers */
807 target_ulong regs[CPU_NB_REGS];
808 target_ulong eip;
809 target_ulong eflags; /* eflags register. During CPU emulation, CC
810 flags and DF are set to zero because they are
811 stored elsewhere */
813 /* emulator internal eflags handling */
814 target_ulong cc_dst;
815 target_ulong cc_src;
816 target_ulong cc_src2;
817 uint32_t cc_op;
818 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
819 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
820 are known at translation time. */
821 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
823 /* segments */
824 SegmentCache segs[6]; /* selector values */
825 SegmentCache ldt;
826 SegmentCache tr;
827 SegmentCache gdt; /* only base and limit are used */
828 SegmentCache idt; /* only base and limit are used */
830 target_ulong cr[5]; /* NOTE: cr1 is unused */
831 int32_t a20_mask;
833 BNDReg bnd_regs[4];
834 BNDCSReg bndcs_regs;
835 uint64_t msr_bndcfgs;
837 /* Beginning of state preserved by INIT (dummy marker). */
838 struct {} start_init_save;
840 /* FPU state */
841 unsigned int fpstt; /* top of stack index */
842 uint16_t fpus;
843 uint16_t fpuc;
844 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
845 FPReg fpregs[8];
846 /* KVM-only so far */
847 uint16_t fpop;
848 uint64_t fpip;
849 uint64_t fpdp;
851 /* emulator internal variables */
852 float_status fp_status;
853 floatx80 ft0;
855 float_status mmx_status; /* for 3DNow! float ops */
856 float_status sse_status;
857 uint32_t mxcsr;
858 XMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
859 XMMReg xmm_t0;
860 MMXReg mmx_t0;
862 uint64_t opmask_regs[NB_OPMASK_REGS];
864 /* sysenter registers */
865 uint32_t sysenter_cs;
866 target_ulong sysenter_esp;
867 target_ulong sysenter_eip;
868 uint64_t efer;
869 uint64_t star;
871 uint64_t vm_hsave;
873 #ifdef TARGET_X86_64
874 target_ulong lstar;
875 target_ulong cstar;
876 target_ulong fmask;
877 target_ulong kernelgsbase;
878 #endif
880 uint64_t tsc;
881 uint64_t tsc_adjust;
882 uint64_t tsc_deadline;
884 uint64_t mcg_status;
885 uint64_t msr_ia32_misc_enable;
886 uint64_t msr_ia32_feature_control;
888 uint64_t msr_fixed_ctr_ctrl;
889 uint64_t msr_global_ctrl;
890 uint64_t msr_global_status;
891 uint64_t msr_global_ovf_ctrl;
892 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
893 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
894 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
896 uint64_t pat;
897 uint32_t smbase;
899 /* End of state preserved by INIT (dummy marker). */
900 struct {} end_init_save;
902 uint64_t system_time_msr;
903 uint64_t wall_clock_msr;
904 uint64_t steal_time_msr;
905 uint64_t async_pf_en_msr;
906 uint64_t pv_eoi_en_msr;
908 uint64_t msr_hv_hypercall;
909 uint64_t msr_hv_guest_os_id;
910 uint64_t msr_hv_vapic;
911 uint64_t msr_hv_tsc;
912 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS];
914 /* exception/interrupt handling */
915 int error_code;
916 int exception_is_int;
917 target_ulong exception_next_eip;
918 target_ulong dr[8]; /* debug registers */
919 union {
920 struct CPUBreakpoint *cpu_breakpoint[4];
921 struct CPUWatchpoint *cpu_watchpoint[4];
922 }; /* break/watchpoints for dr[0..3] */
923 int old_exception; /* exception in flight */
925 uint64_t vm_vmcb;
926 uint64_t tsc_offset;
927 uint64_t intercept;
928 uint16_t intercept_cr_read;
929 uint16_t intercept_cr_write;
930 uint16_t intercept_dr_read;
931 uint16_t intercept_dr_write;
932 uint32_t intercept_exceptions;
933 uint8_t v_tpr;
935 /* KVM states, automatically cleared on reset */
936 uint8_t nmi_injected;
937 uint8_t nmi_pending;
939 CPU_COMMON
941 /* Fields from here on are preserved across CPU reset. */
943 /* processor features (e.g. for CPUID insn) */
944 uint32_t cpuid_level;
945 uint32_t cpuid_xlevel;
946 uint32_t cpuid_xlevel2;
947 uint32_t cpuid_vendor1;
948 uint32_t cpuid_vendor2;
949 uint32_t cpuid_vendor3;
950 uint32_t cpuid_version;
951 FeatureWordArray features;
952 uint32_t cpuid_model[12];
954 /* MTRRs */
955 uint64_t mtrr_fixed[11];
956 uint64_t mtrr_deftype;
957 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
959 /* For KVM */
960 uint32_t mp_state;
961 int32_t exception_injected;
962 int32_t interrupt_injected;
963 uint8_t soft_interrupt;
964 uint8_t has_error_code;
965 uint32_t sipi_vector;
966 bool tsc_valid;
967 int64_t tsc_khz;
968 void *kvm_xsave_buf;
970 uint64_t mcg_cap;
971 uint64_t mcg_ctl;
972 uint64_t mce_banks[MCE_BANKS_DEF*4];
974 uint64_t tsc_aux;
976 /* vmstate */
977 uint16_t fpus_vmstate;
978 uint16_t fptag_vmstate;
979 uint16_t fpregs_format_vmstate;
980 uint64_t xstate_bv;
982 uint64_t xcr0;
983 uint64_t xss;
985 TPRAccess tpr_access_type;
986 } CPUX86State;
988 #include "cpu-qom.h"
990 X86CPU *cpu_x86_init(const char *cpu_model);
991 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
992 int cpu_x86_exec(CPUState *cpu);
993 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
994 void x86_cpudef_setup(void);
995 int cpu_x86_support_mca_broadcast(CPUX86State *env);
997 int cpu_get_pic_interrupt(CPUX86State *s);
998 /* MSDOS compatibility mode FPU exception support */
999 void cpu_set_ferr(CPUX86State *s);
1001 /* this function must always be used to load data in the segment
1002 cache: it synchronizes the hflags with the segment cache values */
1003 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1004 int seg_reg, unsigned int selector,
1005 target_ulong base,
1006 unsigned int limit,
1007 unsigned int flags)
1009 SegmentCache *sc;
1010 unsigned int new_hflags;
1012 sc = &env->segs[seg_reg];
1013 sc->selector = selector;
1014 sc->base = base;
1015 sc->limit = limit;
1016 sc->flags = flags;
1018 /* update the hidden flags */
1020 if (seg_reg == R_CS) {
1021 #ifdef TARGET_X86_64
1022 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1023 /* long mode */
1024 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1025 env->hflags &= ~(HF_ADDSEG_MASK);
1026 } else
1027 #endif
1029 /* legacy / compatibility case */
1030 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1031 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1032 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1033 new_hflags;
1036 if (seg_reg == R_SS) {
1037 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1038 #if HF_CPL_MASK != 3
1039 #error HF_CPL_MASK is hardcoded
1040 #endif
1041 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1043 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1044 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1045 if (env->hflags & HF_CS64_MASK) {
1046 /* zero base assumed for DS, ES and SS in long mode */
1047 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1048 (env->eflags & VM_MASK) ||
1049 !(env->hflags & HF_CS32_MASK)) {
1050 /* XXX: try to avoid this test. The problem comes from the
1051 fact that is real mode or vm86 mode we only modify the
1052 'base' and 'selector' fields of the segment cache to go
1053 faster. A solution may be to force addseg to one in
1054 translate-i386.c. */
1055 new_hflags |= HF_ADDSEG_MASK;
1056 } else {
1057 new_hflags |= ((env->segs[R_DS].base |
1058 env->segs[R_ES].base |
1059 env->segs[R_SS].base) != 0) <<
1060 HF_ADDSEG_SHIFT;
1062 env->hflags = (env->hflags &
1063 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1067 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1068 uint8_t sipi_vector)
1070 CPUState *cs = CPU(cpu);
1071 CPUX86State *env = &cpu->env;
1073 env->eip = 0;
1074 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1075 sipi_vector << 12,
1076 env->segs[R_CS].limit,
1077 env->segs[R_CS].flags);
1078 cs->halted = 0;
1081 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1082 target_ulong *base, unsigned int *limit,
1083 unsigned int *flags);
1085 /* op_helper.c */
1086 /* used for debug or cpu save/restore */
1087 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1088 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1090 /* cpu-exec.c */
1091 /* the following helpers are only usable in user mode simulation as
1092 they can trigger unexpected exceptions */
1093 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1094 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1095 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1097 /* you can call this signal handler from your SIGBUS and SIGSEGV
1098 signal handlers to inform the virtual CPU of exceptions. non zero
1099 is returned if the signal was handled by the virtual CPU. */
1100 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1101 void *puc);
1103 /* cpuid.c */
1104 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1105 uint32_t *eax, uint32_t *ebx,
1106 uint32_t *ecx, uint32_t *edx);
1107 void cpu_clear_apic_feature(CPUX86State *env);
1108 void host_cpuid(uint32_t function, uint32_t count,
1109 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1111 /* helper.c */
1112 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1113 int is_write, int mmu_idx);
1114 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1116 #ifndef CONFIG_USER_ONLY
1117 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1118 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1119 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1120 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1121 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1122 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1123 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1124 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1125 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1126 #endif
1128 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
1130 return (dr7 >> (index * 2)) & 1;
1133 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
1135 return (dr7 >> (index * 2)) & 2;
1138 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
1140 return hw_global_breakpoint_enabled(dr7, index) ||
1141 hw_local_breakpoint_enabled(dr7, index);
1144 static inline int hw_breakpoint_type(unsigned long dr7, int index)
1146 return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
1149 static inline int hw_breakpoint_len(unsigned long dr7, int index)
1151 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
1152 return (len == 2) ? 8 : len + 1;
1155 void hw_breakpoint_insert(CPUX86State *env, int index);
1156 void hw_breakpoint_remove(CPUX86State *env, int index);
1157 bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
1158 void breakpoint_handler(CPUState *cs);
1160 /* will be suppressed */
1161 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1162 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1163 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1165 /* hw/pc.c */
1166 uint64_t cpu_get_tsc(CPUX86State *env);
1168 #define TARGET_PAGE_BITS 12
1170 #ifdef TARGET_X86_64
1171 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1172 /* ??? This is really 48 bits, sign-extended, but the only thing
1173 accessible to userland with bit 48 set is the VSYSCALL, and that
1174 is handled via other mechanisms. */
1175 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1176 #else
1177 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1178 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1179 #endif
1181 /* XXX: This value should match the one returned by CPUID
1182 * and in exec.c */
1183 # if defined(TARGET_X86_64)
1184 # define PHYS_ADDR_MASK 0xffffffffffLL
1185 # else
1186 # define PHYS_ADDR_MASK 0xfffffffffLL
1187 # endif
1189 #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
1191 #define cpu_exec cpu_x86_exec
1192 #define cpu_gen_code cpu_x86_gen_code
1193 #define cpu_signal_handler cpu_x86_signal_handler
1194 #define cpu_list x86_cpu_list
1195 #define cpudef_setup x86_cpudef_setup
1197 /* MMU modes definitions */
1198 #define MMU_MODE0_SUFFIX _ksmap
1199 #define MMU_MODE1_SUFFIX _user
1200 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1201 #define MMU_KSMAP_IDX 0
1202 #define MMU_USER_IDX 1
1203 #define MMU_KNOSMAP_IDX 2
1204 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1206 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1207 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1208 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1211 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1213 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1214 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1215 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1218 #define CC_DST (env->cc_dst)
1219 #define CC_SRC (env->cc_src)
1220 #define CC_SRC2 (env->cc_src2)
1221 #define CC_OP (env->cc_op)
1223 /* n must be a constant to be efficient */
1224 static inline target_long lshift(target_long x, int n)
1226 if (n >= 0) {
1227 return x << n;
1228 } else {
1229 return x >> (-n);
1233 /* float macros */
1234 #define FT0 (env->ft0)
1235 #define ST0 (env->fpregs[env->fpstt].d)
1236 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1237 #define ST1 ST(1)
1239 /* translate.c */
1240 void optimize_flags_init(void);
1242 #include "exec/cpu-all.h"
1243 #include "svm.h"
1245 #if !defined(CONFIG_USER_ONLY)
1246 #include "hw/i386/apic.h"
1247 #endif
1249 #include "exec/exec-all.h"
1251 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1252 target_ulong *cs_base, int *flags)
1254 *cs_base = env->segs[R_CS].base;
1255 *pc = *cs_base + env->eip;
1256 *flags = env->hflags |
1257 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1260 void do_cpu_init(X86CPU *cpu);
1261 void do_cpu_sipi(X86CPU *cpu);
1263 #define MCE_INJECT_BROADCAST 1
1264 #define MCE_INJECT_UNCOND_AO 2
1266 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1267 uint64_t status, uint64_t mcg_status, uint64_t addr,
1268 uint64_t misc, int flags);
1270 /* excp_helper.c */
1271 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1272 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1273 uintptr_t retaddr);
1274 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1275 int error_code);
1276 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1277 int error_code, uintptr_t retaddr);
1278 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1279 int error_code, int next_eip_addend);
1281 /* cc_helper.c */
1282 extern const uint8_t parity_table[256];
1283 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1284 void update_fp_status(CPUX86State *env);
1286 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1288 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1291 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1292 * after generating a call to a helper that uses this.
1294 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1295 int update_mask)
1297 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1298 CC_OP = CC_OP_EFLAGS;
1299 env->df = 1 - (2 * ((eflags >> 10) & 1));
1300 env->eflags = (env->eflags & ~update_mask) |
1301 (eflags & update_mask) | 0x2;
1304 /* load efer and update the corresponding hflags. XXX: do consistency
1305 checks with cpuid bits? */
1306 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1308 env->efer = val;
1309 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1310 if (env->efer & MSR_EFER_LMA) {
1311 env->hflags |= HF_LMA_MASK;
1313 if (env->efer & MSR_EFER_SVME) {
1314 env->hflags |= HF_SVME_MASK;
1318 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1320 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1323 /* fpu_helper.c */
1324 void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
1325 void cpu_set_fpuc(CPUX86State *env, uint16_t val);
1327 /* mem_helper.c */
1328 void helper_lock_init(void);
1330 /* svm_helper.c */
1331 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1332 uint64_t param);
1333 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1335 /* seg_helper.c */
1336 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1338 /* smm_helper.c */
1339 void do_smm_enter(X86CPU *cpu);
1340 void cpu_smm_update(X86CPU *cpu);
1342 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1344 void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features);
1345 void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features);
1348 /* Return name of 32-bit register, from a R_* constant */
1349 const char *get_register_name_32(unsigned int reg);
1351 void enable_compat_apic_id_mode(void);
1353 #define APIC_DEFAULT_ADDRESS 0xfee00000
1354 #define APIC_SPACE_SIZE 0x100000
1356 #endif /* CPU_I386_H */