tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "tcg-target.h"
  33
  34 /* XXX: make safe guess about sizes */
  35 #define MAX_OP_PER_INSTR 266
  36
  37 #if HOST_LONG_BITS == 32
  38 #define MAX_OPC_PARAM_PER_ARG 2
  39 #else
  40 #define MAX_OPC_PARAM_PER_ARG 1
  41 #endif
  42 #define MAX_OPC_PARAM_IARGS 5
  43 #define MAX_OPC_PARAM_OARGS 1
  44 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  45
  46 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  47  * and up to 4 + N parameters on 64-bit archs
  48  * (N = number of input arguments + output arguments).  */
  49 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  50 #define OPC_BUF_SIZE 640
  51 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  52
  53 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  54
  55 #define CPU_TEMP_BUF_NLONGS 128
  56
  57 /* Default target word size to pointer size.  */
  58 #ifndef TCG_TARGET_REG_BITS
  59 # if UINTPTR_MAX == UINT32_MAX
  60 #  define TCG_TARGET_REG_BITS 32
  61 # elif UINTPTR_MAX == UINT64_MAX
  62 #  define TCG_TARGET_REG_BITS 64
  63 # else
  64 #  error Unknown pointer size for tcg target
  65 # endif
  66 #endif
  67
  68 #if TCG_TARGET_REG_BITS == 32
  69 typedef int32_t tcg_target_long;
  70 typedef uint32_t tcg_target_ulong;
  71 #define TCG_PRIlx PRIx32
  72 #define TCG_PRIld PRId32
  73 #elif TCG_TARGET_REG_BITS == 64
  74 typedef int64_t tcg_target_long;
  75 typedef uint64_t tcg_target_ulong;
  76 #define TCG_PRIlx PRIx64
  77 #define TCG_PRIld PRId64
  78 #else
  79 #error unsupported
  80 #endif
  81
  82 #if TCG_TARGET_NB_REGS <= 32
  83 typedef uint32_t TCGRegSet;
  84 #elif TCG_TARGET_NB_REGS <= 64
  85 typedef uint64_t TCGRegSet;
  86 #else
  87 #error unsupported
  88 #endif
  89
  90 #if TCG_TARGET_REG_BITS == 32
  91 /* Turn some undef macros into false macros.  */
  92 #define TCG_TARGET_HAS_extrl_i64_i32    0
  93 #define TCG_TARGET_HAS_extrh_i64_i32    0
  94 #define TCG_TARGET_HAS_div_i64          0
  95 #define TCG_TARGET_HAS_rem_i64          0
  96 #define TCG_TARGET_HAS_div2_i64         0
  97 #define TCG_TARGET_HAS_rot_i64          0
  98 #define TCG_TARGET_HAS_ext8s_i64        0
  99 #define TCG_TARGET_HAS_ext16s_i64       0
 100 #define TCG_TARGET_HAS_ext32s_i64       0
 101 #define TCG_TARGET_HAS_ext8u_i64        0
 102 #define TCG_TARGET_HAS_ext16u_i64       0
 103 #define TCG_TARGET_HAS_ext32u_i64       0
 104 #define TCG_TARGET_HAS_bswap16_i64      0
 105 #define TCG_TARGET_HAS_bswap32_i64      0
 106 #define TCG_TARGET_HAS_bswap64_i64      0
 107 #define TCG_TARGET_HAS_neg_i64          0
 108 #define TCG_TARGET_HAS_not_i64          0
 109 #define TCG_TARGET_HAS_andc_i64         0
 110 #define TCG_TARGET_HAS_orc_i64          0
 111 #define TCG_TARGET_HAS_eqv_i64          0
 112 #define TCG_TARGET_HAS_nand_i64         0
 113 #define TCG_TARGET_HAS_nor_i64          0
 114 #define TCG_TARGET_HAS_deposit_i64      0
 115 #define TCG_TARGET_HAS_movcond_i64      0
 116 #define TCG_TARGET_HAS_add2_i64         0
 117 #define TCG_TARGET_HAS_sub2_i64         0
 118 #define TCG_TARGET_HAS_mulu2_i64        0
 119 #define TCG_TARGET_HAS_muls2_i64        0
 120 #define TCG_TARGET_HAS_muluh_i64        0
 121 #define TCG_TARGET_HAS_mulsh_i64        0
 122 /* Turn some undef macros into true macros.  */
 123 #define TCG_TARGET_HAS_add2_i32         1
 124 #define TCG_TARGET_HAS_sub2_i32         1
 125 #endif
 126
 127 #ifndef TCG_TARGET_deposit_i32_valid
 128 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 129 #endif
 130 #ifndef TCG_TARGET_deposit_i64_valid
 131 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 132 #endif
 133
 134 /* Only one of DIV or DIV2 should be defined.  */
 135 #if defined(TCG_TARGET_HAS_div_i32)
 136 #define TCG_TARGET_HAS_div2_i32         0
 137 #elif defined(TCG_TARGET_HAS_div2_i32)
 138 #define TCG_TARGET_HAS_div_i32          0
 139 #define TCG_TARGET_HAS_rem_i32          0
 140 #endif
 141 #if defined(TCG_TARGET_HAS_div_i64)
 142 #define TCG_TARGET_HAS_div2_i64         0
 143 #elif defined(TCG_TARGET_HAS_div2_i64)
 144 #define TCG_TARGET_HAS_div_i64          0
 145 #define TCG_TARGET_HAS_rem_i64          0
 146 #endif
 147
 148 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 149 #if TCG_TARGET_REG_BITS == 32 \
 150     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 151          || defined(TCG_TARGET_HAS_muluh_i32))
 152 # error "Missing unsigned widening multiply"
 153 #endif
 154
 155 #ifndef TARGET_INSN_START_EXTRA_WORDS
 156 # define TARGET_INSN_START_WORDS 1
 157 #else
 158 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 159 #endif
 160
 161 typedef enum TCGOpcode {
 162 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 163 #include "tcg-opc.h"
 164 #undef DEF
 165     NB_OPS,
 166 } TCGOpcode;
 167
 168 #define tcg_regset_clear(d) (d) = 0
 169 #define tcg_regset_set(d, s) (d) = (s)
 170 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
 171 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
 172 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
 173 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
 174 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
 175 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
 176 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
 177 #define tcg_regset_not(d, a) (d) = ~(a)
 178
 179 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 180 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 181 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 182 typedef uint8_t tcg_insn_unit;
 183 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 184 typedef uint16_t tcg_insn_unit;
 185 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 186 typedef uint32_t tcg_insn_unit;
 187 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 188 typedef uint64_t tcg_insn_unit;
 189 #else
 190 /* The port better have done this.  */
 191 #endif
 192
 193
 194 typedef struct TCGRelocation {
 195     struct TCGRelocation *next;
 196     int type;
 197     tcg_insn_unit *ptr;
 198     intptr_t addend;
 199 } TCGRelocation;
 200
 201 typedef struct TCGLabel {
 202     unsigned has_value : 1;
 203     unsigned id : 31;
 204     union {
 205         uintptr_t value;
 206         tcg_insn_unit *value_ptr;
 207         TCGRelocation *first_reloc;
 208     } u;
 209 } TCGLabel;
 210
 211 typedef struct TCGPool {
 212     struct TCGPool *next;
 213     int size;
 214     uint8_t data[0] __attribute__ ((aligned));
 215 } TCGPool;
 216
 217 #define TCG_POOL_CHUNK_SIZE 32768
 218
 219 #define TCG_MAX_TEMPS 512
 220 #define TCG_MAX_INSNS 512
 221
 222 /* when the size of the arguments of a called function is smaller than
 223    this value, they are statically allocated in the TB stack frame */
 224 #define TCG_STATIC_CALL_ARGS_SIZE 128
 225
 226 typedef enum TCGType {
 227     TCG_TYPE_I32,
 228     TCG_TYPE_I64,
 229     TCG_TYPE_COUNT, /* number of different types */
 230
 231     /* An alias for the size of the host register.  */
 232 #if TCG_TARGET_REG_BITS == 32
 233     TCG_TYPE_REG = TCG_TYPE_I32,
 234 #else
 235     TCG_TYPE_REG = TCG_TYPE_I64,
 236 #endif
 237
 238     /* An alias for the size of the native pointer.  */
 239 #if UINTPTR_MAX == UINT32_MAX
 240     TCG_TYPE_PTR = TCG_TYPE_I32,
 241 #else
 242     TCG_TYPE_PTR = TCG_TYPE_I64,
 243 #endif
 244
 245     /* An alias for the size of the target "long", aka register.  */
 246 #if TARGET_LONG_BITS == 64
 247     TCG_TYPE_TL = TCG_TYPE_I64,
 248 #else
 249     TCG_TYPE_TL = TCG_TYPE_I32,
 250 #endif
 251 } TCGType;
 252
 253 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 254 typedef enum TCGMemOp {
 255     MO_8     = 0,
 256     MO_16    = 1,
 257     MO_32    = 2,
 258     MO_64    = 3,
 259     MO_SIZE  = 3,   /* Mask for the above.  */
 260
 261     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 262
 263     MO_BSWAP = 8,   /* Host reverse endian.  */
 264 #ifdef HOST_WORDS_BIGENDIAN
 265     MO_LE    = MO_BSWAP,
 266     MO_BE    = 0,
 267 #else
 268     MO_LE    = 0,
 269     MO_BE    = MO_BSWAP,
 270 #endif
 271 #ifdef TARGET_WORDS_BIGENDIAN
 272     MO_TE    = MO_BE,
 273 #else
 274     MO_TE    = MO_LE,
 275 #endif
 276
 277     /* MO_UNALN accesses are never checked for alignment.
 278        MO_ALIGN accesses will result in a call to the CPU's
 279        do_unaligned_access hook if the guest address is not aligned.
 280        The default depends on whether the target CPU defines ALIGNED_ONLY.  */
 281     MO_AMASK = 16,
 282 #ifdef ALIGNED_ONLY
 283     MO_ALIGN = 0,
 284     MO_UNALN = MO_AMASK,
 285 #else
 286     MO_ALIGN = MO_AMASK,
 287     MO_UNALN = 0,
 288 #endif
 289
 290     /* Combinations of the above, for ease of use.  */
 291     MO_UB    = MO_8,
 292     MO_UW    = MO_16,
 293     MO_UL    = MO_32,
 294     MO_SB    = MO_SIGN | MO_8,
 295     MO_SW    = MO_SIGN | MO_16,
 296     MO_SL    = MO_SIGN | MO_32,
 297     MO_Q     = MO_64,
 298
 299     MO_LEUW  = MO_LE | MO_UW,
 300     MO_LEUL  = MO_LE | MO_UL,
 301     MO_LESW  = MO_LE | MO_SW,
 302     MO_LESL  = MO_LE | MO_SL,
 303     MO_LEQ   = MO_LE | MO_Q,
 304
 305     MO_BEUW  = MO_BE | MO_UW,
 306     MO_BEUL  = MO_BE | MO_UL,
 307     MO_BESW  = MO_BE | MO_SW,
 308     MO_BESL  = MO_BE | MO_SL,
 309     MO_BEQ   = MO_BE | MO_Q,
 310
 311     MO_TEUW  = MO_TE | MO_UW,
 312     MO_TEUL  = MO_TE | MO_UL,
 313     MO_TESW  = MO_TE | MO_SW,
 314     MO_TESL  = MO_TE | MO_SL,
 315     MO_TEQ   = MO_TE | MO_Q,
 316
 317     MO_SSIZE = MO_SIZE | MO_SIGN,
 318 } TCGMemOp;
 319
 320 typedef tcg_target_ulong TCGArg;
 321
 322 /* Define a type and accessor macros for variables.  Using pointer types
 323    is nice because it gives some level of type safely.  Converting to and
 324    from intptr_t rather than int reduces the number of sign-extension
 325    instructions that get implied on 64-bit hosts.  Users of tcg_gen_* don't
 326    need to know about any of this, and should treat TCGv as an opaque type.
 327    In addition we do typechecking for different types of variables.  TCGv_i32
 328    and TCGv_i64 are 32/64-bit variables respectively.  TCGv and TCGv_ptr
 329    are aliases for target_ulong and host pointer sized values respectively.  */
 330
 331 typedef struct TCGv_i32_d *TCGv_i32;
 332 typedef struct TCGv_i64_d *TCGv_i64;
 333 typedef struct TCGv_ptr_d *TCGv_ptr;
 334 typedef TCGv_ptr TCGv_env;
 335 #if TARGET_LONG_BITS == 32
 336 #define TCGv TCGv_i32
 337 #elif TARGET_LONG_BITS == 64
 338 #define TCGv TCGv_i64
 339 #else
 340 #error Unhandled TARGET_LONG_BITS value
 341 #endif
 342
 343 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
 344 {
 345     return (TCGv_i32)i;
 346 }
 347
 348 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
 349 {
 350     return (TCGv_i64)i;
 351 }
 352
 353 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
 354 {
 355     return (TCGv_ptr)i;
 356 }
 357
 358 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
 359 {
 360     return (intptr_t)t;
 361 }
 362
 363 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
 364 {
 365     return (intptr_t)t;
 366 }
 367
 368 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 369 {
 370     return (intptr_t)t;
 371 }
 372
 373 #if TCG_TARGET_REG_BITS == 32
 374 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
 375 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
 376 #endif
 377
 378 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
 379 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
 380 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
 381
 382 /* Dummy definition to avoid compiler warnings.  */
 383 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
 384 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
 385 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
 386
 387 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
 388 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
 389 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
 390
 391 /* call flags */
 392 /* Helper does not read globals (either directly or through an exception). It
 393    implies TCG_CALL_NO_WRITE_GLOBALS. */
 394 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 395 /* Helper does not write globals */
 396 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 397 /* Helper can be safely suppressed if the return value is not used. */
 398 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 399
 400 /* convenience version of most used call flags */
 401 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 402 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 403 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 404 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 405 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 406
 407 /* used to align parameters */
 408 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 409 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 410
 411 /* Conditions.  Note that these are laid out for easy manipulation by
 412    the functions below:
 413      bit 0 is used for inverting;
 414      bit 1 is signed,
 415      bit 2 is unsigned,
 416      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 417 typedef enum {
 418     /* non-signed */
 419     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 420     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 421     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 422     TCG_COND_NE     = 8 | 0 | 0 | 1,
 423     /* signed */
 424     TCG_COND_LT     = 0 | 0 | 2 | 0,
 425     TCG_COND_GE     = 0 | 0 | 2 | 1,
 426     TCG_COND_LE     = 8 | 0 | 2 | 0,
 427     TCG_COND_GT     = 8 | 0 | 2 | 1,
 428     /* unsigned */
 429     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 430     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 431     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 432     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 433 } TCGCond;
 434
 435 /* Invert the sense of the comparison.  */
 436 static inline TCGCond tcg_invert_cond(TCGCond c)
 437 {
 438     return (TCGCond)(c ^ 1);
 439 }
 440
 441 /* Swap the operands in a comparison.  */
 442 static inline TCGCond tcg_swap_cond(TCGCond c)
 443 {
 444     return c & 6 ? (TCGCond)(c ^ 9) : c;
 445 }
 446
 447 /* Create an "unsigned" version of a "signed" comparison.  */
 448 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 449 {
 450     return c & 2 ? (TCGCond)(c ^ 6) : c;
 451 }
 452
 453 /* Must a comparison be considered unsigned?  */
 454 static inline bool is_unsigned_cond(TCGCond c)
 455 {
 456     return (c & 4) != 0;
 457 }
 458
 459 /* Create a "high" version of a double-word comparison.
 460    This removes equality from a LTE or GTE comparison.  */
 461 static inline TCGCond tcg_high_cond(TCGCond c)
 462 {
 463     switch (c) {
 464     case TCG_COND_GE:
 465     case TCG_COND_LE:
 466     case TCG_COND_GEU:
 467     case TCG_COND_LEU:
 468         return (TCGCond)(c ^ 8);
 469     default:
 470         return c;
 471     }
 472 }
 473
 474 typedef enum TCGTempVal {
 475     TEMP_VAL_DEAD,
 476     TEMP_VAL_REG,
 477     TEMP_VAL_MEM,
 478     TEMP_VAL_CONST,
 479 } TCGTempVal;
 480
 481 typedef struct TCGTemp {
 482     TCGReg reg:8;
 483     TCGTempVal val_type:8;
 484     TCGType base_type:8;
 485     TCGType type:8;
 486     unsigned int fixed_reg:1;
 487     unsigned int indirect_reg:1;
 488     unsigned int indirect_base:1;
 489     unsigned int mem_coherent:1;
 490     unsigned int mem_allocated:1;
 491     unsigned int temp_local:1; /* If true, the temp is saved across
 492                                   basic blocks. Otherwise, it is not
 493                                   preserved across basic blocks. */
 494     unsigned int temp_allocated:1; /* never used for code gen */
 495
 496     tcg_target_long val;
 497     struct TCGTemp *mem_base;
 498     intptr_t mem_offset;
 499     const char *name;
 500 } TCGTemp;
 501
 502 typedef struct TCGContext TCGContext;
 503
 504 typedef struct TCGTempSet {
 505     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 506 } TCGTempSet;
 507
 508 typedef struct TCGOp {
 509     TCGOpcode opc   : 8;
 510
 511     /* The number of out and in parameter for a call.  */
 512     unsigned callo  : 2;
 513     unsigned calli  : 6;
 514
 515     /* Index of the arguments for this op, or -1 for zero-operand ops.  */
 516     signed args     : 16;
 517
 518     /* Index of the prex/next op, or -1 for the end of the list.  */
 519     signed prev     : 16;
 520     signed next     : 16;
 521 } TCGOp;
 522
 523 QEMU_BUILD_BUG_ON(NB_OPS > 0xff);
 524 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE >= 0x7fff);
 525 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE >= 0x7fff);
 526
 527 struct TCGContext {
 528     uint8_t *pool_cur, *pool_end;
 529     TCGPool *pool_first, *pool_current, *pool_first_large;
 530     int nb_labels;
 531     int nb_globals;
 532     int nb_temps;
 533
 534     /* goto_tb support */
 535     tcg_insn_unit *code_buf;
 536     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 537     uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */
 538     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */
 539
 540     /* liveness analysis */
 541     uint16_t *op_dead_args; /* for each operation, each bit tells if the
 542                                corresponding argument is dead */
 543     uint8_t *op_sync_args;  /* for each operation, each bit tells if the
 544                                corresponding output argument needs to be
 545                                sync to memory. */
 546
 547     TCGRegSet reserved_regs;
 548     intptr_t current_frame_offset;
 549     intptr_t frame_start;
 550     intptr_t frame_end;
 551     TCGTemp *frame_temp;
 552
 553     tcg_insn_unit *code_ptr;
 554
 555     GHashTable *helpers;
 556
 557 #ifdef CONFIG_PROFILER
 558     /* profiling info */
 559     int64_t tb_count1;
 560     int64_t tb_count;
 561     int64_t op_count; /* total insn count */
 562     int op_count_max; /* max insn per TB */
 563     int64_t temp_count;
 564     int temp_count_max;
 565     int64_t del_op_count;
 566     int64_t code_in_len;
 567     int64_t code_out_len;
 568     int64_t search_out_len;
 569     int64_t interm_time;
 570     int64_t code_time;
 571     int64_t la_time;
 572     int64_t opt_time;
 573     int64_t restore_count;
 574     int64_t restore_time;
 575 #endif
 576
 577 #ifdef CONFIG_DEBUG_TCG
 578     int temps_in_use;
 579     int goto_tb_issue_mask;
 580 #endif
 581
 582     int gen_first_op_idx;
 583     int gen_last_op_idx;
 584     int gen_next_op_idx;
 585     int gen_next_parm_idx;
 586
 587     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 588        here, because there's too much arithmetic throughout that relies
 589        on addition and subtraction working on bytes.  Rely on the GCC
 590        extension that allows arithmetic on void*.  */
 591     int code_gen_max_blocks;
 592     void *code_gen_prologue;
 593     void *code_gen_buffer;
 594     size_t code_gen_buffer_size;
 595     void *code_gen_ptr;
 596
 597     /* Threshold to flush the translated code buffer.  */
 598     void *code_gen_highwater;
 599
 600     TBContext tb_ctx;
 601
 602     /* Track which vCPU triggers events */
 603     CPUState *cpu;                      /* *_trans */
 604     TCGv_env tcg_env;                   /* *_exec  */
 605
 606     /* The TCGBackendData structure is private to tcg-target.inc.c.  */
 607     struct TCGBackendData *be;
 608
 609     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 610     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 611
 612     /* Tells which temporary holds a given register.
 613        It does not take into account fixed registers */
 614     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 615
 616     TCGOp gen_op_buf[OPC_BUF_SIZE];
 617     TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
 618
 619     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 620     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 621 };
 622
 623 extern TCGContext tcg_ctx;
 624
 625 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
 626 {
 627     int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
 628     tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
 629 }
 630
 631 /* The number of opcodes emitted so far.  */
 632 static inline int tcg_op_buf_count(void)
 633 {
 634     return tcg_ctx.gen_next_op_idx;
 635 }
 636
 637 /* Test for whether to terminate the TB for using too many opcodes.  */
 638 static inline bool tcg_op_buf_full(void)
 639 {
 640     return tcg_op_buf_count() >= OPC_MAX_SIZE;
 641 }
 642
 643 /* pool based memory allocation */
 644
 645 void *tcg_malloc_internal(TCGContext *s, int size);
 646 void tcg_pool_reset(TCGContext *s);
 647 void tcg_pool_delete(TCGContext *s);
 648
 649 void tb_lock(void);
 650 void tb_unlock(void);
 651 void tb_lock_reset(void);
 652
 653 static inline void *tcg_malloc(int size)
 654 {
 655     TCGContext *s = &tcg_ctx;
 656     uint8_t *ptr, *ptr_end;
 657     size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
 658     ptr = s->pool_cur;
 659     ptr_end = ptr + size;
 660     if (unlikely(ptr_end > s->pool_end)) {
 661         return tcg_malloc_internal(&tcg_ctx, size);
 662     } else {
 663         s->pool_cur = ptr_end;
 664         return ptr;
 665     }
 666 }
 667
 668 void tcg_context_init(TCGContext *s);
 669 void tcg_prologue_init(TCGContext *s);
 670 void tcg_func_start(TCGContext *s);
 671
 672 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 673
 674 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 675
 676 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
 677
 678 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
 679 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
 680
 681 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 682 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 683
 684 void tcg_temp_free_i32(TCGv_i32 arg);
 685 void tcg_temp_free_i64(TCGv_i64 arg);
 686
 687 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 688                                               const char *name)
 689 {
 690     int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 691     return MAKE_TCGV_I32(idx);
 692 }
 693
 694 static inline TCGv_i32 tcg_temp_new_i32(void)
 695 {
 696     return tcg_temp_new_internal_i32(0);
 697 }
 698
 699 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 700 {
 701     return tcg_temp_new_internal_i32(1);
 702 }
 703
 704 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 705                                               const char *name)
 706 {
 707     int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 708     return MAKE_TCGV_I64(idx);
 709 }
 710
 711 static inline TCGv_i64 tcg_temp_new_i64(void)
 712 {
 713     return tcg_temp_new_internal_i64(0);
 714 }
 715
 716 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 717 {
 718     return tcg_temp_new_internal_i64(1);
 719 }
 720
 721 #if defined(CONFIG_DEBUG_TCG)
 722 /* If you call tcg_clear_temp_count() at the start of a section of
 723  * code which is not supposed to leak any TCG temporaries, then
 724  * calling tcg_check_temp_count() at the end of the section will
 725  * return 1 if the section did in fact leak a temporary.
 726  */
 727 void tcg_clear_temp_count(void);
 728 int tcg_check_temp_count(void);
 729 #else
 730 #define tcg_clear_temp_count() do { } while (0)
 731 #define tcg_check_temp_count() 0
 732 #endif
 733
 734 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 735 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 736
 737 #define TCG_CT_ALIAS  0x80
 738 #define TCG_CT_IALIAS 0x40
 739 #define TCG_CT_REG    0x01
 740 #define TCG_CT_CONST  0x02 /* any constant of register size */
 741
 742 typedef struct TCGArgConstraint {
 743     uint16_t ct;
 744     uint8_t alias_index;
 745     union {
 746         TCGRegSet regs;
 747     } u;
 748 } TCGArgConstraint;
 749
 750 #define TCG_MAX_OP_ARGS 16
 751
 752 /* Bits for TCGOpDef->flags, 8 bits available.  */
 753 enum {
 754     /* Instruction defines the end of a basic block.  */
 755     TCG_OPF_BB_END       = 0x01,
 756     /* Instruction clobbers call registers and potentially update globals.  */
 757     TCG_OPF_CALL_CLOBBER = 0x02,
 758     /* Instruction has side effects: it cannot be removed if its outputs
 759        are not used, and might trigger exceptions.  */
 760     TCG_OPF_SIDE_EFFECTS = 0x04,
 761     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 762     TCG_OPF_64BIT        = 0x08,
 763     /* Instruction is optional and not implemented by the host, or insn
 764        is generic and should not be implemened by the host.  */
 765     TCG_OPF_NOT_PRESENT  = 0x10,
 766 };
 767
 768 typedef struct TCGOpDef {
 769     const char *name;
 770     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 771     uint8_t flags;
 772     TCGArgConstraint *args_ct;
 773     int *sorted_args;
 774 #if defined(CONFIG_DEBUG_TCG)
 775     int used;
 776 #endif
 777 } TCGOpDef;
 778
 779 extern TCGOpDef tcg_op_defs[];
 780 extern const size_t tcg_op_defs_max;
 781
 782 typedef struct TCGTargetOpDef {
 783     TCGOpcode op;
 784     const char *args_ct_str[TCG_MAX_OP_ARGS];
 785 } TCGTargetOpDef;
 786
 787 #define tcg_abort() \
 788 do {\
 789     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 790     abort();\
 791 } while (0)
 792
 793 #ifdef CONFIG_DEBUG_TCG
 794 # define tcg_debug_assert(X) do { assert(X); } while (0)
 795 #elif QEMU_GNUC_PREREQ(4, 5)
 796 # define tcg_debug_assert(X) \
 797     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 798 #else
 799 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 800 #endif
 801
 802 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
 803
 804 #if UINTPTR_MAX == UINT32_MAX
 805 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
 806 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
 807
 808 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
 809 #define tcg_global_reg_new_ptr(R, N) \
 810     TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
 811 #define tcg_global_mem_new_ptr(R, O, N) \
 812     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
 813 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
 814 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
 815 #else
 816 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
 817 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
 818
 819 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
 820 #define tcg_global_reg_new_ptr(R, N) \
 821     TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
 822 #define tcg_global_mem_new_ptr(R, O, N) \
 823     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
 824 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
 825 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
 826 #endif
 827
 828 void tcg_gen_callN(TCGContext *s, void *func,
 829                    TCGArg ret, int nargs, TCGArg *args);
 830
 831 void tcg_op_remove(TCGContext *s, TCGOp *op);
 832 void tcg_optimize(TCGContext *s);
 833
 834 /* only used for debugging purposes */
 835 void tcg_dump_ops(TCGContext *s);
 836
 837 void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf);
 838 TCGv_i32 tcg_const_i32(int32_t val);
 839 TCGv_i64 tcg_const_i64(int64_t val);
 840 TCGv_i32 tcg_const_local_i32(int32_t val);
 841 TCGv_i64 tcg_const_local_i64(int64_t val);
 842
 843 TCGLabel *gen_new_label(void);
 844
 845 /**
 846  * label_arg
 847  * @l: label
 848  *
 849  * Encode a label for storage in the TCG opcode stream.
 850  */
 851
 852 static inline TCGArg label_arg(TCGLabel *l)
 853 {
 854     return (uintptr_t)l;
 855 }
 856
 857 /**
 858  * arg_label
 859  * @i: value
 860  *
 861  * The opposite of label_arg.  Retrieve a label from the
 862  * encoding of the TCG opcode stream.
 863  */
 864
 865 static inline TCGLabel *arg_label(TCGArg i)
 866 {
 867     return (TCGLabel *)(uintptr_t)i;
 868 }
 869
 870 /**
 871  * tcg_ptr_byte_diff
 872  * @a, @b: addresses to be differenced
 873  *
 874  * There are many places within the TCG backends where we need a byte
 875  * difference between two pointers.  While this can be accomplished
 876  * with local casting, it's easy to get wrong -- especially if one is
 877  * concerned with the signedness of the result.
 878  *
 879  * This version relies on GCC's void pointer arithmetic to get the
 880  * correct result.
 881  */
 882
 883 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
 884 {
 885     return a - b;
 886 }
 887
 888 /**
 889  * tcg_pcrel_diff
 890  * @s: the tcg context
 891  * @target: address of the target
 892  *
 893  * Produce a pc-relative difference, from the current code_ptr
 894  * to the destination address.
 895  */
 896
 897 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
 898 {
 899     return tcg_ptr_byte_diff(target, s->code_ptr);
 900 }
 901
 902 /**
 903  * tcg_current_code_size
 904  * @s: the tcg context
 905  *
 906  * Compute the current code size within the translation block.
 907  * This is used to fill in qemu's data structures for goto_tb.
 908  */
 909
 910 static inline size_t tcg_current_code_size(TCGContext *s)
 911 {
 912     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
 913 }
 914
 915 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
 916 typedef uint32_t TCGMemOpIdx;
 917
 918 /**
 919  * make_memop_idx
 920  * @op: memory operation
 921  * @idx: mmu index
 922  *
 923  * Encode these values into a single parameter.
 924  */
 925 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
 926 {
 927     tcg_debug_assert(idx <= 15);
 928     return (op << 4) | idx;
 929 }
 930
 931 /**
 932  * get_memop
 933  * @oi: combined op/idx parameter
 934  *
 935  * Extract the memory operation from the combined value.
 936  */
 937 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
 938 {
 939     return oi >> 4;
 940 }
 941
 942 /**
 943  * get_mmuidx
 944  * @oi: combined op/idx parameter
 945  *
 946  * Extract the mmu index from the combined value.
 947  */
 948 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
 949 {
 950     return oi & 15;
 951 }
 952
 953 /**
 954  * tcg_qemu_tb_exec:
 955  * @env: pointer to CPUArchState for the CPU
 956  * @tb_ptr: address of generated code for the TB to execute
 957  *
 958  * Start executing code from a given translation block.
 959  * Where translation blocks have been linked, execution
 960  * may proceed from the given TB into successive ones.
 961  * Control eventually returns only when some action is needed
 962  * from the top-level loop: either control must pass to a TB
 963  * which has not yet been directly linked, or an asynchronous
 964  * event such as an interrupt needs handling.
 965  *
 966  * Return: The return value is the value passed to the corresponding
 967  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
 968  * The value is either zero or a 4-byte aligned pointer to that TB combined
 969  * with additional information in its two least significant bits. The
 970  * additional information is encoded as follows:
 971  *  0, 1: the link between this TB and the next is via the specified
 972  *        TB index (0 or 1). That is, we left the TB via (the equivalent
 973  *        of) "goto_tb <index>". The main loop uses this to determine
 974  *        how to link the TB just executed to the next.
 975  *  2:    we are using instruction counting code generation, and we
 976  *        did not start executing this TB because the instruction counter
 977  *        would hit zero midway through it. In this case the pointer
 978  *        returned is the TB we were about to execute, and the caller must
 979  *        arrange to execute the remaining count of instructions.
 980  *  3:    we stopped because the CPU's exit_request flag was set
 981  *        (usually meaning that there is an interrupt that needs to be
 982  *        handled). The pointer returned is the TB we were about to execute
 983  *        when we noticed the pending exit request.
 984  *
 985  * If the bottom two bits indicate an exit-via-index then the CPU
 986  * state is correctly synchronised and ready for execution of the next
 987  * TB (and in particular the guest PC is the address to execute next).
 988  * Otherwise, we gave up on execution of this TB before it started, and
 989  * the caller must fix up the CPU state by calling the CPU's
 990  * synchronize_from_tb() method with the TB pointer we return (falling
 991  * back to calling the CPU's set_pc method with tb->pb if no
 992  * synchronize_from_tb() method exists).
 993  *
 994  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
 995  * to this default (which just calls the prologue.code emitted by
 996  * tcg_target_qemu_prologue()).
 997  */
 998 #define TB_EXIT_MASK 3
 999 #define TB_EXIT_IDX0 0
1000 #define TB_EXIT_IDX1 1
1001 #define TB_EXIT_ICOUNT_EXPIRED 2
1002 #define TB_EXIT_REQUESTED 3
1003
1004 #ifdef HAVE_TCG_QEMU_TB_EXEC
1005 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1006 #else
1007 # define tcg_qemu_tb_exec(env, tb_ptr) \
1008     ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
1009 #endif
1010
1011 void tcg_register_jit(void *buf, size_t buf_size);
1012
1013 /*
1014  * Memory helpers that will be used by TCG generated code.
1015  */
1016 #ifdef CONFIG_SOFTMMU
1017 /* Value zero-extended to tcg register size.  */
1018 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1019                                      TCGMemOpIdx oi, uintptr_t retaddr);
1020 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1021                                     TCGMemOpIdx oi, uintptr_t retaddr);
1022 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1023                                     TCGMemOpIdx oi, uintptr_t retaddr);
1024 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1025                            TCGMemOpIdx oi, uintptr_t retaddr);
1026 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1027                                     TCGMemOpIdx oi, uintptr_t retaddr);
1028 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1029                                     TCGMemOpIdx oi, uintptr_t retaddr);
1030 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1031                            TCGMemOpIdx oi, uintptr_t retaddr);
1032
1033 /* Value sign-extended to tcg register size.  */
1034 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1035                                      TCGMemOpIdx oi, uintptr_t retaddr);
1036 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1037                                     TCGMemOpIdx oi, uintptr_t retaddr);
1038 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1039                                     TCGMemOpIdx oi, uintptr_t retaddr);
1040 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1041                                     TCGMemOpIdx oi, uintptr_t retaddr);
1042 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1043                                     TCGMemOpIdx oi, uintptr_t retaddr);
1044
1045 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1046                         TCGMemOpIdx oi, uintptr_t retaddr);
1047 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1048                        TCGMemOpIdx oi, uintptr_t retaddr);
1049 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1050                        TCGMemOpIdx oi, uintptr_t retaddr);
1051 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1052                        TCGMemOpIdx oi, uintptr_t retaddr);
1053 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1054                        TCGMemOpIdx oi, uintptr_t retaddr);
1055 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1056                        TCGMemOpIdx oi, uintptr_t retaddr);
1057 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1058                        TCGMemOpIdx oi, uintptr_t retaddr);
1059
1060 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1061                             TCGMemOpIdx oi, uintptr_t retaddr);
1062 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1063                             TCGMemOpIdx oi, uintptr_t retaddr);
1064 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1065                             TCGMemOpIdx oi, uintptr_t retaddr);
1066 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1067                             TCGMemOpIdx oi, uintptr_t retaddr);
1068 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1069                             TCGMemOpIdx oi, uintptr_t retaddr);
1070 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1071                             TCGMemOpIdx oi, uintptr_t retaddr);
1072 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1073                             TCGMemOpIdx oi, uintptr_t retaddr);
1074
1075 /* Temporary aliases until backends are converted.  */
1076 #ifdef TARGET_WORDS_BIGENDIAN
1077 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1078 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1079 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1080 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1081 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1082 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1083 # define helper_ret_stw_mmu   helper_be_stw_mmu
1084 # define helper_ret_stl_mmu   helper_be_stl_mmu
1085 # define helper_ret_stq_mmu   helper_be_stq_mmu
1086 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1087 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1088 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1089 #else
1090 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1091 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1092 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1093 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1094 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1095 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1096 # define helper_ret_stw_mmu   helper_le_stw_mmu
1097 # define helper_ret_stl_mmu   helper_le_stl_mmu
1098 # define helper_ret_stq_mmu   helper_le_stq_mmu
1099 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1100 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1101 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1102 #endif
1103
1104 #endif /* CONFIG_SOFTMMU */
1105
1106 #endif /* TCG_H */