4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "qemu-common.h"
23 #include "hw/qdev-properties.h"
24 #if !defined(CONFIG_USER_ONLY)
25 #include "hw/loader.h"
27 #include "hw/arm/arm.h"
28 #include "sysemu/sysemu.h"
29 #include "sysemu/kvm.h"
31 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 ARMCPU
*cpu
= ARM_CPU(cs
);
35 cpu
->env
.regs
[15] = value
;
38 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
40 /* Reset a single ARMCPRegInfo register */
41 ARMCPRegInfo
*ri
= value
;
44 if (ri
->type
& ARM_CP_SPECIAL
) {
49 ri
->resetfn(&cpu
->env
, ri
);
53 /* A zero offset is never possible as it would be regs[0]
54 * so we use it to indicate that reset is being handled elsewhere.
55 * This is basically only used for fields in non-core coprocessors
56 * (like the pxa2xx ones).
58 if (!ri
->fieldoffset
) {
62 if (ri
->type
& ARM_CP_64BIT
) {
63 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
65 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
69 /* CPUClass::reset() */
70 static void arm_cpu_reset(CPUState
*s
)
72 ARMCPU
*cpu
= ARM_CPU(s
);
73 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
74 CPUARMState
*env
= &cpu
->env
;
78 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
79 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
80 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
81 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
82 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
84 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
85 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
88 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
89 /* 64 bit CPUs always start in 64 bit mode */
93 #if defined(CONFIG_USER_ONLY)
94 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
95 /* For user mode we must enable access to coprocessors */
96 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
97 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
98 env
->cp15
.c15_cpar
= 3;
99 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
100 env
->cp15
.c15_cpar
= 1;
103 /* SVC mode with interrupts disabled. */
104 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
105 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
106 clear at reset. Initial SP and PC are loaded from ROM. */
110 env
->uncached_cpsr
&= ~CPSR_I
;
113 /* We should really use ldl_phys here, in case the guest
114 modified flash and reset itself. However images
115 loaded via -kernel have not been copied yet, so load the
116 values directly from there. */
117 env
->regs
[13] = ldl_p(rom
) & 0xFFFFFFFC;
120 env
->regs
[15] = pc
& ~1;
123 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
125 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
126 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
127 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
128 set_float_detect_tininess(float_tininess_before_rounding
,
129 &env
->vfp
.fp_status
);
130 set_float_detect_tininess(float_tininess_before_rounding
,
131 &env
->vfp
.standard_fp_status
);
133 /* Reset is a state change for some CPUARMState fields which we
134 * bake assumptions about into translated code, so we need to
140 #ifndef CONFIG_USER_ONLY
141 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
143 ARMCPU
*cpu
= opaque
;
144 CPUState
*cs
= CPU(cpu
);
149 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
151 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
156 cpu_interrupt(cs
, CPU_INTERRUPT_FIQ
);
158 cpu_reset_interrupt(cs
, CPU_INTERRUPT_FIQ
);
162 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq
);
166 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
169 ARMCPU
*cpu
= opaque
;
170 CPUState
*cs
= CPU(cpu
);
171 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
175 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
178 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
181 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq
);
183 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
184 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
189 static inline void set_feature(CPUARMState
*env
, int feature
)
191 env
->features
|= 1ULL << feature
;
194 static void arm_cpu_initfn(Object
*obj
)
196 CPUState
*cs
= CPU(obj
);
197 ARMCPU
*cpu
= ARM_CPU(obj
);
200 cs
->env_ptr
= &cpu
->env
;
201 cpu_exec_init(&cpu
->env
);
202 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
205 #ifndef CONFIG_USER_ONLY
206 /* Our inbound IRQ and FIQ lines */
208 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 2);
210 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 2);
213 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
214 arm_gt_ptimer_cb
, cpu
);
215 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
216 arm_gt_vtimer_cb
, cpu
);
217 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
218 ARRAY_SIZE(cpu
->gt_timer_outputs
));
221 /* DTB consumers generally don't in fact care what the 'compatible'
222 * string is, so always provide some string and trust that a hypothetical
223 * picky DTB consumer will also provide a helpful error message.
225 cpu
->dtb_compatible
= "qemu,unknown";
227 if (tcg_enabled() && !inited
) {
229 arm_translate_init();
233 static void arm_cpu_finalizefn(Object
*obj
)
235 ARMCPU
*cpu
= ARM_CPU(obj
);
236 g_hash_table_destroy(cpu
->cp_regs
);
239 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
241 CPUState
*cs
= CPU(dev
);
242 ARMCPU
*cpu
= ARM_CPU(dev
);
243 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
244 CPUARMState
*env
= &cpu
->env
;
246 /* Some features automatically imply others: */
247 if (arm_feature(env
, ARM_FEATURE_V8
)) {
248 set_feature(env
, ARM_FEATURE_V7
);
249 set_feature(env
, ARM_FEATURE_ARM_DIV
);
250 set_feature(env
, ARM_FEATURE_LPAE
);
252 if (arm_feature(env
, ARM_FEATURE_V7
)) {
253 set_feature(env
, ARM_FEATURE_VAPA
);
254 set_feature(env
, ARM_FEATURE_THUMB2
);
255 set_feature(env
, ARM_FEATURE_MPIDR
);
256 if (!arm_feature(env
, ARM_FEATURE_M
)) {
257 set_feature(env
, ARM_FEATURE_V6K
);
259 set_feature(env
, ARM_FEATURE_V6
);
262 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
263 set_feature(env
, ARM_FEATURE_V6
);
264 set_feature(env
, ARM_FEATURE_MVFR
);
266 if (arm_feature(env
, ARM_FEATURE_V6
)) {
267 set_feature(env
, ARM_FEATURE_V5
);
268 if (!arm_feature(env
, ARM_FEATURE_M
)) {
269 set_feature(env
, ARM_FEATURE_AUXCR
);
272 if (arm_feature(env
, ARM_FEATURE_V5
)) {
273 set_feature(env
, ARM_FEATURE_V4T
);
275 if (arm_feature(env
, ARM_FEATURE_M
)) {
276 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
278 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
279 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
281 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
282 set_feature(env
, ARM_FEATURE_VFP3
);
284 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
285 set_feature(env
, ARM_FEATURE_VFP
);
287 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
288 set_feature(env
, ARM_FEATURE_V7MP
);
289 set_feature(env
, ARM_FEATURE_PXN
);
292 register_cp_regs_for_features(cpu
);
293 arm_cpu_register_gdb_regs_for_features(cpu
);
295 init_cpreg_list(cpu
);
300 acc
->parent_realize(dev
, errp
);
303 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
312 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpu_model
);
313 oc
= object_class_by_name(typename
);
315 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
316 object_class_is_abstract(oc
)) {
322 /* CPU models. These are not needed for the AArch64 linux-user build. */
323 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
325 static void arm926_initfn(Object
*obj
)
327 ARMCPU
*cpu
= ARM_CPU(obj
);
329 cpu
->dtb_compatible
= "arm,arm926";
330 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
331 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
332 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
333 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
334 cpu
->midr
= 0x41069265;
335 cpu
->reset_fpsid
= 0x41011090;
336 cpu
->ctr
= 0x1dd20d2;
337 cpu
->reset_sctlr
= 0x00090078;
340 static void arm946_initfn(Object
*obj
)
342 ARMCPU
*cpu
= ARM_CPU(obj
);
344 cpu
->dtb_compatible
= "arm,arm946";
345 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
346 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
347 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
348 cpu
->midr
= 0x41059461;
349 cpu
->ctr
= 0x0f004006;
350 cpu
->reset_sctlr
= 0x00000078;
353 static void arm1026_initfn(Object
*obj
)
355 ARMCPU
*cpu
= ARM_CPU(obj
);
357 cpu
->dtb_compatible
= "arm,arm1026";
358 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
359 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
360 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
361 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
362 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
363 cpu
->midr
= 0x4106a262;
364 cpu
->reset_fpsid
= 0x410110a0;
365 cpu
->ctr
= 0x1dd20d2;
366 cpu
->reset_sctlr
= 0x00090078;
367 cpu
->reset_auxcr
= 1;
369 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
370 ARMCPRegInfo ifar
= {
371 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
373 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
376 define_one_arm_cp_reg(cpu
, &ifar
);
380 static void arm1136_r2_initfn(Object
*obj
)
382 ARMCPU
*cpu
= ARM_CPU(obj
);
383 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
384 * older core than plain "arm1136". In particular this does not
385 * have the v6K features.
386 * These ID register values are correct for 1136 but may be wrong
387 * for 1136_r2 (in particular r0p2 does not actually implement most
388 * of the ID registers).
391 cpu
->dtb_compatible
= "arm,arm1136";
392 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
393 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
394 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
395 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
396 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
397 cpu
->midr
= 0x4107b362;
398 cpu
->reset_fpsid
= 0x410120b4;
399 cpu
->mvfr0
= 0x11111111;
400 cpu
->mvfr1
= 0x00000000;
401 cpu
->ctr
= 0x1dd20d2;
402 cpu
->reset_sctlr
= 0x00050078;
403 cpu
->id_pfr0
= 0x111;
407 cpu
->id_mmfr0
= 0x01130003;
408 cpu
->id_mmfr1
= 0x10030302;
409 cpu
->id_mmfr2
= 0x01222110;
410 cpu
->id_isar0
= 0x00140011;
411 cpu
->id_isar1
= 0x12002111;
412 cpu
->id_isar2
= 0x11231111;
413 cpu
->id_isar3
= 0x01102131;
414 cpu
->id_isar4
= 0x141;
415 cpu
->reset_auxcr
= 7;
418 static void arm1136_initfn(Object
*obj
)
420 ARMCPU
*cpu
= ARM_CPU(obj
);
422 cpu
->dtb_compatible
= "arm,arm1136";
423 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
424 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
425 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
426 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
427 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
428 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
429 cpu
->midr
= 0x4117b363;
430 cpu
->reset_fpsid
= 0x410120b4;
431 cpu
->mvfr0
= 0x11111111;
432 cpu
->mvfr1
= 0x00000000;
433 cpu
->ctr
= 0x1dd20d2;
434 cpu
->reset_sctlr
= 0x00050078;
435 cpu
->id_pfr0
= 0x111;
439 cpu
->id_mmfr0
= 0x01130003;
440 cpu
->id_mmfr1
= 0x10030302;
441 cpu
->id_mmfr2
= 0x01222110;
442 cpu
->id_isar0
= 0x00140011;
443 cpu
->id_isar1
= 0x12002111;
444 cpu
->id_isar2
= 0x11231111;
445 cpu
->id_isar3
= 0x01102131;
446 cpu
->id_isar4
= 0x141;
447 cpu
->reset_auxcr
= 7;
450 static void arm1176_initfn(Object
*obj
)
452 ARMCPU
*cpu
= ARM_CPU(obj
);
454 cpu
->dtb_compatible
= "arm,arm1176";
455 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
456 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
457 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
458 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
459 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
460 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
461 cpu
->midr
= 0x410fb767;
462 cpu
->reset_fpsid
= 0x410120b5;
463 cpu
->mvfr0
= 0x11111111;
464 cpu
->mvfr1
= 0x00000000;
465 cpu
->ctr
= 0x1dd20d2;
466 cpu
->reset_sctlr
= 0x00050078;
467 cpu
->id_pfr0
= 0x111;
471 cpu
->id_mmfr0
= 0x01130003;
472 cpu
->id_mmfr1
= 0x10030302;
473 cpu
->id_mmfr2
= 0x01222100;
474 cpu
->id_isar0
= 0x0140011;
475 cpu
->id_isar1
= 0x12002111;
476 cpu
->id_isar2
= 0x11231121;
477 cpu
->id_isar3
= 0x01102131;
478 cpu
->id_isar4
= 0x01141;
479 cpu
->reset_auxcr
= 7;
482 static void arm11mpcore_initfn(Object
*obj
)
484 ARMCPU
*cpu
= ARM_CPU(obj
);
486 cpu
->dtb_compatible
= "arm,arm11mpcore";
487 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
488 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
489 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
490 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
491 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
492 cpu
->midr
= 0x410fb022;
493 cpu
->reset_fpsid
= 0x410120b4;
494 cpu
->mvfr0
= 0x11111111;
495 cpu
->mvfr1
= 0x00000000;
496 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
497 cpu
->id_pfr0
= 0x111;
501 cpu
->id_mmfr0
= 0x01100103;
502 cpu
->id_mmfr1
= 0x10020302;
503 cpu
->id_mmfr2
= 0x01222000;
504 cpu
->id_isar0
= 0x00100011;
505 cpu
->id_isar1
= 0x12002111;
506 cpu
->id_isar2
= 0x11221011;
507 cpu
->id_isar3
= 0x01102131;
508 cpu
->id_isar4
= 0x141;
509 cpu
->reset_auxcr
= 1;
512 static void cortex_m3_initfn(Object
*obj
)
514 ARMCPU
*cpu
= ARM_CPU(obj
);
515 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
516 set_feature(&cpu
->env
, ARM_FEATURE_M
);
517 cpu
->midr
= 0x410fc231;
520 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
522 #ifndef CONFIG_USER_ONLY
523 CPUClass
*cc
= CPU_CLASS(oc
);
525 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
529 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
530 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
531 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
532 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
533 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
537 static void cortex_a8_initfn(Object
*obj
)
539 ARMCPU
*cpu
= ARM_CPU(obj
);
541 cpu
->dtb_compatible
= "arm,cortex-a8";
542 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
543 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
544 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
545 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
546 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
547 cpu
->midr
= 0x410fc080;
548 cpu
->reset_fpsid
= 0x410330c0;
549 cpu
->mvfr0
= 0x11110222;
550 cpu
->mvfr1
= 0x00011100;
551 cpu
->ctr
= 0x82048004;
552 cpu
->reset_sctlr
= 0x00c50078;
553 cpu
->id_pfr0
= 0x1031;
555 cpu
->id_dfr0
= 0x400;
557 cpu
->id_mmfr0
= 0x31100003;
558 cpu
->id_mmfr1
= 0x20000000;
559 cpu
->id_mmfr2
= 0x01202000;
560 cpu
->id_mmfr3
= 0x11;
561 cpu
->id_isar0
= 0x00101111;
562 cpu
->id_isar1
= 0x12112111;
563 cpu
->id_isar2
= 0x21232031;
564 cpu
->id_isar3
= 0x11112131;
565 cpu
->id_isar4
= 0x00111142;
566 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
567 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
568 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
569 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
570 cpu
->reset_auxcr
= 2;
571 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
574 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
575 /* power_control should be set to maximum latency. Again,
576 * default to 0 and set by private hook
578 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
579 .access
= PL1_RW
, .resetvalue
= 0,
580 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
581 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
582 .access
= PL1_RW
, .resetvalue
= 0,
583 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
584 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
585 .access
= PL1_RW
, .resetvalue
= 0,
586 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
587 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
588 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
589 /* TLB lockdown control */
590 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
591 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
592 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
593 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
594 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
595 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
596 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
597 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
598 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
599 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
603 static void cortex_a9_initfn(Object
*obj
)
605 ARMCPU
*cpu
= ARM_CPU(obj
);
607 cpu
->dtb_compatible
= "arm,cortex-a9";
608 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
609 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
610 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
611 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
612 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
613 /* Note that A9 supports the MP extensions even for
614 * A9UP and single-core A9MP (which are both different
615 * and valid configurations; we don't model A9UP).
617 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
618 cpu
->midr
= 0x410fc090;
619 cpu
->reset_fpsid
= 0x41033090;
620 cpu
->mvfr0
= 0x11110222;
621 cpu
->mvfr1
= 0x01111111;
622 cpu
->ctr
= 0x80038003;
623 cpu
->reset_sctlr
= 0x00c50078;
624 cpu
->id_pfr0
= 0x1031;
626 cpu
->id_dfr0
= 0x000;
628 cpu
->id_mmfr0
= 0x00100103;
629 cpu
->id_mmfr1
= 0x20000000;
630 cpu
->id_mmfr2
= 0x01230000;
631 cpu
->id_mmfr3
= 0x00002111;
632 cpu
->id_isar0
= 0x00101111;
633 cpu
->id_isar1
= 0x13112111;
634 cpu
->id_isar2
= 0x21232041;
635 cpu
->id_isar3
= 0x11112131;
636 cpu
->id_isar4
= 0x00111142;
637 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
638 cpu
->ccsidr
[0] = 0xe00fe015; /* 16k L1 dcache. */
639 cpu
->ccsidr
[1] = 0x200fe015; /* 16k L1 icache. */
641 ARMCPRegInfo cbar
= {
642 .name
= "CBAR", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4,
643 .opc2
= 0, .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
644 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_config_base_address
)
646 define_one_arm_cp_reg(cpu
, &cbar
);
647 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
651 #ifndef CONFIG_USER_ONLY
652 static int a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
655 /* Linux wants the number of processors from here.
656 * Might as well set the interrupt-controller bit too.
658 *value
= ((smp_cpus
- 1) << 24) | (1 << 23);
663 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
664 #ifndef CONFIG_USER_ONLY
665 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
666 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
667 .writefn
= arm_cp_write_ignore
, },
669 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
670 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
674 static void cortex_a15_initfn(Object
*obj
)
676 ARMCPU
*cpu
= ARM_CPU(obj
);
678 cpu
->dtb_compatible
= "arm,cortex-a15";
679 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
680 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
681 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
682 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
683 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
684 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
685 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
686 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
687 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
688 cpu
->midr
= 0x412fc0f1;
689 cpu
->reset_fpsid
= 0x410430f0;
690 cpu
->mvfr0
= 0x10110222;
691 cpu
->mvfr1
= 0x11111111;
692 cpu
->ctr
= 0x8444c004;
693 cpu
->reset_sctlr
= 0x00c50078;
694 cpu
->id_pfr0
= 0x00001131;
695 cpu
->id_pfr1
= 0x00011011;
696 cpu
->id_dfr0
= 0x02010555;
697 cpu
->id_afr0
= 0x00000000;
698 cpu
->id_mmfr0
= 0x10201105;
699 cpu
->id_mmfr1
= 0x20000000;
700 cpu
->id_mmfr2
= 0x01240000;
701 cpu
->id_mmfr3
= 0x02102211;
702 cpu
->id_isar0
= 0x02101110;
703 cpu
->id_isar1
= 0x13112111;
704 cpu
->id_isar2
= 0x21232041;
705 cpu
->id_isar3
= 0x11112131;
706 cpu
->id_isar4
= 0x10011142;
707 cpu
->clidr
= 0x0a200023;
708 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
709 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
710 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
711 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
714 static void ti925t_initfn(Object
*obj
)
716 ARMCPU
*cpu
= ARM_CPU(obj
);
717 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
718 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
719 cpu
->midr
= ARM_CPUID_TI925T
;
720 cpu
->ctr
= 0x5109149;
721 cpu
->reset_sctlr
= 0x00000070;
724 static void sa1100_initfn(Object
*obj
)
726 ARMCPU
*cpu
= ARM_CPU(obj
);
728 cpu
->dtb_compatible
= "intel,sa1100";
729 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
730 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
731 cpu
->midr
= 0x4401A11B;
732 cpu
->reset_sctlr
= 0x00000070;
735 static void sa1110_initfn(Object
*obj
)
737 ARMCPU
*cpu
= ARM_CPU(obj
);
738 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
739 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
740 cpu
->midr
= 0x6901B119;
741 cpu
->reset_sctlr
= 0x00000070;
744 static void pxa250_initfn(Object
*obj
)
746 ARMCPU
*cpu
= ARM_CPU(obj
);
748 cpu
->dtb_compatible
= "marvell,xscale";
749 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
750 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
751 cpu
->midr
= 0x69052100;
752 cpu
->ctr
= 0xd172172;
753 cpu
->reset_sctlr
= 0x00000078;
756 static void pxa255_initfn(Object
*obj
)
758 ARMCPU
*cpu
= ARM_CPU(obj
);
760 cpu
->dtb_compatible
= "marvell,xscale";
761 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
762 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
763 cpu
->midr
= 0x69052d00;
764 cpu
->ctr
= 0xd172172;
765 cpu
->reset_sctlr
= 0x00000078;
768 static void pxa260_initfn(Object
*obj
)
770 ARMCPU
*cpu
= ARM_CPU(obj
);
772 cpu
->dtb_compatible
= "marvell,xscale";
773 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
774 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
775 cpu
->midr
= 0x69052903;
776 cpu
->ctr
= 0xd172172;
777 cpu
->reset_sctlr
= 0x00000078;
780 static void pxa261_initfn(Object
*obj
)
782 ARMCPU
*cpu
= ARM_CPU(obj
);
784 cpu
->dtb_compatible
= "marvell,xscale";
785 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
786 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
787 cpu
->midr
= 0x69052d05;
788 cpu
->ctr
= 0xd172172;
789 cpu
->reset_sctlr
= 0x00000078;
792 static void pxa262_initfn(Object
*obj
)
794 ARMCPU
*cpu
= ARM_CPU(obj
);
796 cpu
->dtb_compatible
= "marvell,xscale";
797 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
798 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
799 cpu
->midr
= 0x69052d06;
800 cpu
->ctr
= 0xd172172;
801 cpu
->reset_sctlr
= 0x00000078;
804 static void pxa270a0_initfn(Object
*obj
)
806 ARMCPU
*cpu
= ARM_CPU(obj
);
808 cpu
->dtb_compatible
= "marvell,xscale";
809 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
810 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
811 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
812 cpu
->midr
= 0x69054110;
813 cpu
->ctr
= 0xd172172;
814 cpu
->reset_sctlr
= 0x00000078;
817 static void pxa270a1_initfn(Object
*obj
)
819 ARMCPU
*cpu
= ARM_CPU(obj
);
821 cpu
->dtb_compatible
= "marvell,xscale";
822 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
823 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
824 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
825 cpu
->midr
= 0x69054111;
826 cpu
->ctr
= 0xd172172;
827 cpu
->reset_sctlr
= 0x00000078;
830 static void pxa270b0_initfn(Object
*obj
)
832 ARMCPU
*cpu
= ARM_CPU(obj
);
834 cpu
->dtb_compatible
= "marvell,xscale";
835 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
836 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
837 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
838 cpu
->midr
= 0x69054112;
839 cpu
->ctr
= 0xd172172;
840 cpu
->reset_sctlr
= 0x00000078;
843 static void pxa270b1_initfn(Object
*obj
)
845 ARMCPU
*cpu
= ARM_CPU(obj
);
847 cpu
->dtb_compatible
= "marvell,xscale";
848 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
849 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
850 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
851 cpu
->midr
= 0x69054113;
852 cpu
->ctr
= 0xd172172;
853 cpu
->reset_sctlr
= 0x00000078;
856 static void pxa270c0_initfn(Object
*obj
)
858 ARMCPU
*cpu
= ARM_CPU(obj
);
860 cpu
->dtb_compatible
= "marvell,xscale";
861 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
862 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
863 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
864 cpu
->midr
= 0x69054114;
865 cpu
->ctr
= 0xd172172;
866 cpu
->reset_sctlr
= 0x00000078;
869 static void pxa270c5_initfn(Object
*obj
)
871 ARMCPU
*cpu
= ARM_CPU(obj
);
873 cpu
->dtb_compatible
= "marvell,xscale";
874 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
875 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
876 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
877 cpu
->midr
= 0x69054117;
878 cpu
->ctr
= 0xd172172;
879 cpu
->reset_sctlr
= 0x00000078;
882 #ifdef CONFIG_USER_ONLY
883 static void arm_any_initfn(Object
*obj
)
885 ARMCPU
*cpu
= ARM_CPU(obj
);
886 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
887 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
888 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
889 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
890 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
891 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
892 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
893 #ifdef TARGET_AARCH64
894 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
896 cpu
->midr
= 0xffffffff;
900 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
902 typedef struct ARMCPUInfo
{
904 void (*initfn
)(Object
*obj
);
905 void (*class_init
)(ObjectClass
*oc
, void *data
);
908 static const ARMCPUInfo arm_cpus
[] = {
909 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
910 { .name
= "arm926", .initfn
= arm926_initfn
},
911 { .name
= "arm946", .initfn
= arm946_initfn
},
912 { .name
= "arm1026", .initfn
= arm1026_initfn
},
913 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
914 * older core than plain "arm1136". In particular this does not
915 * have the v6K features.
917 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
918 { .name
= "arm1136", .initfn
= arm1136_initfn
},
919 { .name
= "arm1176", .initfn
= arm1176_initfn
},
920 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
921 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
922 .class_init
= arm_v7m_class_init
},
923 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
924 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
925 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
926 { .name
= "ti925t", .initfn
= ti925t_initfn
},
927 { .name
= "sa1100", .initfn
= sa1100_initfn
},
928 { .name
= "sa1110", .initfn
= sa1110_initfn
},
929 { .name
= "pxa250", .initfn
= pxa250_initfn
},
930 { .name
= "pxa255", .initfn
= pxa255_initfn
},
931 { .name
= "pxa260", .initfn
= pxa260_initfn
},
932 { .name
= "pxa261", .initfn
= pxa261_initfn
},
933 { .name
= "pxa262", .initfn
= pxa262_initfn
},
934 /* "pxa270" is an alias for "pxa270-a0" */
935 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
936 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
937 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
938 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
939 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
940 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
941 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
942 #ifdef CONFIG_USER_ONLY
943 { .name
= "any", .initfn
= arm_any_initfn
},
948 static Property arm_cpu_properties
[] = {
949 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
950 DEFINE_PROP_END_OF_LIST()
953 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
955 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
956 CPUClass
*cc
= CPU_CLASS(acc
);
957 DeviceClass
*dc
= DEVICE_CLASS(oc
);
959 acc
->parent_realize
= dc
->realize
;
960 dc
->realize
= arm_cpu_realizefn
;
961 dc
->props
= arm_cpu_properties
;
963 acc
->parent_reset
= cc
->reset
;
964 cc
->reset
= arm_cpu_reset
;
966 cc
->class_by_name
= arm_cpu_class_by_name
;
967 cc
->do_interrupt
= arm_cpu_do_interrupt
;
968 cc
->dump_state
= arm_cpu_dump_state
;
969 cc
->set_pc
= arm_cpu_set_pc
;
970 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
971 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
972 #ifndef CONFIG_USER_ONLY
973 cc
->get_phys_page_debug
= arm_cpu_get_phys_page_debug
;
974 cc
->vmsd
= &vmstate_arm_cpu
;
976 cc
->gdb_num_core_regs
= 26;
977 cc
->gdb_core_xml_file
= "arm-core.xml";
980 static void cpu_register(const ARMCPUInfo
*info
)
982 TypeInfo type_info
= {
983 .parent
= TYPE_ARM_CPU
,
984 .instance_size
= sizeof(ARMCPU
),
985 .instance_init
= info
->initfn
,
986 .class_size
= sizeof(ARMCPUClass
),
987 .class_init
= info
->class_init
,
990 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
991 type_register(&type_info
);
992 g_free((void *)type_info
.name
);
995 static const TypeInfo arm_cpu_type_info
= {
996 .name
= TYPE_ARM_CPU
,
998 .instance_size
= sizeof(ARMCPU
),
999 .instance_init
= arm_cpu_initfn
,
1000 .instance_finalize
= arm_cpu_finalizefn
,
1002 .class_size
= sizeof(ARMCPUClass
),
1003 .class_init
= arm_cpu_class_init
,
1006 static void arm_cpu_register_types(void)
1010 type_register_static(&arm_cpu_type_info
);
1011 for (i
= 0; i
< ARRAY_SIZE(arm_cpus
); i
++) {
1012 cpu_register(&arm_cpus
[i
]);
1016 type_init(arm_cpu_register_types
)