target/arm: Reorganize PMCCNTR accesses
[qemu/ar7.git] / hw / misc / mips_cpc.c
blob6d345745f6a47fd0acefe41a716b44e5d04311ce
1 /*
2 * Cluster Power Controller emulation
4 * Copyright (c) 2016 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu/log.h"
24 #include "hw/sysbus.h"
26 #include "hw/misc/mips_cpc.h"
28 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
30 return (1ULL << cpc->num_vp) - 1;
33 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
35 CPUState *cs = first_cpu;
37 CPU_FOREACH(cs) {
38 uint64_t i = 1ULL << cs->cpu_index;
39 if (i & vp_run & ~cpc->vp_running) {
40 cpu_reset(cs);
41 cpc->vp_running |= i;
46 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
48 CPUState *cs = first_cpu;
50 CPU_FOREACH(cs) {
51 uint64_t i = 1ULL << cs->cpu_index;
52 if (i & vp_stop & cpc->vp_running) {
53 cpu_interrupt(cs, CPU_INTERRUPT_HALT);
54 cpc->vp_running &= ~i;
59 static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
60 unsigned size)
62 MIPSCPCState *s = opaque;
64 switch (offset) {
65 case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
66 case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
67 cpc_run_vp(s, data & cpc_vp_run_mask(s));
68 break;
69 case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
70 case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
71 cpc_stop_vp(s, data & cpc_vp_run_mask(s));
72 break;
73 default:
74 qemu_log_mask(LOG_UNIMP,
75 "%s: Bad offset 0x%x\n", __func__, (int)offset);
76 break;
79 return;
82 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
84 MIPSCPCState *s = opaque;
86 switch (offset) {
87 case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
88 case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
89 return s->vp_running;
90 default:
91 qemu_log_mask(LOG_UNIMP,
92 "%s: Bad offset 0x%x\n", __func__, (int)offset);
93 return 0;
97 static const MemoryRegionOps cpc_ops = {
98 .read = cpc_read,
99 .write = cpc_write,
100 .endianness = DEVICE_NATIVE_ENDIAN,
101 .impl = {
102 .max_access_size = 8,
106 static void mips_cpc_init(Object *obj)
108 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
109 MIPSCPCState *s = MIPS_CPC(obj);
111 memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
112 CPC_ADDRSPACE_SZ);
113 sysbus_init_mmio(sbd, &s->mr);
116 static void mips_cpc_realize(DeviceState *dev, Error **errp)
118 MIPSCPCState *s = MIPS_CPC(dev);
120 if (s->vp_start_running > cpc_vp_run_mask(s)) {
121 error_setg(errp,
122 "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
123 s->vp_running, s->num_vp);
124 return;
128 static void mips_cpc_reset(DeviceState *dev)
130 MIPSCPCState *s = MIPS_CPC(dev);
132 /* Reflect the fact that all VPs are halted on reset */
133 s->vp_running = 0;
135 /* Put selected VPs into run state */
136 cpc_run_vp(s, s->vp_start_running);
139 static const VMStateDescription vmstate_mips_cpc = {
140 .name = "mips-cpc",
141 .version_id = 0,
142 .minimum_version_id = 0,
143 .fields = (VMStateField[]) {
144 VMSTATE_UINT64(vp_running, MIPSCPCState),
145 VMSTATE_END_OF_LIST()
149 static Property mips_cpc_properties[] = {
150 DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
151 DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
152 DEFINE_PROP_END_OF_LIST(),
155 static void mips_cpc_class_init(ObjectClass *klass, void *data)
157 DeviceClass *dc = DEVICE_CLASS(klass);
159 dc->realize = mips_cpc_realize;
160 dc->reset = mips_cpc_reset;
161 dc->vmsd = &vmstate_mips_cpc;
162 dc->props = mips_cpc_properties;
165 static const TypeInfo mips_cpc_info = {
166 .name = TYPE_MIPS_CPC,
167 .parent = TYPE_SYS_BUS_DEVICE,
168 .instance_size = sizeof(MIPSCPCState),
169 .instance_init = mips_cpc_init,
170 .class_init = mips_cpc_class_init,
173 static void mips_cpc_register_types(void)
175 type_register_static(&mips_cpc_info);
178 type_init(mips_cpc_register_types)