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spapr_pci: Fix extended config space accesses
[qemu/ar7.git] / disas / cris.c
blob2dd56deea4a860fe5a824452ac7e2687f5c52ef7
1 /* Disassembler code for CRIS.
2 Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Written by Hans-Peter Nilsson.
5
6 This file is part of the GNU binutils and GDB, the GNU debugger.
7
8 This program is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by the
10 Free Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
20
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "disas/bfd.h"
24 #include "target/cris/opcode-cris.h"
25
26 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
27
28 /* cris-opc.c -- Table of opcodes for the CRIS processor.
29 Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
30 Contributed by Axis Communications AB, Lund, Sweden.
31 Originally written for GAS 1.38.1 by Mikael Asker.
32 Reorganized by Hans-Peter Nilsson.
33
34 This file is part of GAS, GDB and the GNU binutils.
35
36 GAS, GDB, and GNU binutils is free software; you can redistribute it
37 and/or modify it under the terms of the GNU General Public License as
38 published by the Free Software Foundation; either version 2, or (at your
39 option) any later version.
40
41 GAS, GDB, and GNU binutils are distributed in the hope that they will be
42 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
43 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44 GNU General Public License for more details.
45
46 You should have received a copy of the GNU General Public License
47 along with this program; if not, see <http://www.gnu.org/licenses/>. */
48
49 #ifndef NULL
50 #define NULL (0)
51 #endif
52
53 /* This table isn't used for CRISv32 and the size of immediate operands. */
54 const struct cris_spec_reg
55 cris_spec_regs[] =
56 {
57 {"bz", 0, 1, cris_ver_v32p, NULL},
58 {"p0", 0, 1, 0, NULL},
59 {"vr", 1, 1, 0, NULL},
60 {"p1", 1, 1, 0, NULL},
61 {"pid", 2, 1, cris_ver_v32p, NULL},
62 {"p2", 2, 1, cris_ver_v32p, NULL},
63 {"p2", 2, 1, cris_ver_warning, NULL},
64 {"srs", 3, 1, cris_ver_v32p, NULL},
65 {"p3", 3, 1, cris_ver_v32p, NULL},
66 {"p3", 3, 1, cris_ver_warning, NULL},
67 {"wz", 4, 2, cris_ver_v32p, NULL},
68 {"p4", 4, 2, 0, NULL},
69 {"ccr", 5, 2, cris_ver_v0_10, NULL},
70 {"exs", 5, 4, cris_ver_v32p, NULL},
71 {"p5", 5, 2, cris_ver_v0_10, NULL},
72 {"p5", 5, 4, cris_ver_v32p, NULL},
73 {"dcr0",6, 2, cris_ver_v0_3, NULL},
74 {"eda", 6, 4, cris_ver_v32p, NULL},
75 {"p6", 6, 2, cris_ver_v0_3, NULL},
76 {"p6", 6, 4, cris_ver_v32p, NULL},
77 {"dcr1/mof", 7, 4, cris_ver_v10p,
78 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
79 {"dcr1/mof", 7, 2, cris_ver_v0_3,
80 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
81 {"mof", 7, 4, cris_ver_v10p, NULL},
82 {"dcr1",7, 2, cris_ver_v0_3, NULL},
83 {"p7", 7, 4, cris_ver_v10p, NULL},
84 {"p7", 7, 2, cris_ver_v0_3, NULL},
85 {"dz", 8, 4, cris_ver_v32p, NULL},
86 {"p8", 8, 4, 0, NULL},
87 {"ibr", 9, 4, cris_ver_v0_10, NULL},
88 {"ebp", 9, 4, cris_ver_v32p, NULL},
89 {"p9", 9, 4, 0, NULL},
90 {"irp", 10, 4, cris_ver_v0_10, NULL},
91 {"erp", 10, 4, cris_ver_v32p, NULL},
92 {"p10", 10, 4, 0, NULL},
93 {"srp", 11, 4, 0, NULL},
94 {"p11", 11, 4, 0, NULL},
95 /* For disassembly use only. Accept at assembly with a warning. */
96 {"bar/dtp0", 12, 4, cris_ver_warning,
97 "Ambiguous register `bar/dtp0' specified"},
98 {"nrp", 12, 4, cris_ver_v32p, NULL},
99 {"bar", 12, 4, cris_ver_v8_10, NULL},
100 {"dtp0",12, 4, cris_ver_v0_3, NULL},
101 {"p12", 12, 4, 0, NULL},
102 /* For disassembly use only. Accept at assembly with a warning. */
103 {"dccr/dtp1",13, 4, cris_ver_warning,
104 "Ambiguous register `dccr/dtp1' specified"},
105 {"ccs", 13, 4, cris_ver_v32p, NULL},
106 {"dccr",13, 4, cris_ver_v8_10, NULL},
107 {"dtp1",13, 4, cris_ver_v0_3, NULL},
108 {"p13", 13, 4, 0, NULL},
109 {"brp", 14, 4, cris_ver_v3_10, NULL},
110 {"usp", 14, 4, cris_ver_v32p, NULL},
111 {"p14", 14, 4, cris_ver_v3p, NULL},
112 {"usp", 15, 4, cris_ver_v10, NULL},
113 {"spc", 15, 4, cris_ver_v32p, NULL},
114 {"p15", 15, 4, cris_ver_v10p, NULL},
115 {NULL, 0, 0, cris_ver_version_all, NULL}
116 };
117
118 /* Add version specifiers to this table when necessary.
119 The (now) regular coding of register names suggests a simpler
120 implementation. */
121 const struct cris_support_reg cris_support_regs[] =
122 {
123 {"s0", 0},
124 {"s1", 1},
125 {"s2", 2},
126 {"s3", 3},
127 {"s4", 4},
128 {"s5", 5},
129 {"s6", 6},
130 {"s7", 7},
131 {"s8", 8},
132 {"s9", 9},
133 {"s10", 10},
134 {"s11", 11},
135 {"s12", 12},
136 {"s13", 13},
137 {"s14", 14},
138 {"s15", 15},
139 {NULL, 0}
140 };
141
142 /* All CRIS opcodes are 16 bits.
143
144 - The match component is a mask saying which bits must match a
145 particular opcode in order for an instruction to be an instance
146 of that opcode.
147
148 - The args component is a string containing characters symbolically
149 matching the operands of an instruction. Used for both assembly
150 and disassembly.
151
152 Operand-matching characters:
153 [ ] , space
154 Verbatim.
155 A The string "ACR" (case-insensitive).
156 B Not really an operand. It causes a "BDAP -size,SP" prefix to be
157 output for the PUSH alias-instructions and recognizes a push-
158 prefix at disassembly. This letter isn't recognized for v32.
159 Must be followed by a R or P letter.
160 ! Non-match pattern, will not match if there's a prefix insn.
161 b Non-matching operand, used for branches with 16-bit
162 displacement. Only recognized by the disassembler.
163 c 5-bit unsigned immediate in bits <4:0>.
164 C 4-bit unsigned immediate in bits <3:0>.
165 d At assembly, optionally (as in put other cases before this one)
166 ".d" or ".D" at the start of the operands, followed by one space
167 character. At disassembly, nothing.
168 D General register in bits <15:12> and <3:0>.
169 f List of flags in bits <15:12> and <3:0>.
170 i 6-bit signed immediate in bits <5:0>.
171 I 6-bit unsigned immediate in bits <5:0>.
172 M Size modifier (B, W or D) for CLEAR instructions.
173 m Size modifier (B, W or D) in bits <5:4>
174 N A 32-bit dword, like in the difference between s and y.
175 This has no effect on bits in the opcode. Can also be expressed
176 as "[pc+]" in input.
177 n As N, but PC-relative (to the start of the instruction).
178 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
179 branch instructions.
180 O [-128..127] offset in bits <7:0>. Also matches a comma and a
181 general register after the expression, in bits <15:12>. Used
182 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
183 P Special register in bits <15:12>.
184 p Indicates that the insn is a prefix insn. Must be first
185 character.
186 Q As O, but don't relax; force an 8-bit offset.
187 R General register in bits <15:12>.
188 r General register in bits <3:0>.
189 S Source operand in bit <10> and a prefix; a 3-operand prefix
190 without side-effect.
191 s Source operand in bits <10> and <3:0>, optionally with a
192 side-effect prefix, except [pc] (the name, not R15 as in ACR)
193 isn't allowed for v32 and higher.
194 T Support register in bits <15:12>.
195 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
196 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
197 Not recognized at disassembly.
198 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
199 y Like 's' but do not allow an integer at assembly.
200 Y The difference s-y; only an integer is allowed.
201 z Size modifier (B or W) in bit <4>. */
202
203
204 /* Please note the order of the opcodes in this table is significant.
205 The assembler requires that all instances of the same mnemonic must
206 be consecutive. If they aren't, the assembler might not recognize
207 them, or may indicate an internal error.
208
209 The disassembler should not normally care about the order of the
210 opcodes, but will prefer an earlier alternative if the "match-score"
211 (see cris-dis.c) is computed as equal.
212
213 It should not be significant for proper execution that this table is
214 in alphabetical order, but please follow that convention for an easy
215 overview. */
216
217 const struct cris_opcode
218 cris_opcodes[] =
219 {
220 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
221 cris_abs_op},
222
223 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
224 cris_reg_mode_add_sub_cmp_and_or_move_op},
225
226 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
227 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
228
229 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
230 cris_ver_v0_10,
231 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
232
233 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
234 cris_ver_v0_10,
235 cris_three_operand_add_sub_cmp_and_or_op},
236
237 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
238 cris_ver_v32p,
239 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
240
241 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
242 cris_ver_v32p,
243 cris_not_implemented_op},
244
245 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
246 cris_ver_v32p,
247 cris_not_implemented_op},
248
249 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
250 cris_ver_v32p,
251 cris_addi_op},
252
253 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
254 cris_addi_op},
255
256 /* This collates after "addo", but we want to disassemble as "addoq",
257 not "addo". */
258 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
259 cris_ver_v32p,
260 cris_not_implemented_op},
261
262 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
263 cris_ver_v32p,
264 cris_not_implemented_op},
265
266 /* This must be located after the insn above, lest we misinterpret
267 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
268 parser bug. */
269 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
270 cris_ver_v32p,
271 cris_not_implemented_op},
272
273 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
274 cris_quick_mode_add_sub_op},
275
276 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
277 cris_reg_mode_add_sub_cmp_and_or_move_op},
278
279 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
280 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
281 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
282
283 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
284 cris_ver_v0_10,
285 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
286
287 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
288 cris_ver_v0_10,
289 cris_three_operand_add_sub_cmp_and_or_op},
290
291 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
292 cris_reg_mode_add_sub_cmp_and_or_move_op},
293
294 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
295 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
296 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
297
298 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
299 cris_ver_v0_10,
300 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
301
302 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
303 cris_ver_v0_10,
304 cris_three_operand_add_sub_cmp_and_or_op},
305
306 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
307 cris_reg_mode_add_sub_cmp_and_or_move_op},
308
309 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
310 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
311
312 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
313 cris_ver_v0_10,
314 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
315
316 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
317 cris_ver_v0_10,
318 cris_three_operand_add_sub_cmp_and_or_op},
319
320 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
321 cris_quick_mode_and_cmp_move_or_op},
322
323 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
324 cris_asr_op},
325
326 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
327 cris_asrq_op},
328
329 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
330 cris_ax_ei_setf_op},
331
332 /* FIXME: Should use branch #defines. */
333 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
334 cris_sixteen_bit_offset_branch_op},
335
336 {"ba",
337 BA_QUICK_OPCODE,
338 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
339 cris_eight_bit_offset_branch_op},
340
341 /* Needs to come after the usual "ba o", which might be relaxed to
342 this one. */
343 {"ba", BA_DWORD_OPCODE,
344 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
345 cris_ver_v32p,
346 cris_none_reg_mode_jump_op},
347
348 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
349 cris_ver_v32p,
350 cris_none_reg_mode_jump_op},
351
352 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
353 cris_ver_v32p,
354 cris_none_reg_mode_jump_op},
355
356 {"bcc",
357 BRANCH_QUICK_OPCODE+CC_CC*0x1000,
358 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
359 cris_eight_bit_offset_branch_op},
360
361 {"bcs",
362 BRANCH_QUICK_OPCODE+CC_CS*0x1000,
363 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
364 cris_eight_bit_offset_branch_op},
365
366 {"bdap",
367 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
368 cris_ver_v0_10,
369 cris_bdap_prefix},
370
371 {"bdap",
372 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
373 cris_ver_v0_10,
374 cris_quick_mode_bdap_prefix},
375
376 {"beq",
377 BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
378 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
379 cris_eight_bit_offset_branch_op},
380
381 /* This is deliberately put before "bext" to trump it, even though not
382 in alphabetical order, since we don't do excluding version checks
383 for v0..v10. */
384 {"bwf",
385 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
386 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
387 cris_ver_v10,
388 cris_eight_bit_offset_branch_op},
389
390 {"bext",
391 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
392 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
393 cris_ver_v0_3,
394 cris_eight_bit_offset_branch_op},
395
396 {"bge",
397 BRANCH_QUICK_OPCODE+CC_GE*0x1000,
398 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
399 cris_eight_bit_offset_branch_op},
400
401 {"bgt",
402 BRANCH_QUICK_OPCODE+CC_GT*0x1000,
403 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
404 cris_eight_bit_offset_branch_op},
405
406 {"bhi",
407 BRANCH_QUICK_OPCODE+CC_HI*0x1000,
408 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
409 cris_eight_bit_offset_branch_op},
410
411 {"bhs",
412 BRANCH_QUICK_OPCODE+CC_HS*0x1000,
413 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
414 cris_eight_bit_offset_branch_op},
415
416 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
417 cris_ver_v0_10,
418 cris_biap_prefix},
419
420 {"ble",
421 BRANCH_QUICK_OPCODE+CC_LE*0x1000,
422 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
423 cris_eight_bit_offset_branch_op},
424
425 {"blo",
426 BRANCH_QUICK_OPCODE+CC_LO*0x1000,
427 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
428 cris_eight_bit_offset_branch_op},
429
430 {"bls",
431 BRANCH_QUICK_OPCODE+CC_LS*0x1000,
432 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
433 cris_eight_bit_offset_branch_op},
434
435 {"blt",
436 BRANCH_QUICK_OPCODE+CC_LT*0x1000,
437 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
438 cris_eight_bit_offset_branch_op},
439
440 {"bmi",
441 BRANCH_QUICK_OPCODE+CC_MI*0x1000,
442 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
443 cris_eight_bit_offset_branch_op},
444
445 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
446 cris_ver_sim_v0_10,
447 cris_not_implemented_op},
448
449 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
450 cris_ver_sim_v0_10,
451 cris_not_implemented_op},
452
453 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
454 cris_ver_sim_v0_10,
455 cris_not_implemented_op},
456
457 {"bne",
458 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
459 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
460 cris_eight_bit_offset_branch_op},
461
462 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
463 cris_two_operand_bound_op},
464 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
465 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
466 cris_ver_v0_10,
467 cris_two_operand_bound_op},
468 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
469 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
470 cris_two_operand_bound_op},
471 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
472 cris_ver_v0_10,
473 cris_two_operand_bound_op},
474 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
475 cris_ver_v0_10,
476 cris_three_operand_bound_op},
477
478 {"bpl",
479 BRANCH_QUICK_OPCODE+CC_PL*0x1000,
480 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
481 cris_eight_bit_offset_branch_op},
482
483 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
484 cris_ver_v3p,
485 cris_break_op},
486
487 {"bsb",
488 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
489 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
490 cris_ver_v32p,
491 cris_eight_bit_offset_branch_op},
492
493 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
494 cris_ver_v32p,
495 cris_none_reg_mode_jump_op},
496
497 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
498 cris_ver_v32p,
499 cris_none_reg_mode_jump_op},
500
501 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
502 cris_ver_warning,
503 cris_not_implemented_op},
504
505 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
506 cris_ver_warning,
507 cris_not_implemented_op},
508
509 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
510 cris_ver_warning,
511 cris_not_implemented_op},
512
513 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
514 cris_btst_nop_op},
515 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
516 cris_btst_nop_op},
517
518 {"bvc",
519 BRANCH_QUICK_OPCODE+CC_VC*0x1000,
520 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
521 cris_eight_bit_offset_branch_op},
522
523 {"bvs",
524 BRANCH_QUICK_OPCODE+CC_VS*0x1000,
525 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
526 cris_eight_bit_offset_branch_op},
527
528 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
529 cris_reg_mode_clear_op},
530
531 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
532 cris_none_reg_mode_clear_test_op},
533
534 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
535 cris_ver_v0_10,
536 cris_none_reg_mode_clear_test_op},
537
538 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
539 cris_clearf_di_op},
540
541 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
542 cris_reg_mode_add_sub_cmp_and_or_move_op},
543
544 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
545 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
546
547 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
548 cris_ver_v0_10,
549 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
550
551 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
552 cris_quick_mode_and_cmp_move_or_op},
553
554 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
555 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
556 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
557
558 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
559 cris_ver_v0_10,
560 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
561
562 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
563 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
564 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
565
566 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
567 cris_ver_v0_10,
568 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
569
570 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
571 cris_clearf_di_op},
572
573 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
574 cris_ver_v0_10,
575 cris_dip_prefix},
576
577 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
578 cris_not_implemented_op},
579
580 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
581 cris_dstep_logshift_mstep_neg_not_op},
582
583 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
584 cris_ax_ei_setf_op},
585
586 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
587 cris_ver_v32p,
588 cris_not_implemented_op},
589
590 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
591 cris_ver_v32p,
592 cris_not_implemented_op},
593
594 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
595 cris_ver_v32p,
596 cris_not_implemented_op},
597
598 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
599 cris_ver_v32p,
600 cris_not_implemented_op},
601
602 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
603 cris_ver_v32p,
604 cris_not_implemented_op},
605
606 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
607 cris_ver_v32p,
608 cris_reg_mode_jump_op},
609
610 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
611 cris_ver_v32p,
612 cris_reg_mode_jump_op},
613
614 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
615 cris_ver_v32p,
616 cris_reg_mode_jump_op},
617
618 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
619 cris_ver_v32p,
620 cris_reg_mode_jump_op},
621
622 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
623 cris_ver_v8_10,
624 cris_reg_mode_jump_op},
625
626 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
627 cris_ver_v8_10,
628 cris_none_reg_mode_jump_op},
629
630 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
631 cris_ver_v8_10,
632 cris_none_reg_mode_jump_op},
633
634 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
635 cris_ver_v8_10,
636 cris_reg_mode_jump_op},
637
638 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
639 cris_ver_v8_10,
640 cris_none_reg_mode_jump_op},
641
642 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
643 cris_ver_v8_10,
644 cris_none_reg_mode_jump_op},
645
646 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
647 cris_ver_v8_10,
648 cris_reg_mode_jump_op},
649
650 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
651 cris_ver_v8_10,
652 cris_none_reg_mode_jump_op},
653
654 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
655 cris_ver_v8_10,
656 cris_none_reg_mode_jump_op},
657
658 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
659 cris_reg_mode_jump_op},
660
661 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
662 cris_ver_v0_10,
663 cris_none_reg_mode_jump_op},
664
665 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
666 cris_ver_v32p,
667 cris_none_reg_mode_jump_op},
668
669 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
670 cris_ver_v0_10,
671 cris_none_reg_mode_jump_op},
672
673 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
674 cris_ver_v8_10,
675 cris_reg_mode_jump_op},
676
677 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
678 cris_ver_v8_10,
679 cris_none_reg_mode_jump_op},
680
681 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
682 cris_ver_v8_10,
683 cris_none_reg_mode_jump_op},
684
685 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
686 cris_ver_v32p,
687 cris_reg_mode_jump_op},
688
689 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
690 cris_ver_v32p,
691 cris_reg_mode_jump_op},
692
693 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
694 cris_reg_mode_jump_op},
695
696 {"jump",
697 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
698 cris_ver_v0_10,
699 cris_none_reg_mode_jump_op},
700
701 {"jump",
702 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
703 cris_ver_v0_10,
704 cris_none_reg_mode_jump_op},
705
706 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
707 cris_ver_v32p,
708 cris_none_reg_mode_jump_op},
709
710 {"jump",
711 JUMP_PC_INCR_OPCODE_V32,
712 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
713 cris_ver_v32p,
714 cris_none_reg_mode_jump_op},
715
716 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
717 cris_ver_v10,
718 cris_none_reg_mode_jump_op},
719
720 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
721 cris_ver_v10,
722 cris_none_reg_mode_jump_op},
723
724 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
725 cris_ver_v32p,
726 cris_not_implemented_op},
727
728 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
729 cris_ver_v32p,
730 cris_not_implemented_op},
731
732 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
733 cris_ver_v32p,
734 cris_addi_op},
735
736 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
737 cris_dstep_logshift_mstep_neg_not_op},
738
739 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
740 cris_dstep_logshift_mstep_neg_not_op},
741
742 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
743 cris_dstep_logshift_mstep_neg_not_op},
744
745 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
746 cris_dstep_logshift_mstep_neg_not_op},
747
748 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
749 cris_ver_v3p,
750 cris_not_implemented_op},
751
752 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
753 cris_ver_v32p,
754 cris_not_implemented_op},
755
756 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
757 cris_reg_mode_add_sub_cmp_and_or_move_op},
758
759 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
760 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
761
762 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
763 cris_ver_v0_10,
764 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
765
766 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
767 cris_move_to_preg_op},
768
769 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
770 cris_reg_mode_move_from_preg_op},
771
772 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
773 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
774
775 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
776 cris_ver_v0_10,
777 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
778
779 {"move",
780 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
781 "s,P", 0, SIZE_SPEC_REG, 0,
782 cris_move_to_preg_op},
783
784 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
785 cris_ver_v0_10,
786 cris_move_to_preg_op},
787
788 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
789 cris_none_reg_mode_move_from_preg_op},
790
791 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
792 cris_ver_v0_10,
793 cris_none_reg_mode_move_from_preg_op},
794
795 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
796 cris_ver_v32p,
797 cris_not_implemented_op},
798
799 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
800 cris_ver_v32p,
801 cris_not_implemented_op},
802
803 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
804 cris_move_reg_to_mem_movem_op},
805
806 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
807 cris_ver_v0_10,
808 cris_move_reg_to_mem_movem_op},
809
810 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
811 cris_move_mem_to_reg_movem_op},
812
813 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
814 cris_ver_v0_10,
815 cris_move_mem_to_reg_movem_op},
816
817 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
818 cris_quick_mode_and_cmp_move_or_op},
819
820 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
821 cris_reg_mode_add_sub_cmp_and_or_move_op},
822
823 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
824 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
825 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
826
827 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
828 cris_ver_v0_10,
829 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
830
831 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
832 cris_reg_mode_add_sub_cmp_and_or_move_op},
833
834 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
835 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
836 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
837
838 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
839 cris_ver_v0_10,
840 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
841
842 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
843 cris_ver_v0_10,
844 cris_dstep_logshift_mstep_neg_not_op},
845
846 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
847 cris_ver_v10p,
848 cris_muls_op},
849
850 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
851 cris_ver_v10p,
852 cris_mulu_op},
853
854 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
855 cris_dstep_logshift_mstep_neg_not_op},
856
857 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
858 cris_ver_v0_10,
859 cris_btst_nop_op},
860
861 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
862 cris_ver_v32p,
863 cris_btst_nop_op},
864
865 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
866 cris_dstep_logshift_mstep_neg_not_op},
867
868 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
869 cris_reg_mode_add_sub_cmp_and_or_move_op},
870
871 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
872 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
873
874 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
875 cris_ver_v0_10,
876 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
877
878 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
879 cris_ver_v0_10,
880 cris_three_operand_add_sub_cmp_and_or_op},
881
882 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
883 cris_quick_mode_and_cmp_move_or_op},
884
885 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
886 cris_ver_v0_10,
887 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
888
889 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
890 cris_ver_v0_10,
891 cris_none_reg_mode_move_from_preg_op},
892
893 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
894 cris_ver_v0_10,
895 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
896
897 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
898 cris_ver_v0_10,
899 cris_move_to_preg_op},
900
901 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
902 cris_ver_v10,
903 cris_not_implemented_op},
904
905 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
906 cris_ver_v10,
907 cris_not_implemented_op},
908
909 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
910 cris_ver_v32p,
911 cris_not_implemented_op},
912
913 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
914 cris_ver_v32p,
915 cris_not_implemented_op},
916
917 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
918 cris_ver_v32p,
919 cris_not_implemented_op},
920
921 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
922 cris_ver_v0_10,
923 cris_reg_mode_move_from_preg_op},
924
925 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
926 cris_ver_v32p,
927 cris_reg_mode_move_from_preg_op},
928
929 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
930 cris_ver_v0_10,
931 cris_reg_mode_move_from_preg_op},
932
933 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
934 cris_ver_v32p,
935 cris_reg_mode_move_from_preg_op},
936
937 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
938 cris_ver_v0_10,
939 cris_reg_mode_move_from_preg_op},
940
941 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
942 cris_ver_v32p,
943 cris_reg_mode_move_from_preg_op},
944
945 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
946 cris_ver_v10,
947 cris_not_implemented_op},
948
949 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
950 cris_ver_v10,
951 cris_not_implemented_op},
952
953 {"sa",
954 0x0530+CC_A*0x1000,
955 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
956 cris_scc_op},
957
958 {"ssb",
959 0x0530+CC_EXT*0x1000,
960 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
961 cris_ver_v32p,
962 cris_scc_op},
963
964 {"scc",
965 0x0530+CC_CC*0x1000,
966 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
967 cris_scc_op},
968
969 {"scs",
970 0x0530+CC_CS*0x1000,
971 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
972 cris_scc_op},
973
974 {"seq",
975 0x0530+CC_EQ*0x1000,
976 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
977 cris_scc_op},
978
979 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
980 cris_ax_ei_setf_op},
981
982 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
983 cris_ver_v32p,
984 cris_not_implemented_op},
985
986 /* Need to have "swf" in front of "sext" so it is the one displayed in
987 disassembly. */
988 {"swf",
989 0x0530+CC_EXT*0x1000,
990 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
991 cris_ver_v10,
992 cris_scc_op},
993
994 {"sext",
995 0x0530+CC_EXT*0x1000,
996 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
997 cris_ver_v0_3,
998 cris_scc_op},
999
1000 {"sge",
1001 0x0530+CC_GE*0x1000,
1002 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
1003 cris_scc_op},
1004
1005 {"sgt",
1006 0x0530+CC_GT*0x1000,
1007 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
1008 cris_scc_op},
1009
1010 {"shi",
1011 0x0530+CC_HI*0x1000,
1012 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
1013 cris_scc_op},
1014
1015 {"shs",
1016 0x0530+CC_HS*0x1000,
1017 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
1018 cris_scc_op},
1019
1020 {"sle",
1021 0x0530+CC_LE*0x1000,
1022 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
1023 cris_scc_op},
1024
1025 {"slo",
1026 0x0530+CC_LO*0x1000,
1027 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
1028 cris_scc_op},
1029
1030 {"sls",
1031 0x0530+CC_LS*0x1000,
1032 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
1033 cris_scc_op},
1034
1035 {"slt",
1036 0x0530+CC_LT*0x1000,
1037 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
1038 cris_scc_op},
1039
1040 {"smi",
1041 0x0530+CC_MI*0x1000,
1042 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
1043 cris_scc_op},
1044
1045 {"sne",
1046 0x0530+CC_NE*0x1000,
1047 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
1048 cris_scc_op},
1049
1050 {"spl",
1051 0x0530+CC_PL*0x1000,
1052 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
1053 cris_scc_op},
1054
1055 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
1056 cris_reg_mode_add_sub_cmp_and_or_move_op},
1057
1058 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
1059 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1060
1061 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
1062 cris_ver_v0_10,
1063 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1064
1065 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
1066 cris_ver_v0_10,
1067 cris_three_operand_add_sub_cmp_and_or_op},
1068
1069 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
1070 cris_quick_mode_add_sub_op},
1071
1072 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
1073 cris_reg_mode_add_sub_cmp_and_or_move_op},
1074
1075 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
1076 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
1077 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1078
1079 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
1080 cris_ver_v0_10,
1081 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1082
1083 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
1084 cris_ver_v0_10,
1085 cris_three_operand_add_sub_cmp_and_or_op},
1086
1087 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
1088 cris_reg_mode_add_sub_cmp_and_or_move_op},
1089
1090 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
1091 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
1092 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1093
1094 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
1095 cris_ver_v0_10,
1096 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1097
1098 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
1099 cris_ver_v0_10,
1100 cris_three_operand_add_sub_cmp_and_or_op},
1101
1102 {"svc",
1103 0x0530+CC_VC*0x1000,
1104 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
1105 cris_scc_op},
1106
1107 {"svs",
1108 0x0530+CC_VS*0x1000,
1109 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
1110 cris_scc_op},
1111
1112 /* The insn "swapn" is the same as "not" and will be disassembled as
1113 such, but the swap* family of mnmonics are generally v8-and-higher
1114 only, so count it in. */
1115 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
1116 cris_ver_v8p,
1117 cris_not_implemented_op},
1118
1119 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
1120 cris_ver_v8p,
1121 cris_not_implemented_op},
1122
1123 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
1124 cris_ver_v8p,
1125 cris_not_implemented_op},
1126
1127 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
1128 cris_ver_v8p,
1129 cris_not_implemented_op},
1130
1131 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
1132 cris_ver_v8p,
1133 cris_not_implemented_op},
1134
1135 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
1136 cris_ver_v8p,
1137 cris_not_implemented_op},
1138
1139 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
1140 cris_ver_v8p,
1141 cris_not_implemented_op},
1142
1143 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
1144 cris_ver_v8p,
1145 cris_not_implemented_op},
1146
1147 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
1148 cris_ver_v8p,
1149 cris_not_implemented_op},
1150
1151 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
1152 cris_ver_v8p,
1153 cris_not_implemented_op},
1154
1155 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
1156 cris_ver_v8p,
1157 cris_not_implemented_op},
1158
1159 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
1160 cris_ver_v8p,
1161 cris_not_implemented_op},
1162
1163 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
1164 cris_ver_v8p,
1165 cris_not_implemented_op},
1166
1167 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
1168 cris_ver_v8p,
1169 cris_not_implemented_op},
1170
1171 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
1172 cris_ver_v8p,
1173 cris_not_implemented_op},
1174
1175 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
1176 cris_ver_v0_10,
1177 cris_reg_mode_test_op},
1178
1179 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
1180 cris_none_reg_mode_clear_test_op},
1181
1182 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
1183 cris_ver_v0_10,
1184 cris_none_reg_mode_clear_test_op},
1185
1186 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
1187 cris_xor_op},
1188
1189 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1190 };
1191
1192 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1193 const char * const
1194 cris_cc_strings[] =
1195 {
1196 "hs",
1197 "lo",
1198 "ne",
1199 "eq",
1200 "vc",
1201 "vs",
1202 "pl",
1203 "mi",
1204 "ls",
1205 "hi",
1206 "ge",
1207 "lt",
1208 "gt",
1209 "le",
1210 "a",
1211 /* This is a placeholder. In v0, this would be "ext". In v32, this
1212 is "sb". */
1213 "wf"
1214 };
1215
1216 /*
1217 * Local variables:
1218 * eval: (c-set-style "gnu")
1219 * indent-tabs-mode: t
1220 * End:
1221 */
1222
1223
1224 /* No instruction will be disassembled longer than this. In theory, and
1225 in silicon, address prefixes can be cascaded. In practice, cascading
1226 is not used by GCC, and not supported by the assembler. */
1227 #ifndef MAX_BYTES_PER_CRIS_INSN
1228 #define MAX_BYTES_PER_CRIS_INSN 8
1229 #endif
1230
1231 /* Whether or not to decode prefixes, folding it into the following
1232 instruction. FIXME: Make this optional later. */
1233 #ifndef PARSE_PREFIX
1234 #define PARSE_PREFIX 1
1235 #endif
1236
1237 /* Sometimes we prefix all registers with this character. */
1238 #define REGISTER_PREFIX_CHAR '$'
1239
1240 /* Whether or not to trace the following sequence:
1241 sub* X,r%d
1242 bound* Y,r%d
1243 adds.w [pc+r%d.w],pc
1244
1245 This is the assembly form of a switch-statement in C.
1246 The "sub is optional. If there is none, then X will be zero.
1247 X is the value of the first case,
1248 Y is the number of cases (including default).
1249
1250 This results in case offsets printed on the form:
1251 case N: -> case_address
1252 where N is an estimation on the corresponding 'case' operand in C,
1253 and case_address is where execution of that case continues after the
1254 sequence presented above.
1255
1256 The old style of output was to print the offsets as instructions,
1257 which made it hard to follow "case"-constructs in the disassembly,
1258 and caused a lot of annoying warnings about undefined instructions.
1259
1260 FIXME: Make this optional later. */
1261 #ifndef TRACE_CASE
1262 #define TRACE_CASE (disdata->trace_case)
1263 #endif
1264
1265 enum cris_disass_family
1266 { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
1267
1268 /* Stored in the disasm_info->private_data member. */
1269 struct cris_disasm_data
1270 {
1271 /* Whether to print something less confusing if we find something
1272 matching a switch-construct. */
1273 bfd_boolean trace_case;
1274
1275 /* Whether this code is flagged as crisv32. FIXME: Should be an enum
1276 that includes "compatible". */
1277 enum cris_disass_family distype;
1278 };
1279
1280 /* Value of first element in switch. */
1281 static long case_offset = 0;
1282
1283 /* How many more case-offsets to print. */
1284 static long case_offset_counter = 0;
1285
1286 /* Number of case offsets. */
1287 static long no_of_case_offsets = 0;
1288
1289 /* Candidate for next case_offset. */
1290 static long last_immediate = 0;
1291
1292 static int cris_constraint
1293 (const char *, unsigned, unsigned, struct cris_disasm_data *);
1294
1295 /* Parse disassembler options and store state in info. FIXME: For the
1296 time being, we abuse static variables. */
1297
1298 static bfd_boolean
1299 cris_parse_disassembler_options (disassemble_info *info,
1300 enum cris_disass_family distype)
1301 {
1302 struct cris_disasm_data *disdata;
1303
1304 info->private_data = calloc (1, sizeof (struct cris_disasm_data));
1305 disdata = (struct cris_disasm_data *) info->private_data;
1306 if (disdata == NULL)
1307 return false;
1308
1309 /* Default true. */
1310 disdata->trace_case
1311 = (info->disassembler_options == NULL
1312 || (strcmp (info->disassembler_options, "nocase") != 0));
1313
1314 disdata->distype = distype;
1315 return true;
1316 }
1317
1318 static const struct cris_spec_reg *
1319 spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
1320 {
1321 int i;
1322
1323 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1324 {
1325 if (cris_spec_regs[i].number == sreg)
1326 {
1327 if (distype == cris_dis_v32)
1328 switch (cris_spec_regs[i].applicable_version)
1329 {
1330 case cris_ver_warning:
1331 case cris_ver_version_all:
1332 case cris_ver_v3p:
1333 case cris_ver_v8p:
1334 case cris_ver_v10p:
1335 case cris_ver_v32p:
1336 /* No ambiguous sizes or register names with CRISv32. */
1337 if (cris_spec_regs[i].warning == NULL)
1338 return &cris_spec_regs[i];
1339 default:
1340 ;
1341 }
1342 else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
1343 return &cris_spec_regs[i];
1344 }
1345 }
1346
1347 return NULL;
1348 }
1349
1350 /* Return the number of bits in the argument. */
1351
1352 static int
1353 number_of_bits (unsigned int val)
1354 {
1355 int bits;
1356
1357 for (bits = 0; val != 0; val &= val - 1)
1358 bits++;
1359
1360 return bits;
1361 }
1362
1363 /* Get an entry in the opcode-table. */
1364
1365 static const struct cris_opcode *
1366 get_opcode_entry (unsigned int insn,
1367 unsigned int prefix_insn,
1368 struct cris_disasm_data *disdata)
1369 {
1370 /* For non-prefixed insns, we keep a table of pointers, indexed by the
1371 insn code. Each entry is initialized when found to be NULL. */
1372 static const struct cris_opcode **opc_table = NULL;
1373
1374 const struct cris_opcode *max_matchedp = NULL;
1375 const struct cris_opcode **prefix_opc_table = NULL;
1376
1377 /* We hold a table for each prefix that need to be handled differently. */
1378 static const struct cris_opcode **dip_prefixes = NULL;
1379 static const struct cris_opcode **bdapq_m1_prefixes = NULL;
1380 static const struct cris_opcode **bdapq_m2_prefixes = NULL;
1381 static const struct cris_opcode **bdapq_m4_prefixes = NULL;
1382 static const struct cris_opcode **rest_prefixes = NULL;
1383
1384 /* Allocate and clear the opcode-table. */
1385 if (opc_table == NULL)
1386 {
1387 opc_table = g_new0(const struct cris_opcode *, 65536);
1388 dip_prefixes = g_new0(const struct cris_opcode *, 65536);
1389 bdapq_m1_prefixes = g_new0(const struct cris_opcode *, 65536);
1390 bdapq_m2_prefixes = g_new0(const struct cris_opcode *, 65536);
1391 bdapq_m4_prefixes = g_new0(const struct cris_opcode *, 65536);
1392 rest_prefixes = g_new0(const struct cris_opcode *, 65536);
1393 }
1394
1395 /* Get the right table if this is a prefix.
1396 This code is connected to cris_constraints in that it knows what
1397 prefixes play a role in recognition of patterns; the necessary
1398 state is reflected by which table is used. If constraints
1399 involving match or non-match of prefix insns are changed, then this
1400 probably needs changing too. */
1401 if (prefix_insn != NO_CRIS_PREFIX)
1402 {
1403 const struct cris_opcode *popcodep
1404 = (opc_table[prefix_insn] != NULL
1405 ? opc_table[prefix_insn]
1406 : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
1407
1408 if (popcodep == NULL)
1409 return NULL;
1410
1411 if (popcodep->match == BDAP_QUICK_OPCODE)
1412 {
1413 /* Since some offsets are recognized with "push" macros, we
1414 have to have different tables for them. */
1415 int offset = (prefix_insn & 255);
1416
1417 if (offset > 127)
1418 offset -= 256;
1419
1420 switch (offset)
1421 {
1422 case -4:
1423 prefix_opc_table = bdapq_m4_prefixes;
1424 break;
1425
1426 case -2:
1427 prefix_opc_table = bdapq_m2_prefixes;
1428 break;
1429
1430 case -1:
1431 prefix_opc_table = bdapq_m1_prefixes;
1432 break;
1433
1434 default:
1435 prefix_opc_table = rest_prefixes;
1436 break;
1437 }
1438 }
1439 else if (popcodep->match == DIP_OPCODE)
1440 /* We don't allow postincrement when the prefix is DIP, so use a
1441 different table for DIP. */
1442 prefix_opc_table = dip_prefixes;
1443 else
1444 prefix_opc_table = rest_prefixes;
1445 }
1446
1447 if (prefix_insn != NO_CRIS_PREFIX
1448 && prefix_opc_table[insn] != NULL)
1449 max_matchedp = prefix_opc_table[insn];
1450 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
1451 max_matchedp = opc_table[insn];
1452 else
1453 {
1454 const struct cris_opcode *opcodep;
1455 int max_level_of_match = -1;
1456
1457 for (opcodep = cris_opcodes;
1458 opcodep->name != NULL;
1459 opcodep++)
1460 {
1461 int level_of_match;
1462
1463 if (disdata->distype == cris_dis_v32)
1464 {
1465 switch (opcodep->applicable_version)
1466 {
1467 case cris_ver_version_all:
1468 break;
1469
1470 case cris_ver_v0_3:
1471 case cris_ver_v0_10:
1472 case cris_ver_v3_10:
1473 case cris_ver_sim_v0_10:
1474 case cris_ver_v8_10:
1475 case cris_ver_v10:
1476 case cris_ver_warning:
1477 continue;
1478
1479 case cris_ver_v3p:
1480 case cris_ver_v8p:
1481 case cris_ver_v10p:
1482 case cris_ver_v32p:
1483 break;
1484
1485 case cris_ver_v8:
1486 abort ();
1487 default:
1488 abort ();
1489 }
1490 }
1491 else
1492 {
1493 switch (opcodep->applicable_version)
1494 {
1495 case cris_ver_version_all:
1496 case cris_ver_v0_3:
1497 case cris_ver_v3p:
1498 case cris_ver_v0_10:
1499 case cris_ver_v8p:
1500 case cris_ver_v8_10:
1501 case cris_ver_v10:
1502 case cris_ver_sim_v0_10:
1503 case cris_ver_v10p:
1504 case cris_ver_warning:
1505 break;
1506
1507 case cris_ver_v32p:
1508 continue;
1509
1510 case cris_ver_v8:
1511 abort ();
1512 default:
1513 abort ();
1514 }
1515 }
1516
1517 /* We give a double lead for bits matching the template in
1518 cris_opcodes. Not even, because then "move p8,r10" would
1519 be given 2 bits lead over "clear.d r10". When there's a
1520 tie, the first entry in the table wins. This is
1521 deliberate, to avoid a more complicated recognition
1522 formula. */
1523 if ((opcodep->match & insn) == opcodep->match
1524 && (opcodep->lose & insn) == 0
1525 && ((level_of_match
1526 = cris_constraint (opcodep->args,
1527 insn,
1528 prefix_insn,
1529 disdata))
1530 >= 0)
1531 && ((level_of_match
1532 += 2 * number_of_bits (opcodep->match
1533 | opcodep->lose))
1534 > max_level_of_match))
1535 {
1536 max_matchedp = opcodep;
1537 max_level_of_match = level_of_match;
1538
1539 /* If there was a full match, never mind looking
1540 further. */
1541 if (level_of_match >= 2 * 16)
1542 break;
1543 }
1544 }
1545 /* Fill in the new entry.
1546
1547 If there are changes to the opcode-table involving prefixes, and
1548 disassembly then does not work correctly, try removing the
1549 else-clause below that fills in the prefix-table. If that
1550 helps, you need to change the prefix_opc_table setting above, or
1551 something related. */
1552 if (prefix_insn == NO_CRIS_PREFIX)
1553 opc_table[insn] = max_matchedp;
1554 else
1555 prefix_opc_table[insn] = max_matchedp;
1556 }
1557
1558 return max_matchedp;
1559 }
1560
1561 /* Return -1 if the constraints of a bitwise-matched instruction say
1562 that there is no match. Otherwise return a nonnegative number
1563 indicating the confidence in the match (higher is better). */
1564
1565 static int
1566 cris_constraint (const char *cs,
1567 unsigned int insn,
1568 unsigned int prefix_insn,
1569 struct cris_disasm_data *disdata)
1570 {
1571 int retval = 0;
1572 int tmp;
1573 int prefix_ok = 0;
1574 const char *s;
1575
1576 for (s = cs; *s; s++)
1577 switch (*s)
1578 {
1579 case '!':
1580 /* Do not recognize "pop" if there's a prefix and then only for
1581 v0..v10. */
1582 if (prefix_insn != NO_CRIS_PREFIX
1583 || disdata->distype != cris_dis_v0_v10)
1584 return -1;
1585 break;
1586
1587 case 'U':
1588 /* Not recognized at disassembly. */
1589 return -1;
1590
1591 case 'M':
1592 /* Size modifier for "clear", i.e. special register 0, 4 or 8.
1593 Check that it is one of them. Only special register 12 could
1594 be mismatched, but checking for matches is more logical than
1595 checking for mismatches when there are only a few cases. */
1596 tmp = ((insn >> 12) & 0xf);
1597 if (tmp != 0 && tmp != 4 && tmp != 8)
1598 return -1;
1599 break;
1600
1601 case 'm':
1602 if ((insn & 0x30) == 0x30)
1603 return -1;
1604 break;
1605
1606 case 'S':
1607 /* A prefix operand without side-effect. */
1608 if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
1609 {
1610 prefix_ok = 1;
1611 break;
1612 }
1613 else
1614 return -1;
1615
1616 case 's':
1617 case 'y':
1618 case 'Y':
1619 /* If this is a prefixed insn with postincrement (side-effect),
1620 the prefix must not be DIP. */
1621 if (prefix_insn != NO_CRIS_PREFIX)
1622 {
1623 if (insn & 0x400)
1624 {
1625 const struct cris_opcode *prefix_opcodep
1626 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1627
1628 if (prefix_opcodep->match == DIP_OPCODE)
1629 return -1;
1630 }
1631
1632 prefix_ok = 1;
1633 }
1634 break;
1635
1636 case 'B':
1637 /* If we don't fall through, then the prefix is ok. */
1638 prefix_ok = 1;
1639
1640 /* A "push" prefix. Check for valid "push" size.
1641 In case of special register, it may be != 4. */
1642 if (prefix_insn != NO_CRIS_PREFIX)
1643 {
1644 /* Match the prefix insn to BDAPQ. */
1645 const struct cris_opcode *prefix_opcodep
1646 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1647
1648 if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
1649 {
1650 int pushsize = (prefix_insn & 255);
1651
1652 if (pushsize > 127)
1653 pushsize -= 256;
1654
1655 if (s[1] == 'P')
1656 {
1657 unsigned int spec_reg = (insn >> 12) & 15;
1658 const struct cris_spec_reg *sregp
1659 = spec_reg_info (spec_reg, disdata->distype);
1660
1661 /* For a special-register, the "prefix size" must
1662 match the size of the register. */
1663 if (sregp && sregp->reg_size == (unsigned int) -pushsize)
1664 break;
1665 }
1666 else if (s[1] == 'R')
1667 {
1668 if ((insn & 0x30) == 0x20 && pushsize == -4)
1669 break;
1670 }
1671 /* FIXME: Should abort here; next constraint letter
1672 *must* be 'P' or 'R'. */
1673 }
1674 }
1675 return -1;
1676
1677 case 'D':
1678 retval = (((insn >> 12) & 15) == (insn & 15));
1679 if (!retval)
1680 return -1;
1681 else
1682 retval += 4;
1683 break;
1684
1685 case 'P':
1686 {
1687 const struct cris_spec_reg *sregp
1688 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
1689
1690 /* Since we match four bits, we will give a value of 4-1 = 3
1691 in a match. If there is a corresponding exact match of a
1692 special register in another pattern, it will get a value of
1693 4, which will be higher. This should be correct in that an
1694 exact pattern would match better than a general pattern.
1695
1696 Note that there is a reason for not returning zero; the
1697 pattern for "clear" is partly matched in the bit-pattern
1698 (the two lower bits must be zero), while the bit-pattern
1699 for a move from a special register is matched in the
1700 register constraint. */
1701
1702 if (sregp != NULL)
1703 {
1704 retval += 3;
1705 break;
1706 }
1707 else
1708 return -1;
1709 }
1710 }
1711
1712 if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
1713 return -1;
1714
1715 return retval;
1716 }
1717
1718 /* Format number as hex with a leading "0x" into outbuffer. */
1719
1720 static char *
1721 format_hex (unsigned long number,
1722 char *outbuffer,
1723 struct cris_disasm_data *disdata)
1724 {
1725 /* Truncate negative numbers on >32-bit hosts. */
1726 number &= 0xffffffff;
1727
1728 sprintf (outbuffer, "0x%lx", number);
1729
1730 /* Save this value for the "case" support. */
1731 if (TRACE_CASE)
1732 last_immediate = number;
1733
1734 return outbuffer + strlen (outbuffer);
1735 }
1736
1737 /* Format number as decimal into outbuffer. Parameter signedp says
1738 whether the number should be formatted as signed (!= 0) or
1739 unsigned (== 0). */
1740
1741 static char *
1742 format_dec (long number, char *outbuffer, int signedp)
1743 {
1744 last_immediate = number;
1745 sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
1746
1747 return outbuffer + strlen (outbuffer);
1748 }
1749
1750 /* Format the name of the general register regno into outbuffer. */
1751
1752 static char *
1753 format_reg (struct cris_disasm_data *disdata,
1754 int regno,
1755 char *outbuffer_start,
1756 bfd_boolean with_reg_prefix)
1757 {
1758 char *outbuffer = outbuffer_start;
1759
1760 if (with_reg_prefix)
1761 *outbuffer++ = REGISTER_PREFIX_CHAR;
1762
1763 switch (regno)
1764 {
1765 case 15:
1766 /* For v32, there is no context in which we output PC. */
1767 if (disdata->distype == cris_dis_v32)
1768 strcpy (outbuffer, "acr");
1769 else
1770 strcpy (outbuffer, "pc");
1771 break;
1772
1773 case 14:
1774 strcpy (outbuffer, "sp");
1775 break;
1776
1777 default:
1778 sprintf (outbuffer, "r%d", regno);
1779 break;
1780 }
1781
1782 return outbuffer_start + strlen (outbuffer_start);
1783 }
1784
1785 /* Format the name of a support register into outbuffer. */
1786
1787 static char *
1788 format_sup_reg (unsigned int regno,
1789 char *outbuffer_start,
1790 bfd_boolean with_reg_prefix)
1791 {
1792 char *outbuffer = outbuffer_start;
1793 int i;
1794
1795 if (with_reg_prefix)
1796 *outbuffer++ = REGISTER_PREFIX_CHAR;
1797
1798 for (i = 0; cris_support_regs[i].name != NULL; i++)
1799 if (cris_support_regs[i].number == regno)
1800 {
1801 sprintf (outbuffer, "%s", cris_support_regs[i].name);
1802 return outbuffer_start + strlen (outbuffer_start);
1803 }
1804
1805 /* There's supposed to be register names covering all numbers, though
1806 some may be generic names. */
1807 sprintf (outbuffer, "format_sup_reg-BUG");
1808 return outbuffer_start + strlen (outbuffer_start);
1809 }
1810
1811 /* Return the length of an instruction. */
1812
1813 static unsigned
1814 bytes_to_skip (unsigned int insn,
1815 const struct cris_opcode *matchedp,
1816 enum cris_disass_family distype,
1817 const struct cris_opcode *prefix_matchedp)
1818 {
1819 /* Each insn is a word plus "immediate" operands. */
1820 unsigned to_skip = 2;
1821 const char *template = matchedp->args;
1822 const char *s;
1823
1824 for (s = template; *s; s++)
1825 if ((*s == 's' || *s == 'N' || *s == 'Y')
1826 && (insn & 0x400) && (insn & 15) == 15
1827 && prefix_matchedp == NULL)
1828 {
1829 /* Immediate via [pc+], so we have to check the size of the
1830 operand. */
1831 int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
1832
1833 if (matchedp->imm_oprnd_size == SIZE_FIX_32)
1834 to_skip += 4;
1835 else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
1836 {
1837 const struct cris_spec_reg *sregp
1838 = spec_reg_info ((insn >> 12) & 15, distype);
1839
1840 /* FIXME: Improve error handling; should have been caught
1841 earlier. */
1842 if (sregp == NULL)
1843 return 2;
1844
1845 /* PC is incremented by two, not one, for a byte. Except on
1846 CRISv32, where constants are always DWORD-size for
1847 special registers. */
1848 to_skip +=
1849 distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
1850 }
1851 else
1852 to_skip += (mode_size + 1) & ~1;
1853 }
1854 else if (*s == 'n')
1855 to_skip += 4;
1856 else if (*s == 'b')
1857 to_skip += 2;
1858
1859 return to_skip;
1860 }
1861
1862 /* Print condition code flags. */
1863
1864 static char *
1865 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
1866 {
1867 /* Use the v8 (Etrax 100) flag definitions for disassembly.
1868 The differences with v0 (Etrax 1..4) vs. Svinto are:
1869 v0 'd' <=> v8 'm'
1870 v0 'e' <=> v8 'b'.
1871 FIXME: Emit v0..v3 flag names somehow. */
1872 static const char v8_fnames[] = "cvznxibm";
1873 static const char v32_fnames[] = "cvznxiup";
1874 const char *fnames
1875 = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
1876
1877 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
1878 int i;
1879
1880 for (i = 0; i < 8; i++)
1881 if (flagbits & (1 << i))
1882 *cp++ = fnames[i];
1883
1884 return cp;
1885 }
1886
1887 /* Print out an insn with its operands, and update the info->insn_type
1888 fields. The prefix_opcodep and the rest hold a prefix insn that is
1889 supposed to be output as an address mode. */
1890
1891 static void
1892 print_with_operands (const struct cris_opcode *opcodep,
1893 unsigned int insn,
1894 unsigned char *buffer,
1895 bfd_vma addr,
1896 disassemble_info *info,
1897 /* If a prefix insn was before this insn (and is supposed
1898 to be output as an address), here is a description of
1899 it. */
1900 const struct cris_opcode *prefix_opcodep,
1901 unsigned int prefix_insn,
1902 unsigned char *prefix_buffer,
1903 bfd_boolean with_reg_prefix)
1904 {
1905 /* Get a buffer of somewhat reasonable size where we store
1906 intermediate parts of the insn. */
1907 char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
1908 char *tp = temp;
1909 static const char mode_char[] = "bwd?";
1910 const char *s;
1911 const char *cs;
1912 struct cris_disasm_data *disdata
1913 = (struct cris_disasm_data *) info->private_data;
1914
1915 /* Print out the name first thing we do. */
1916 (*info->fprintf_func) (info->stream, "%s", opcodep->name);
1917
1918 cs = opcodep->args;
1919 s = cs;
1920
1921 /* Ignore any prefix indicator. */
1922 if (*s == 'p')
1923 s++;
1924
1925 if (*s == 'm' || *s == 'M' || *s == 'z')
1926 {
1927 *tp++ = '.';
1928
1929 /* Get the size-letter. */
1930 *tp++ = *s == 'M'
1931 ? (insn & 0x8000 ? 'd'
1932 : insn & 0x4000 ? 'w' : 'b')
1933 : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
1934
1935 /* Ignore the size and the space character that follows. */
1936 s += 2;
1937 }
1938
1939 /* Add a space if this isn't a long-branch, because for those will add
1940 the condition part of the name later. */
1941 if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
1942 *tp++ = ' ';
1943
1944 /* Fill in the insn-type if deducible from the name (and there's no
1945 better way). */
1946 if (opcodep->name[0] == 'j')
1947 {
1948 if (CONST_STRNEQ (opcodep->name, "jsr"))
1949 /* It's "jsr" or "jsrc". */
1950 info->insn_type = dis_jsr;
1951 else
1952 /* Any other jump-type insn is considered a branch. */
1953 info->insn_type = dis_branch;
1954 }
1955
1956 /* We might know some more fields right now. */
1957 info->branch_delay_insns = opcodep->delayed;
1958
1959 /* Handle operands. */
1960 for (; *s; s++)
1961 {
1962 switch (*s)
1963 {
1964 case 'T':
1965 tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
1966 break;
1967
1968 case 'A':
1969 if (with_reg_prefix)
1970 *tp++ = REGISTER_PREFIX_CHAR;
1971 *tp++ = 'a';
1972 *tp++ = 'c';
1973 *tp++ = 'r';
1974 break;
1975
1976 case '[':
1977 case ']':
1978 case ',':
1979 *tp++ = *s;
1980 break;
1981
1982 case '!':
1983 /* Ignore at this point; used at earlier stages to avoid
1984 recognition if there's a prefix at something that in other
1985 ways looks like a "pop". */
1986 break;
1987
1988 case 'd':
1989 /* Ignore. This is an optional ".d " on the large one of
1990 relaxable insns. */
1991 break;
1992
1993 case 'B':
1994 /* This was the prefix that made this a "push". We've already
1995 handled it by recognizing it, so signal that the prefix is
1996 handled by setting it to NULL. */
1997 prefix_opcodep = NULL;
1998 break;
1999
2000 case 'D':
2001 case 'r':
2002 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2003 break;
2004
2005 case 'R':
2006 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2007 break;
2008
2009 case 'n':
2010 {
2011 /* Like N but pc-relative to the start of the insn. */
2012 uint32_t number
2013 = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2014 + buffer[5] * 0x1000000 + addr);
2015
2016 /* Finish off and output previous formatted bytes. */
2017 *tp = 0;
2018 if (temp[0])
2019 (*info->fprintf_func) (info->stream, "%s", temp);
2020 tp = temp;
2021
2022 (*info->print_address_func) ((bfd_vma) number, info);
2023 }
2024 break;
2025
2026 case 'u':
2027 {
2028 /* Like n but the offset is bits <3:0> in the instruction. */
2029 unsigned long number = (buffer[0] & 0xf) * 2 + addr;
2030
2031 /* Finish off and output previous formatted bytes. */
2032 *tp = 0;
2033 if (temp[0])
2034 (*info->fprintf_func) (info->stream, "%s", temp);
2035 tp = temp;
2036
2037 (*info->print_address_func) ((bfd_vma) number, info);
2038 }
2039 break;
2040
2041 case 'N':
2042 case 'y':
2043 case 'Y':
2044 case 'S':
2045 case 's':
2046 /* Any "normal" memory operand. */
2047 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
2048 {
2049 /* We're looking at [pc+], i.e. we need to output an immediate
2050 number, where the size can depend on different things. */
2051 int32_t number;
2052 int signedp
2053 = ((*cs == 'z' && (insn & 0x20))
2054 || opcodep->match == BDAP_QUICK_OPCODE);
2055 int nbytes;
2056
2057 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2058 nbytes = 4;
2059 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2060 {
2061 const struct cris_spec_reg *sregp
2062 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2063
2064 /* A NULL return should have been as a non-match earlier,
2065 so catch it as an internal error in the error-case
2066 below. */
2067 if (sregp == NULL)
2068 /* Whatever non-valid size. */
2069 nbytes = 42;
2070 else
2071 /* PC is always incremented by a multiple of two.
2072 For CRISv32, immediates are always 4 bytes for
2073 special registers. */
2074 nbytes = disdata->distype == cris_dis_v32
2075 ? 4 : (sregp->reg_size + 1) & ~1;
2076 }
2077 else
2078 {
2079 int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
2080
2081 if (mode_size == 1)
2082 nbytes = 2;
2083 else
2084 nbytes = mode_size;
2085 }
2086
2087 switch (nbytes)
2088 {
2089 case 1:
2090 number = buffer[2];
2091 if (signedp && number > 127)
2092 number -= 256;
2093 break;
2094
2095 case 2:
2096 number = buffer[2] + buffer[3] * 256;
2097 if (signedp && number > 32767)
2098 number -= 65536;
2099 break;
2100
2101 case 4:
2102 number
2103 = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2104 + buffer[5] * 0x1000000;
2105 break;
2106
2107 default:
2108 strcpy (tp, "bug");
2109 tp += 3;
2110 number = 42;
2111 }
2112
2113 if ((*cs == 'z' && (insn & 0x20))
2114 || (opcodep->match == BDAP_QUICK_OPCODE
2115 && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
2116 tp = format_dec (number, tp, signedp);
2117 else
2118 {
2119 unsigned int highbyte = (number >> 24) & 0xff;
2120
2121 /* Either output this as an address or as a number. If it's
2122 a dword with the same high-byte as the address of the
2123 insn, assume it's an address, and also if it's a non-zero
2124 non-0xff high-byte. If this is a jsr or a jump, then
2125 it's definitely an address. */
2126 if (nbytes == 4
2127 && (highbyte == ((addr >> 24) & 0xff)
2128 || (highbyte != 0 && highbyte != 0xff)
2129 || info->insn_type == dis_branch
2130 || info->insn_type == dis_jsr))
2131 {
2132 /* Finish off and output previous formatted bytes. */
2133 *tp = 0;
2134 tp = temp;
2135 if (temp[0])
2136 (*info->fprintf_func) (info->stream, "%s", temp);
2137
2138 (*info->print_address_func) ((bfd_vma) number, info);
2139
2140 info->target = number;
2141 }
2142 else
2143 tp = format_hex (number, tp, disdata);
2144 }
2145 }
2146 else
2147 {
2148 /* Not an immediate number. Then this is a (possibly
2149 prefixed) memory operand. */
2150 if (info->insn_type != dis_nonbranch)
2151 {
2152 int mode_size
2153 = 1 << ((insn >> 4)
2154 & (opcodep->args[0] == 'z' ? 1 : 3));
2155 int size;
2156 info->insn_type = dis_dref;
2157 info->flags |= CRIS_DIS_FLAG_MEMREF;
2158
2159 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2160 size = 4;
2161 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2162 {
2163 const struct cris_spec_reg *sregp
2164 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2165
2166 /* FIXME: Improve error handling; should have been caught
2167 earlier. */
2168 if (sregp == NULL)
2169 size = 4;
2170 else
2171 size = sregp->reg_size;
2172 }
2173 else
2174 size = mode_size;
2175
2176 info->data_size = size;
2177 }
2178
2179 *tp++ = '[';
2180
2181 if (prefix_opcodep
2182 /* We don't match dip with a postincremented field
2183 as a side-effect address mode. */
2184 && ((insn & 0x400) == 0
2185 || prefix_opcodep->match != DIP_OPCODE))
2186 {
2187 if (insn & 0x400)
2188 {
2189 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2190 *tp++ = '=';
2191 }
2192
2193
2194 /* We mainly ignore the prefix format string when the
2195 address-mode syntax is output. */
2196 switch (prefix_opcodep->match)
2197 {
2198 case DIP_OPCODE:
2199 /* It's [r], [r+] or [pc+]. */
2200 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2201 {
2202 /* It's [pc+]. This cannot possibly be anything
2203 but an address. */
2204 uint32_t number
2205 = prefix_buffer[2] + prefix_buffer[3] * 256
2206 + prefix_buffer[4] * 65536
2207 + prefix_buffer[5] * 0x1000000;
2208
2209 info->target = (bfd_vma) number;
2210
2211 /* Finish off and output previous formatted
2212 data. */
2213 *tp = 0;
2214 tp = temp;
2215 if (temp[0])
2216 (*info->fprintf_func) (info->stream, "%s", temp);
2217
2218 (*info->print_address_func) ((bfd_vma) number, info);
2219 }
2220 else
2221 {
2222 /* For a memref in an address, we use target2.
2223 In this case, target is zero. */
2224 info->flags
2225 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2226 | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
2227
2228 info->target2 = prefix_insn & 15;
2229
2230 *tp++ = '[';
2231 tp = format_reg (disdata, prefix_insn & 15, tp,
2232 with_reg_prefix);
2233 if (prefix_insn & 0x400)
2234 *tp++ = '+';
2235 *tp++ = ']';
2236 }
2237 break;
2238
2239 case BDAP_QUICK_OPCODE:
2240 {
2241 int number;
2242
2243 number = prefix_buffer[0];
2244 if (number > 127)
2245 number -= 256;
2246
2247 /* Output "reg+num" or, if num < 0, "reg-num". */
2248 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2249 with_reg_prefix);
2250 if (number >= 0)
2251 *tp++ = '+';
2252 tp = format_dec (number, tp, 1);
2253
2254 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2255 info->target = (prefix_insn >> 12) & 15;
2256 info->target2 = (bfd_vma) number;
2257 break;
2258 }
2259
2260 case BIAP_OPCODE:
2261 /* Output "r+R.m". */
2262 tp = format_reg (disdata, prefix_insn & 15, tp,
2263 with_reg_prefix);
2264 *tp++ = '+';
2265 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2266 with_reg_prefix);
2267 *tp++ = '.';
2268 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2269
2270 info->flags
2271 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2272 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2273
2274 | ((prefix_insn & 0x8000)
2275 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
2276 : ((prefix_insn & 0x8000)
2277 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
2278
2279 /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
2280 if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
2281 /* Then start interpreting data as offsets. */
2282 case_offset_counter = no_of_case_offsets;
2283 break;
2284
2285 case BDAP_INDIR_OPCODE:
2286 /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
2287 "r-s". */
2288 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2289 with_reg_prefix);
2290
2291 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2292 {
2293 int32_t number;
2294 unsigned int nbytes;
2295
2296 /* It's a value. Get its size. */
2297 int mode_size = 1 << ((prefix_insn >> 4) & 3);
2298
2299 if (mode_size == 1)
2300 nbytes = 2;
2301 else
2302 nbytes = mode_size;
2303
2304 switch (nbytes)
2305 {
2306 case 1:
2307 number = prefix_buffer[2];
2308 if (number > 127)
2309 number -= 256;
2310 break;
2311
2312 case 2:
2313 number = prefix_buffer[2] + prefix_buffer[3] * 256;
2314 if (number > 32767)
2315 number -= 65536;
2316 break;
2317
2318 case 4:
2319 number
2320 = prefix_buffer[2] + prefix_buffer[3] * 256
2321 + prefix_buffer[4] * 65536
2322 + prefix_buffer[5] * 0x1000000;
2323 break;
2324
2325 default:
2326 strcpy (tp, "bug");
2327 tp += 3;
2328 number = 42;
2329 }
2330
2331 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2332 info->target2 = (bfd_vma) number;
2333
2334 /* If the size is dword, then assume it's an
2335 address. */
2336 if (nbytes == 4)
2337 {
2338 /* Finish off and output previous formatted
2339 bytes. */
2340 *tp++ = '+';
2341 *tp = 0;
2342 tp = temp;
2343 (*info->fprintf_func) (info->stream, "%s", temp);
2344
2345 (*info->print_address_func) ((bfd_vma) number, info);
2346 }
2347 else
2348 {
2349 if (number >= 0)
2350 *tp++ = '+';
2351 tp = format_dec (number, tp, 1);
2352 }
2353 }
2354 else
2355 {
2356 /* Output "r+[R].m" or "r+[R+].m". */
2357 *tp++ = '+';
2358 *tp++ = '[';
2359 tp = format_reg (disdata, prefix_insn & 15, tp,
2360 with_reg_prefix);
2361 if (prefix_insn & 0x400)
2362 *tp++ = '+';
2363 *tp++ = ']';
2364 *tp++ = '.';
2365 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2366
2367 info->flags
2368 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2369 | CRIS_DIS_FLAG_MEM_TARGET2_MEM
2370 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2371
2372 | (((prefix_insn >> 4) == 2)
2373 ? 0
2374 : (((prefix_insn >> 4) & 3) == 1
2375 ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
2376 : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
2377 }
2378 break;
2379
2380 default:
2381 (*info->fprintf_func) (info->stream, "?prefix-bug");
2382 }
2383
2384 /* To mark that the prefix is used, reset it. */
2385 prefix_opcodep = NULL;
2386 }
2387 else
2388 {
2389 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2390
2391 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2392 info->target = insn & 15;
2393
2394 if (insn & 0x400)
2395 *tp++ = '+';
2396 }
2397 *tp++ = ']';
2398 }
2399 break;
2400
2401 case 'x':
2402 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2403 *tp++ = '.';
2404 *tp++ = mode_char[(insn >> 4) & 3];
2405 break;
2406
2407 case 'I':
2408 tp = format_dec (insn & 63, tp, 0);
2409 break;
2410
2411 case 'b':
2412 {
2413 int where = buffer[2] + buffer[3] * 256;
2414
2415 if (where > 32767)
2416 where -= 65536;
2417
2418 where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
2419
2420 if (insn == BA_PC_INCR_OPCODE)
2421 info->insn_type = dis_branch;
2422 else
2423 info->insn_type = dis_condbranch;
2424
2425 info->target = (bfd_vma) where;
2426
2427 *tp = 0;
2428 tp = temp;
2429 (*info->fprintf_func) (info->stream, "%s%s ",
2430 temp, cris_cc_strings[insn >> 12]);
2431
2432 (*info->print_address_func) ((bfd_vma) where, info);
2433 }
2434 break;
2435
2436 case 'c':
2437 tp = format_dec (insn & 31, tp, 0);
2438 break;
2439
2440 case 'C':
2441 tp = format_dec (insn & 15, tp, 0);
2442 break;
2443
2444 case 'o':
2445 {
2446 long offset = insn & 0xfe;
2447 bfd_vma target;
2448
2449 if (insn & 1)
2450 offset |= ~0xff;
2451
2452 if (opcodep->match == BA_QUICK_OPCODE)
2453 info->insn_type = dis_branch;
2454 else
2455 info->insn_type = dis_condbranch;
2456
2457 target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
2458 info->target = target;
2459 *tp = 0;
2460 tp = temp;
2461 (*info->fprintf_func) (info->stream, "%s", temp);
2462 (*info->print_address_func) (target, info);
2463 }
2464 break;
2465
2466 case 'Q':
2467 case 'O':
2468 {
2469 long number = buffer[0];
2470
2471 if (number > 127)
2472 number = number - 256;
2473
2474 tp = format_dec (number, tp, 1);
2475 *tp++ = ',';
2476 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2477 }
2478 break;
2479
2480 case 'f':
2481 tp = print_flags (disdata, insn, tp);
2482 break;
2483
2484 case 'i':
2485 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
2486 break;
2487
2488 case 'P':
2489 {
2490 const struct cris_spec_reg *sregp
2491 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2492
2493 if (sregp == NULL || sregp->name == NULL)
2494 /* Should have been caught as a non-match earlier. */
2495 *tp++ = '?';
2496 else
2497 {
2498 if (with_reg_prefix)
2499 *tp++ = REGISTER_PREFIX_CHAR;
2500 strcpy (tp, sregp->name);
2501 tp += strlen (tp);
2502 }
2503 }
2504 break;
2505
2506 default:
2507 strcpy (tp, "???");
2508 tp += 3;
2509 }
2510 }
2511
2512 *tp = 0;
2513
2514 if (prefix_opcodep)
2515 (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
2516 prefix_opcodep->name, prefix_opcodep->args);
2517
2518 (*info->fprintf_func) (info->stream, "%s", temp);
2519
2520 /* Get info for matching case-tables, if we don't have any active.
2521 We assume that the last constant seen is used; either in the insn
2522 itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
2523 if (TRACE_CASE && case_offset_counter == 0)
2524 {
2525 if (CONST_STRNEQ (opcodep->name, "sub"))
2526 case_offset = last_immediate;
2527
2528 /* It could also be an "add", if there are negative case-values. */
2529 else if (CONST_STRNEQ (opcodep->name, "add"))
2530 /* The first case is the negated operand to the add. */
2531 case_offset = -last_immediate;
2532
2533 /* A bound insn will tell us the number of cases. */
2534 else if (CONST_STRNEQ (opcodep->name, "bound"))
2535 no_of_case_offsets = last_immediate + 1;
2536
2537 /* A jump or jsr or branch breaks the chain of insns for a
2538 case-table, so assume default first-case again. */
2539 else if (info->insn_type == dis_jsr
2540 || info->insn_type == dis_branch
2541 || info->insn_type == dis_condbranch)
2542 case_offset = 0;
2543 }
2544 }
2545
2546
2547 /* Print the CRIS instruction at address memaddr on stream. Returns
2548 length of the instruction, in bytes. Prefix register names with `$' if
2549 WITH_REG_PREFIX. */
2550
2551 static int
2552 print_insn_cris_generic (bfd_vma memaddr,
2553 disassemble_info *info,
2554 bfd_boolean with_reg_prefix)
2555 {
2556 int nbytes;
2557 unsigned int insn;
2558 const struct cris_opcode *matchedp;
2559 int advance = 0;
2560 struct cris_disasm_data *disdata
2561 = (struct cris_disasm_data *) info->private_data;
2562
2563 /* No instruction will be disassembled as longer than this number of
2564 bytes; stacked prefixes will not be expanded. */
2565 unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
2566 unsigned char *bufp;
2567 int status = 0;
2568 bfd_vma addr;
2569
2570 /* There will be an "out of range" error after the last instruction.
2571 Reading pairs of bytes in decreasing number, we hope that we will get
2572 at least the amount that we will consume.
2573
2574 If we can't get any data, or we do not get enough data, we print
2575 the error message. */
2576
2577 nbytes = info->buffer_length ? info->buffer_length
2578 : MAX_BYTES_PER_CRIS_INSN;
2579 nbytes = MIN(nbytes, MAX_BYTES_PER_CRIS_INSN);
2580 status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);
2581
2582 /* If we did not get all we asked for, then clear the rest.
2583 Hopefully this makes a reproducible result in case of errors. */
2584 if (nbytes != MAX_BYTES_PER_CRIS_INSN)
2585 memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
2586
2587 addr = memaddr;
2588 bufp = buffer;
2589
2590 /* Set some defaults for the insn info. */
2591 info->insn_info_valid = 1;
2592 info->branch_delay_insns = 0;
2593 info->data_size = 0;
2594 info->insn_type = dis_nonbranch;
2595 info->flags = 0;
2596 info->target = 0;
2597 info->target2 = 0;
2598
2599 /* If we got any data, disassemble it. */
2600 if (nbytes != 0)
2601 {
2602 matchedp = NULL;
2603
2604 insn = bufp[0] + bufp[1] * 256;
2605
2606 /* If we're in a case-table, don't disassemble the offsets. */
2607 if (TRACE_CASE && case_offset_counter != 0)
2608 {
2609 info->insn_type = dis_noninsn;
2610 advance += 2;
2611
2612 /* If to print data as offsets, then shortcut here. */
2613 (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
2614 case_offset + no_of_case_offsets
2615 - case_offset_counter,
2616 case_offset_counter == 1 ? "/default" :
2617 "");
2618
2619 (*info->print_address_func) ((bfd_vma)
2620 ((short) (insn)
2621 + (long) (addr
2622 - (no_of_case_offsets
2623 - case_offset_counter)
2624 * 2)), info);
2625 case_offset_counter--;
2626
2627 /* The default case start (without a "sub" or "add") must be
2628 zero. */
2629 if (case_offset_counter == 0)
2630 case_offset = 0;
2631 }
2632 else if (insn == 0)
2633 {
2634 /* We're often called to disassemble zeroes. While this is a
2635 valid "bcc .+2" insn, it is also useless enough and enough
2636 of a nuiscance that we will just output "bcc .+2" for it
2637 and signal it as a noninsn. */
2638 (*info->fprintf_func) (info->stream,
2639 disdata->distype == cris_dis_v32
2640 ? "bcc ." : "bcc .+2");
2641 info->insn_type = dis_noninsn;
2642 advance += 2;
2643 }
2644 else
2645 {
2646 const struct cris_opcode *prefix_opcodep = NULL;
2647 unsigned char *prefix_buffer = bufp;
2648 unsigned int prefix_insn = insn;
2649 int prefix_size = 0;
2650
2651 matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
2652
2653 /* Check if we're supposed to write out prefixes as address
2654 modes and if this was a prefix. */
2655 if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
2656 {
2657 /* If it's a prefix, put it into the prefix vars and get the
2658 main insn. */
2659 prefix_size = bytes_to_skip (prefix_insn, matchedp,
2660 disdata->distype, NULL);
2661 prefix_opcodep = matchedp;
2662
2663 insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
2664 matchedp = get_opcode_entry (insn, prefix_insn, disdata);
2665
2666 if (matchedp != NULL)
2667 {
2668 addr += prefix_size;
2669 bufp += prefix_size;
2670 advance += prefix_size;
2671 }
2672 else
2673 {
2674 /* The "main" insn wasn't valid, at least not when
2675 prefixed. Put back things enough to output the
2676 prefix insn only, as a normal insn. */
2677 matchedp = prefix_opcodep;
2678 insn = prefix_insn;
2679 prefix_opcodep = NULL;
2680 }
2681 }
2682
2683 if (matchedp == NULL)
2684 {
2685 (*info->fprintf_func) (info->stream, "??0x%x", insn);
2686 advance += 2;
2687
2688 info->insn_type = dis_noninsn;
2689 }
2690 else
2691 {
2692 advance
2693 += bytes_to_skip (insn, matchedp, disdata->distype,
2694 prefix_opcodep);
2695
2696 /* The info_type and assorted fields will be set according
2697 to the operands. */
2698 print_with_operands (matchedp, insn, bufp, addr, info,
2699 prefix_opcodep, prefix_insn,
2700 prefix_buffer, with_reg_prefix);
2701 }
2702 }
2703 }
2704 else
2705 info->insn_type = dis_noninsn;
2706
2707 /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
2708 status when reading that much, and the insn decoding indicated a
2709 length exceeding what we read, there is an error. */
2710 if (status != 0 && (nbytes == 0 || advance > nbytes))
2711 {
2712 (*info->memory_error_func) (status, memaddr, info);
2713 return -1;
2714 }
2715
2716 /* Max supported insn size with one folded prefix insn. */
2717 info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
2718
2719 /* I would like to set this to a fixed value larger than the actual
2720 number of bytes to print in order to avoid spaces between bytes,
2721 but objdump.c (2.9.1) does not like that, so we print 16-bit
2722 chunks, which is the next choice. */
2723 info->bytes_per_chunk = 2;
2724
2725 /* Printing bytes in order of increasing addresses makes sense,
2726 especially on a little-endian target.
2727 This is completely the opposite of what you think; setting this to
2728 BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
2729 we want. */
2730 info->display_endian = BFD_ENDIAN_BIG;
2731
2732 return advance;
2733 }
2734
2735 /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
2736 static int
2737 print_insn_cris_with_register_prefix (bfd_vma vma,
2738 disassemble_info *info)
2739 {
2740 if (info->private_data == NULL
2741 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2742 return -1;
2743 return print_insn_cris_generic (vma, info, true);
2744 }
2745 /* Disassemble, prefixing register names with `$'. CRIS v32. */
2746
2747 static int
2748 print_insn_crisv32_with_register_prefix (bfd_vma vma,
2749 disassemble_info *info)
2750 {
2751 if (info->private_data == NULL
2752 && !cris_parse_disassembler_options (info, cris_dis_v32))
2753 return -1;
2754 return print_insn_cris_generic (vma, info, true);
2755 }
2756
2757 #if 0
2758 /* Disassemble, prefixing register names with `$'.
2759 Common v10 and v32 subset. */
2760
2761 static int
2762 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
2763 disassemble_info *info)
2764 {
2765 if (info->private_data == NULL
2766 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2767 return -1;
2768 return print_insn_cris_generic (vma, info, true);
2769 }
2770
2771 /* Disassemble, no prefixes on register names. CRIS v0..v10. */
2772
2773 static int
2774 print_insn_cris_without_register_prefix (bfd_vma vma,
2775 disassemble_info *info)
2776 {
2777 if (info->private_data == NULL
2778 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2779 return -1;
2780 return print_insn_cris_generic (vma, info, false);
2781 }
2782
2783 /* Disassemble, no prefixes on register names. CRIS v32. */
2784
2785 static int
2786 print_insn_crisv32_without_register_prefix (bfd_vma vma,
2787 disassemble_info *info)
2788 {
2789 if (info->private_data == NULL
2790 && !cris_parse_disassembler_options (info, cris_dis_v32))
2791 return -1;
2792 return print_insn_cris_generic (vma, info, false);
2793 }
2794
2795 /* Disassemble, no prefixes on register names.
2796 Common v10 and v32 subset. */
2797
2798 static int
2799 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
2800 disassemble_info *info)
2801 {
2802 if (info->private_data == NULL
2803 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2804 return -1;
2805 return print_insn_cris_generic (vma, info, false);
2806 }
2807 #endif
2808
2809 int
2810 print_insn_crisv10 (bfd_vma vma,
2811 disassemble_info *info)
2812 {
2813 return print_insn_cris_with_register_prefix(vma, info);
2814 }
2815
2816 int
2817 print_insn_crisv32 (bfd_vma vma,
2818 disassemble_info *info)
2819 {
2820 return print_insn_crisv32_with_register_prefix(vma, info);
2821 }
2822
2823 /* Return a disassembler-function that prints registers with a `$' prefix,
2824 or one that prints registers without a prefix.
2825 FIXME: We should improve the solution to avoid the multitude of
2826 functions seen above. */
2827 #if 0
2828 disassembler_ftype
2829 cris_get_disassembler (bfd *abfd)
2830 {
2831 /* If there's no bfd in sight, we return what is valid as input in all
2832 contexts if fed back to the assembler: disassembly *with* register
2833 prefix. Unfortunately this will be totally wrong for v32. */
2834 if (abfd == NULL)
2835 return print_insn_cris_with_register_prefix;
2836
2837 if (bfd_get_symbol_leading_char (abfd) == 0)
2838 {
2839 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2840 return print_insn_crisv32_with_register_prefix;
2841 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2842 return print_insn_crisv10_v32_with_register_prefix;
2843
2844 /* We default to v10. This may be specifically specified in the
2845 bfd mach, but is also the default setting. */
2846 return print_insn_cris_with_register_prefix;
2847 }
2848
2849 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2850 return print_insn_crisv32_without_register_prefix;
2851 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2852 return print_insn_crisv10_v32_without_register_prefix;
2853 return print_insn_cris_without_register_prefix;
2854 }
2855 #endif
2856 /* Local variables:
2857 eval: (c-set-style "gnu")
2858 indent-tabs-mode: t
2859 End: */
AR7 emulation for QEMU