2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/i386/pc.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/isa/isa.h"
30 #include "hw/sysbus.h"
31 #include "qemu/range.h"
32 #include "hw/xen/xen.h"
33 #include "hw/pci-host/pam.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/i386/ioapic.h"
36 #include "qapi/visitor.h"
39 * I440FX chipset data sheet.
40 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
44 #define I440FX_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
47 typedef struct I440FXState
{
48 PCIHostState parent_obj
;
50 uint64_t pci_hole64_size
;
51 uint32_t short_root_bus
;
54 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
55 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
56 #define XEN_PIIX_NUM_PIRQS 128ULL
57 #define PIIX_PIRQC 0x60
60 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
61 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
63 #define RCR_IOPORT 0xcf9
65 typedef struct PIIX3State
{
69 * bitmap to track pic levels.
70 * The pic level is the logical OR of all the PCI irqs mapped to it
71 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
73 * PIRQ is mapped to PIC pins, we track it by
74 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
75 * pic_irq * PIIX_NUM_PIRQS + pirq
77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
78 #error "unable to encode pic state in 64bit in pic_levels."
84 /* This member isn't used. Just for save/load compatibility */
85 int32_t pci_irq_levels_vmstate
[PIIX_NUM_PIRQS
];
87 /* Reset Control Register contents */
90 /* IO memory region for Reset Control Register (RCR_IOPORT) */
94 #define TYPE_I440FX_PCI_DEVICE "i440FX"
95 #define I440FX_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
98 struct PCII440FXState
{
100 PCIDevice parent_obj
;
103 MemoryRegion
*system_memory
;
104 MemoryRegion
*pci_address_space
;
105 MemoryRegion
*ram_memory
;
106 PAMMemoryRegion pam_regions
[13];
107 MemoryRegion smram_region
;
108 MemoryRegion smram
, low_smram
;
112 #define I440FX_PAM 0x59
113 #define I440FX_PAM_SIZE 7
114 #define I440FX_SMRAM 0x72
116 static void piix3_set_irq(void *opaque
, int pirq
, int level
);
117 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pci_intx
);
118 static void piix3_write_config_xen(PCIDevice
*dev
,
119 uint32_t address
, uint32_t val
, int len
);
121 /* return the global irq number corresponding to a given device irq
122 pin. We could also use the bus number to have a more precise
124 static int pci_slot_get_pirq(PCIDevice
*pci_dev
, int pci_intx
)
127 slot_addend
= (pci_dev
->devfn
>> 3) - 1;
128 return (pci_intx
+ slot_addend
) & 3;
131 static void i440fx_update_memory_mappings(PCII440FXState
*d
)
134 PCIDevice
*pd
= PCI_DEVICE(d
);
136 memory_region_transaction_begin();
137 for (i
= 0; i
< 13; i
++) {
138 pam_update(&d
->pam_regions
[i
], i
,
139 pd
->config
[I440FX_PAM
+ ((i
+ 1) / 2)]);
141 memory_region_set_enabled(&d
->smram_region
,
142 !(pd
->config
[I440FX_SMRAM
] & SMRAM_D_OPEN
));
143 memory_region_set_enabled(&d
->smram
,
144 pd
->config
[I440FX_SMRAM
] & SMRAM_G_SMRAME
);
145 memory_region_transaction_commit();
149 static void i440fx_write_config(PCIDevice
*dev
,
150 uint32_t address
, uint32_t val
, int len
)
152 PCII440FXState
*d
= I440FX_PCI_DEVICE(dev
);
154 /* XXX: implement SMRAM.D_LOCK */
155 pci_default_write_config(dev
, address
, val
, len
);
156 if (ranges_overlap(address
, len
, I440FX_PAM
, I440FX_PAM_SIZE
) ||
157 range_covers_byte(address
, len
, I440FX_SMRAM
)) {
158 i440fx_update_memory_mappings(d
);
162 static int i440fx_load_old(QEMUFile
* f
, void *opaque
, int version_id
)
164 PCII440FXState
*d
= opaque
;
165 PCIDevice
*pd
= PCI_DEVICE(d
);
169 ret
= pci_device_load(pd
, f
);
172 i440fx_update_memory_mappings(d
);
173 qemu_get_8s(f
, &smm_enabled
);
175 if (version_id
== 2) {
176 for (i
= 0; i
< PIIX_NUM_PIRQS
; i
++) {
177 qemu_get_be32(f
); /* dummy load for compatibility */
184 static int i440fx_post_load(void *opaque
, int version_id
)
186 PCII440FXState
*d
= opaque
;
188 i440fx_update_memory_mappings(d
);
192 static const VMStateDescription vmstate_i440fx
= {
195 .minimum_version_id
= 3,
196 .minimum_version_id_old
= 1,
197 .load_state_old
= i440fx_load_old
,
198 .post_load
= i440fx_post_load
,
199 .fields
= (VMStateField
[]) {
200 VMSTATE_PCI_DEVICE(parent_obj
, PCII440FXState
),
201 /* Used to be smm_enabled, which was basically always zero because
202 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
205 VMSTATE_END_OF_LIST()
209 static void i440fx_pcihost_get_pci_hole_start(Object
*obj
, Visitor
*v
,
210 void *opaque
, const char *name
,
213 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
214 uint32_t value
= s
->pci_info
.w32
.begin
;
216 visit_type_uint32(v
, &value
, name
, errp
);
219 static void i440fx_pcihost_get_pci_hole_end(Object
*obj
, Visitor
*v
,
220 void *opaque
, const char *name
,
223 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
224 uint32_t value
= s
->pci_info
.w32
.end
;
226 visit_type_uint32(v
, &value
, name
, errp
);
229 static void i440fx_pcihost_get_pci_hole64_start(Object
*obj
, Visitor
*v
,
230 void *opaque
, const char *name
,
233 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
236 pci_bus_get_w64_range(h
->bus
, &w64
);
238 visit_type_uint64(v
, &w64
.begin
, name
, errp
);
241 static void i440fx_pcihost_get_pci_hole64_end(Object
*obj
, Visitor
*v
,
242 void *opaque
, const char *name
,
245 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
248 pci_bus_get_w64_range(h
->bus
, &w64
);
250 visit_type_uint64(v
, &w64
.end
, name
, errp
);
253 static void i440fx_pcihost_initfn(Object
*obj
)
255 PCIHostState
*s
= PCI_HOST_BRIDGE(obj
);
256 I440FXState
*d
= I440FX_PCI_HOST_BRIDGE(obj
);
258 memory_region_init_io(&s
->conf_mem
, obj
, &pci_host_conf_le_ops
, s
,
260 memory_region_init_io(&s
->data_mem
, obj
, &pci_host_data_le_ops
, s
,
263 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_START
, "int",
264 i440fx_pcihost_get_pci_hole_start
,
265 NULL
, NULL
, NULL
, NULL
);
267 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_END
, "int",
268 i440fx_pcihost_get_pci_hole_end
,
269 NULL
, NULL
, NULL
, NULL
);
271 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_START
, "int",
272 i440fx_pcihost_get_pci_hole64_start
,
273 NULL
, NULL
, NULL
, NULL
);
275 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_END
, "int",
276 i440fx_pcihost_get_pci_hole64_end
,
277 NULL
, NULL
, NULL
, NULL
);
279 d
->pci_info
.w32
.end
= IO_APIC_DEFAULT_ADDRESS
;
282 static void i440fx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
284 PCIHostState
*s
= PCI_HOST_BRIDGE(dev
);
285 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
287 sysbus_add_io(sbd
, 0xcf8, &s
->conf_mem
);
288 sysbus_init_ioports(sbd
, 0xcf8, 4);
290 sysbus_add_io(sbd
, 0xcfc, &s
->data_mem
);
291 sysbus_init_ioports(sbd
, 0xcfc, 4);
294 static void i440fx_realize(PCIDevice
*dev
, Error
**errp
)
296 dev
->config
[I440FX_SMRAM
] = 0x02;
299 PCIBus
*i440fx_init(PCII440FXState
**pi440fx_state
,
301 ISABus
**isa_bus
, qemu_irq
*pic
,
302 MemoryRegion
*address_space_mem
,
303 MemoryRegion
*address_space_io
,
305 ram_addr_t below_4g_mem_size
,
306 ram_addr_t above_4g_mem_size
,
307 MemoryRegion
*pci_address_space
,
308 MemoryRegion
*ram_memory
)
319 dev
= qdev_create(NULL
, TYPE_I440FX_PCI_HOST_BRIDGE
);
320 s
= PCI_HOST_BRIDGE(dev
);
321 b
= pci_bus_new(dev
, NULL
, pci_address_space
,
322 address_space_io
, 0, TYPE_PCI_BUS
);
324 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev
), NULL
);
325 qdev_init_nofail(dev
);
327 d
= pci_create_simple(b
, 0, TYPE_I440FX_PCI_DEVICE
);
328 *pi440fx_state
= I440FX_PCI_DEVICE(d
);
330 f
->system_memory
= address_space_mem
;
331 f
->pci_address_space
= pci_address_space
;
332 f
->ram_memory
= ram_memory
;
334 i440fx
= I440FX_PCI_HOST_BRIDGE(dev
);
335 i440fx
->pci_info
.w32
.begin
= below_4g_mem_size
;
337 /* setup pci memory mapping */
338 pc_pci_as_mapping_init(OBJECT(f
), f
->system_memory
,
339 f
->pci_address_space
);
341 /* if *disabled* show SMRAM to all CPUs */
342 memory_region_init_alias(&f
->smram_region
, OBJECT(d
), "smram-region",
343 f
->pci_address_space
, 0xa0000, 0x20000);
344 memory_region_add_subregion_overlap(f
->system_memory
, 0xa0000,
345 &f
->smram_region
, 1);
346 memory_region_set_enabled(&f
->smram_region
, true);
348 /* smram, as seen by SMM CPUs */
349 memory_region_init(&f
->smram
, OBJECT(d
), "smram", 1ull << 32);
350 memory_region_set_enabled(&f
->smram
, true);
351 memory_region_init_alias(&f
->low_smram
, OBJECT(d
), "smram-low",
352 f
->ram_memory
, 0xa0000, 0x20000);
353 memory_region_set_enabled(&f
->low_smram
, true);
354 memory_region_add_subregion(&f
->smram
, 0xa0000, &f
->low_smram
);
355 object_property_add_const_link(qdev_get_machine(), "smram",
356 OBJECT(&f
->smram
), &error_abort
);
358 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
359 &f
->pam_regions
[0], PAM_BIOS_BASE
, PAM_BIOS_SIZE
);
360 for (i
= 0; i
< 12; ++i
) {
361 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
362 &f
->pam_regions
[i
+1], PAM_EXPAN_BASE
+ i
* PAM_EXPAN_SIZE
,
366 /* Xen supports additional interrupt routes from the PCI devices to
367 * the IOAPIC: the four pins of each PCI device on the bus are also
368 * connected to the IOAPIC directly.
369 * These additional routes can be discovered through ACPI. */
371 piix3
= DO_UPCAST(PIIX3State
, dev
,
372 pci_create_simple_multifunction(b
, -1, true, "PIIX3-xen"));
373 pci_bus_irqs(b
, xen_piix3_set_irq
, xen_pci_slot_get_pirq
,
374 piix3
, XEN_PIIX_NUM_PIRQS
);
376 piix3
= DO_UPCAST(PIIX3State
, dev
,
377 pci_create_simple_multifunction(b
, -1, true, "PIIX3"));
378 pci_bus_irqs(b
, piix3_set_irq
, pci_slot_get_pirq
, piix3
,
380 pci_bus_set_route_irq_fn(b
, piix3_route_intx_pin_to_irq
);
383 *isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(piix3
), "isa.0"));
385 *piix3_devfn
= piix3
->dev
.devfn
;
387 ram_size
= ram_size
/ 8 / 1024 / 1024;
388 if (ram_size
> 255) {
391 d
->config
[0x57] = ram_size
;
393 i440fx_update_memory_mappings(f
);
398 PCIBus
*find_i440fx(void)
400 PCIHostState
*s
= OBJECT_CHECK(PCIHostState
,
401 object_resolve_path("/machine/i440fx", NULL
),
402 TYPE_PCI_HOST_BRIDGE
);
403 return s
? s
->bus
: NULL
;
406 /* PIIX3 PCI to ISA bridge */
407 static void piix3_set_irq_pic(PIIX3State
*piix3
, int pic_irq
)
409 qemu_set_irq(piix3
->pic
[pic_irq
],
410 !!(piix3
->pic_levels
&
411 (((1ULL << PIIX_NUM_PIRQS
) - 1) <<
412 (pic_irq
* PIIX_NUM_PIRQS
))));
415 static void piix3_set_irq_level_internal(PIIX3State
*piix3
, int pirq
, int level
)
420 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
421 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
425 mask
= 1ULL << ((pic_irq
* PIIX_NUM_PIRQS
) + pirq
);
426 piix3
->pic_levels
&= ~mask
;
427 piix3
->pic_levels
|= mask
* !!level
;
430 static void piix3_set_irq_level(PIIX3State
*piix3
, int pirq
, int level
)
434 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
435 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
439 piix3_set_irq_level_internal(piix3
, pirq
, level
);
441 piix3_set_irq_pic(piix3
, pic_irq
);
444 static void piix3_set_irq(void *opaque
, int pirq
, int level
)
446 PIIX3State
*piix3
= opaque
;
447 piix3_set_irq_level(piix3
, pirq
, level
);
450 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pin
)
452 PIIX3State
*piix3
= opaque
;
453 int irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pin
];
456 if (irq
< PIIX_NUM_PIC_IRQS
) {
457 route
.mode
= PCI_INTX_ENABLED
;
460 route
.mode
= PCI_INTX_DISABLED
;
466 /* irq routing is changed. so rebuild bitmap */
467 static void piix3_update_irq_levels(PIIX3State
*piix3
)
471 piix3
->pic_levels
= 0;
472 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
473 piix3_set_irq_level(piix3
, pirq
,
474 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
478 static void piix3_write_config(PCIDevice
*dev
,
479 uint32_t address
, uint32_t val
, int len
)
481 pci_default_write_config(dev
, address
, val
, len
);
482 if (ranges_overlap(address
, len
, PIIX_PIRQC
, 4)) {
483 PIIX3State
*piix3
= DO_UPCAST(PIIX3State
, dev
, dev
);
486 pci_bus_fire_intx_routing_notifier(piix3
->dev
.bus
);
487 piix3_update_irq_levels(piix3
);
488 for (pic_irq
= 0; pic_irq
< PIIX_NUM_PIC_IRQS
; pic_irq
++) {
489 piix3_set_irq_pic(piix3
, pic_irq
);
494 static void piix3_write_config_xen(PCIDevice
*dev
,
495 uint32_t address
, uint32_t val
, int len
)
497 xen_piix_pci_write_config_client(address
, val
, len
);
498 piix3_write_config(dev
, address
, val
, len
);
501 static void piix3_reset(void *opaque
)
503 PIIX3State
*d
= opaque
;
504 uint8_t *pci_conf
= d
->dev
.config
;
506 pci_conf
[0x04] = 0x07; /* master, memory and I/O */
507 pci_conf
[0x05] = 0x00;
508 pci_conf
[0x06] = 0x00;
509 pci_conf
[0x07] = 0x02; /* PCI_status_devsel_medium */
510 pci_conf
[0x4c] = 0x4d;
511 pci_conf
[0x4e] = 0x03;
512 pci_conf
[0x4f] = 0x00;
513 pci_conf
[0x60] = 0x80;
514 pci_conf
[0x61] = 0x80;
515 pci_conf
[0x62] = 0x80;
516 pci_conf
[0x63] = 0x80;
517 pci_conf
[0x69] = 0x02;
518 pci_conf
[0x70] = 0x80;
519 pci_conf
[0x76] = 0x0c;
520 pci_conf
[0x77] = 0x0c;
521 pci_conf
[0x78] = 0x02;
522 pci_conf
[0x79] = 0x00;
523 pci_conf
[0x80] = 0x00;
524 pci_conf
[0x82] = 0x00;
525 pci_conf
[0xa0] = 0x08;
526 pci_conf
[0xa2] = 0x00;
527 pci_conf
[0xa3] = 0x00;
528 pci_conf
[0xa4] = 0x00;
529 pci_conf
[0xa5] = 0x00;
530 pci_conf
[0xa6] = 0x00;
531 pci_conf
[0xa7] = 0x00;
532 pci_conf
[0xa8] = 0x0f;
533 pci_conf
[0xaa] = 0x00;
534 pci_conf
[0xab] = 0x00;
535 pci_conf
[0xac] = 0x00;
536 pci_conf
[0xae] = 0x00;
542 static int piix3_post_load(void *opaque
, int version_id
)
544 PIIX3State
*piix3
= opaque
;
547 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
548 * might bring the system to a different state than the saved one;
549 * for example, the interrupt could be masked but the i8259 would
550 * not know that yet and would trigger an interrupt in the CPU.
552 * Here, we update irq levels without raising the interrupt.
553 * Interrupt state will be deserialized separately through the i8259.
555 piix3
->pic_levels
= 0;
556 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
557 piix3_set_irq_level_internal(piix3
, pirq
,
558 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
563 static void piix3_pre_save(void *opaque
)
566 PIIX3State
*piix3
= opaque
;
568 for (i
= 0; i
< ARRAY_SIZE(piix3
->pci_irq_levels_vmstate
); i
++) {
569 piix3
->pci_irq_levels_vmstate
[i
] =
570 pci_bus_get_irq_level(piix3
->dev
.bus
, i
);
574 static bool piix3_rcr_needed(void *opaque
)
576 PIIX3State
*piix3
= opaque
;
578 return (piix3
->rcr
!= 0);
581 static const VMStateDescription vmstate_piix3_rcr
= {
584 .minimum_version_id
= 1,
585 .needed
= piix3_rcr_needed
,
586 .fields
= (VMStateField
[]) {
587 VMSTATE_UINT8(rcr
, PIIX3State
),
588 VMSTATE_END_OF_LIST()
592 static const VMStateDescription vmstate_piix3
= {
595 .minimum_version_id
= 2,
596 .post_load
= piix3_post_load
,
597 .pre_save
= piix3_pre_save
,
598 .fields
= (VMStateField
[]) {
599 VMSTATE_PCI_DEVICE(dev
, PIIX3State
),
600 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate
, PIIX3State
,
602 VMSTATE_END_OF_LIST()
604 .subsections
= (const VMStateDescription
*[]) {
611 static void rcr_write(void *opaque
, hwaddr addr
, uint64_t val
, unsigned len
)
613 PIIX3State
*d
= opaque
;
616 qemu_system_reset_request();
619 d
->rcr
= val
& 2; /* keep System Reset type only */
622 static uint64_t rcr_read(void *opaque
, hwaddr addr
, unsigned len
)
624 PIIX3State
*d
= opaque
;
629 static const MemoryRegionOps rcr_ops
= {
632 .endianness
= DEVICE_LITTLE_ENDIAN
635 static void piix3_realize(PCIDevice
*dev
, Error
**errp
)
637 PIIX3State
*d
= DO_UPCAST(PIIX3State
, dev
, dev
);
639 isa_bus_new(DEVICE(d
), get_system_memory(),
640 pci_address_space_io(dev
));
642 memory_region_init_io(&d
->rcr_mem
, OBJECT(dev
), &rcr_ops
, d
,
643 "piix3-reset-control", 1);
644 memory_region_add_subregion_overlap(pci_address_space_io(dev
), RCR_IOPORT
,
647 qemu_register_reset(piix3_reset
, d
);
650 static void piix3_class_init(ObjectClass
*klass
, void *data
)
652 DeviceClass
*dc
= DEVICE_CLASS(klass
);
653 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
655 dc
->desc
= "ISA bridge";
656 dc
->vmsd
= &vmstate_piix3
;
657 dc
->hotpluggable
= false;
658 k
->realize
= piix3_realize
;
659 k
->config_write
= piix3_write_config
;
660 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
661 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
662 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_0
;
663 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
665 * Reason: part of PIIX3 southbridge, needs to be wired up by
666 * pc_piix.c's pc_init1()
668 dc
->cannot_instantiate_with_device_add_yet
= true;
671 static const TypeInfo piix3_info
= {
673 .parent
= TYPE_PCI_DEVICE
,
674 .instance_size
= sizeof(PIIX3State
),
675 .class_init
= piix3_class_init
,
678 static void piix3_xen_class_init(ObjectClass
*klass
, void *data
)
680 DeviceClass
*dc
= DEVICE_CLASS(klass
);
681 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
683 dc
->desc
= "ISA bridge";
684 dc
->vmsd
= &vmstate_piix3
;
685 dc
->hotpluggable
= false;
686 k
->realize
= piix3_realize
;
687 k
->config_write
= piix3_write_config_xen
;
688 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
689 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
690 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_0
;
691 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
693 * Reason: part of PIIX3 southbridge, needs to be wired up by
694 * pc_piix.c's pc_init1()
696 dc
->cannot_instantiate_with_device_add_yet
= true;
699 static const TypeInfo piix3_xen_info
= {
701 .parent
= TYPE_PCI_DEVICE
,
702 .instance_size
= sizeof(PIIX3State
),
703 .class_init
= piix3_xen_class_init
,
706 static void i440fx_class_init(ObjectClass
*klass
, void *data
)
708 DeviceClass
*dc
= DEVICE_CLASS(klass
);
709 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
711 k
->realize
= i440fx_realize
;
712 k
->config_write
= i440fx_write_config
;
713 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
714 k
->device_id
= PCI_DEVICE_ID_INTEL_82441
;
716 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
717 dc
->desc
= "Host bridge";
718 dc
->vmsd
= &vmstate_i440fx
;
720 * PCI-facing part of the host bridge, not usable without the
721 * host-facing part, which can't be device_add'ed, yet.
723 dc
->cannot_instantiate_with_device_add_yet
= true;
724 dc
->hotpluggable
= false;
727 static const TypeInfo i440fx_info
= {
728 .name
= TYPE_I440FX_PCI_DEVICE
,
729 .parent
= TYPE_PCI_DEVICE
,
730 .instance_size
= sizeof(PCII440FXState
),
731 .class_init
= i440fx_class_init
,
734 static const char *i440fx_pcihost_root_bus_path(PCIHostState
*host_bridge
,
737 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(host_bridge
);
739 /* For backwards compat with old device paths */
740 if (s
->short_root_bus
) {
746 static Property i440fx_props
[] = {
747 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE
, I440FXState
,
748 pci_hole64_size
, DEFAULT_PCI_HOLE64_SIZE
),
749 DEFINE_PROP_UINT32("short_root_bus", I440FXState
, short_root_bus
, 0),
750 DEFINE_PROP_END_OF_LIST(),
753 static void i440fx_pcihost_class_init(ObjectClass
*klass
, void *data
)
755 DeviceClass
*dc
= DEVICE_CLASS(klass
);
756 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
758 hc
->root_bus_path
= i440fx_pcihost_root_bus_path
;
759 dc
->realize
= i440fx_pcihost_realize
;
761 dc
->props
= i440fx_props
;
764 static const TypeInfo i440fx_pcihost_info
= {
765 .name
= TYPE_I440FX_PCI_HOST_BRIDGE
,
766 .parent
= TYPE_PCI_HOST_BRIDGE
,
767 .instance_size
= sizeof(I440FXState
),
768 .instance_init
= i440fx_pcihost_initfn
,
769 .class_init
= i440fx_pcihost_class_init
,
772 static void i440fx_register_types(void)
774 type_register_static(&i440fx_info
);
775 type_register_static(&piix3_info
);
776 type_register_static(&piix3_xen_info
);
777 type_register_static(&i440fx_pcihost_info
);
780 type_init(i440fx_register_types
)