target-lm32/cpu.h

   1 /*
   2  *  LatticeMico32 virtual CPU header.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_LM32_H
  21 #define CPU_LM32_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUArchState struct CPULM32State
  26
  27 #include "config.h"
  28 #include "qemu-common.h"
  29 #include "exec/cpu-defs.h"
  30 struct CPULM32State;
  31 typedef struct CPULM32State CPULM32State;
  32
  33 #define NB_MMU_MODES 1
  34 #define TARGET_PAGE_BITS 12
  35 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch)
  36 {
  37     return 0;
  38 }
  39
  40 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  41 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  42
  43 /* Exceptions indices */
  44 enum {
  45     EXCP_RESET = 0,
  46     EXCP_BREAKPOINT,
  47     EXCP_INSN_BUS_ERROR,
  48     EXCP_WATCHPOINT,
  49     EXCP_DATA_BUS_ERROR,
  50     EXCP_DIVIDE_BY_ZERO,
  51     EXCP_IRQ,
  52     EXCP_SYSTEMCALL
  53 };
  54
  55 /* Registers */
  56 enum {
  57     R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
  58     R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
  59     R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
  60     R_R31
  61 };
  62
  63 /* Register aliases */
  64 enum {
  65     R_GP = R_R26,
  66     R_FP = R_R27,
  67     R_SP = R_R28,
  68     R_RA = R_R29,
  69     R_EA = R_R30,
  70     R_BA = R_R31
  71 };
  72
  73 /* IE flags */
  74 enum {
  75     IE_IE  = (1<<0),
  76     IE_EIE = (1<<1),
  77     IE_BIE = (1<<2),
  78 };
  79
  80 /* DC flags */
  81 enum {
  82     DC_SS  = (1<<0),
  83     DC_RE  = (1<<1),
  84     DC_C0  = (1<<2),
  85     DC_C1  = (1<<3),
  86     DC_C2  = (1<<4),
  87     DC_C3  = (1<<5),
  88 };
  89
  90 /* CFG mask */
  91 enum {
  92     CFG_M         = (1<<0),
  93     CFG_D         = (1<<1),
  94     CFG_S         = (1<<2),
  95     CFG_U         = (1<<3),
  96     CFG_X         = (1<<4),
  97     CFG_CC        = (1<<5),
  98     CFG_IC        = (1<<6),
  99     CFG_DC        = (1<<7),
 100     CFG_G         = (1<<8),
 101     CFG_H         = (1<<9),
 102     CFG_R         = (1<<10),
 103     CFG_J         = (1<<11),
 104     CFG_INT_SHIFT = 12,
 105     CFG_BP_SHIFT  = 18,
 106     CFG_WP_SHIFT  = 22,
 107     CFG_REV_SHIFT = 26,
 108 };
 109
 110 /* CSRs */
 111 enum {
 112     CSR_IE   = 0x00,
 113     CSR_IM   = 0x01,
 114     CSR_IP   = 0x02,
 115     CSR_ICC  = 0x03,
 116     CSR_DCC  = 0x04,
 117     CSR_CC   = 0x05,
 118     CSR_CFG  = 0x06,
 119     CSR_EBA  = 0x07,
 120     CSR_DC   = 0x08,
 121     CSR_DEBA = 0x09,
 122     CSR_JTX  = 0x0e,
 123     CSR_JRX  = 0x0f,
 124     CSR_BP0  = 0x10,
 125     CSR_BP1  = 0x11,
 126     CSR_BP2  = 0x12,
 127     CSR_BP3  = 0x13,
 128     CSR_WP0  = 0x18,
 129     CSR_WP1  = 0x19,
 130     CSR_WP2  = 0x1a,
 131     CSR_WP3  = 0x1b,
 132 };
 133
 134 enum {
 135     LM32_FEATURE_MULTIPLY     =  1,
 136     LM32_FEATURE_DIVIDE       =  2,
 137     LM32_FEATURE_SHIFT        =  4,
 138     LM32_FEATURE_SIGN_EXTEND  =  8,
 139     LM32_FEATURE_I_CACHE      = 16,
 140     LM32_FEATURE_D_CACHE      = 32,
 141     LM32_FEATURE_CYCLE_COUNT  = 64,
 142 };
 143
 144 enum {
 145     LM32_FLAG_IGNORE_MSB = 1,
 146 };
 147
 148 struct CPULM32State {
 149     /* general registers */
 150     uint32_t regs[32];
 151
 152     /* special registers */
 153     uint32_t pc;        /* program counter */
 154     uint32_t ie;        /* interrupt enable */
 155     uint32_t icc;       /* instruction cache control */
 156     uint32_t dcc;       /* data cache control */
 157     uint32_t cc;        /* cycle counter */
 158     uint32_t cfg;       /* configuration */
 159
 160     /* debug registers */
 161     uint32_t dc;        /* debug control */
 162     uint32_t bp[4];     /* breakpoints */
 163     uint32_t wp[4];     /* watchpoints */
 164
 165     struct CPUBreakpoint *cpu_breakpoint[4];
 166     struct CPUWatchpoint *cpu_watchpoint[4];
 167
 168     CPU_COMMON
 169
 170     /* Fields from here on are preserved across CPU reset. */
 171     uint32_t eba;       /* exception base address */
 172     uint32_t deba;      /* debug exception base address */
 173
 174     /* interrupt controller handle for callbacks */
 175     DeviceState *pic_state;
 176     /* JTAG UART handle for callbacks */
 177     DeviceState *juart_state;
 178
 179     /* processor core features */
 180     uint32_t flags;
 181
 182 };
 183
 184 typedef enum {
 185     LM32_WP_DISABLED = 0,
 186     LM32_WP_READ,
 187     LM32_WP_WRITE,
 188     LM32_WP_READ_WRITE,
 189 } lm32_wp_t;
 190
 191 static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
 192 {
 193     assert(idx < 4);
 194     return (dc >> (idx+1)*2) & 0x3;
 195 }
 196
 197 #include "cpu-qom.h"
 198
 199 LM32CPU *cpu_lm32_init(const char *cpu_model);
 200 int cpu_lm32_exec(CPUState *cpu);
 201 /* you can call this signal handler from your SIGBUS and SIGSEGV
 202    signal handlers to inform the virtual CPU of exceptions. non zero
 203    is returned if the signal was handled by the virtual CPU.  */
 204 int cpu_lm32_signal_handler(int host_signum, void *pinfo,
 205                           void *puc);
 206 void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 207 void lm32_translate_init(void);
 208 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
 209 void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
 210 void lm32_debug_excp_handler(CPUState *cs);
 211 void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
 212 void lm32_breakpoint_remove(CPULM32State *env, int index);
 213 void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
 214         lm32_wp_t wp_type);
 215 void lm32_watchpoint_remove(CPULM32State *env, int index);
 216 bool lm32_cpu_do_semihosting(CPUState *cs);
 217
 218 #define cpu_init(cpu_model) CPU(cpu_lm32_init(cpu_model))
 219
 220 #define cpu_list lm32_cpu_list
 221 #define cpu_exec cpu_lm32_exec
 222 #define cpu_signal_handler cpu_lm32_signal_handler
 223
 224 int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 225                               int mmu_idx);
 226
 227 #include "exec/cpu-all.h"
 228
 229 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
 230                                         target_ulong *cs_base, int *flags)
 231 {
 232     *pc = env->pc;
 233     *cs_base = 0;
 234     *flags = 0;
 235 }
 236
 237 #include "exec/exec-all.h"
 238
 239 #endif