hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21 #include "blockdev.h"
  22
  23 #define MP_MISC_BASE            0x80002000
  24 #define MP_MISC_SIZE            0x00001000
  25
  26 #define MP_ETH_BASE             0x80008000
  27 #define MP_ETH_SIZE             0x00001000
  28
  29 #define MP_WLAN_BASE            0x8000C000
  30 #define MP_WLAN_SIZE            0x00000800
  31
  32 #define MP_UART1_BASE           0x8000C840
  33 #define MP_UART2_BASE           0x8000C940
  34
  35 #define MP_GPIO_BASE            0x8000D000
  36 #define MP_GPIO_SIZE            0x00001000
  37
  38 #define MP_FLASHCFG_BASE        0x90006000
  39 #define MP_FLASHCFG_SIZE        0x00001000
  40
  41 #define MP_AUDIO_BASE           0x90007000
  42
  43 #define MP_PIC_BASE             0x90008000
  44 #define MP_PIC_SIZE             0x00001000
  45
  46 #define MP_PIT_BASE             0x90009000
  47 #define MP_PIT_SIZE             0x00001000
  48
  49 #define MP_LCD_BASE             0x9000c000
  50 #define MP_LCD_SIZE             0x00001000
  51
  52 #define MP_SRAM_BASE            0xC0000000
  53 #define MP_SRAM_SIZE            0x00020000
  54
  55 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  56 #define MP_FLASH_SIZE_MAX       32*1024*1024
  57
  58 #define MP_TIMER1_IRQ           4
  59 #define MP_TIMER2_IRQ           5
  60 #define MP_TIMER3_IRQ           6
  61 #define MP_TIMER4_IRQ           7
  62 #define MP_EHCI_IRQ             8
  63 #define MP_ETH_IRQ              9
  64 #define MP_UART1_IRQ            11
  65 #define MP_UART2_IRQ            11
  66 #define MP_GPIO_IRQ             12
  67 #define MP_RTC_IRQ              28
  68 #define MP_AUDIO_IRQ            30
  69
  70 /* Wolfson 8750 I2C address */
  71 #define MP_WM_ADDR              0x1A
  72
  73 /* Ethernet register offsets */
  74 #define MP_ETH_SMIR             0x010
  75 #define MP_ETH_PCXR             0x408
  76 #define MP_ETH_SDCMR            0x448
  77 #define MP_ETH_ICR              0x450
  78 #define MP_ETH_IMR              0x458
  79 #define MP_ETH_FRDP0            0x480
  80 #define MP_ETH_FRDP1            0x484
  81 #define MP_ETH_FRDP2            0x488
  82 #define MP_ETH_FRDP3            0x48C
  83 #define MP_ETH_CRDP0            0x4A0
  84 #define MP_ETH_CRDP1            0x4A4
  85 #define MP_ETH_CRDP2            0x4A8
  86 #define MP_ETH_CRDP3            0x4AC
  87 #define MP_ETH_CTDP0            0x4E0
  88 #define MP_ETH_CTDP1            0x4E4
  89 #define MP_ETH_CTDP2            0x4E8
  90 #define MP_ETH_CTDP3            0x4EC
  91
  92 /* MII PHY access */
  93 #define MP_ETH_SMIR_DATA        0x0000FFFF
  94 #define MP_ETH_SMIR_ADDR        0x03FF0000
  95 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  96 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  97
  98 /* PHY registers */
  99 #define MP_ETH_PHY1_BMSR        0x00210000
 100 #define MP_ETH_PHY1_PHYSID1     0x00410000
 101 #define MP_ETH_PHY1_PHYSID2     0x00610000
 102
 103 #define MP_PHY_BMSR_LINK        0x0004
 104 #define MP_PHY_BMSR_AUTONEG     0x0008
 105
 106 #define MP_PHY_88E3015          0x01410E20
 107
 108 /* TX descriptor status */
 109 #define MP_ETH_TX_OWN           (1 << 31)
 110
 111 /* RX descriptor status */
 112 #define MP_ETH_RX_OWN           (1 << 31)
 113
 114 /* Interrupt cause/mask bits */
 115 #define MP_ETH_IRQ_RX_BIT       0
 116 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 117 #define MP_ETH_IRQ_TXHI_BIT     2
 118 #define MP_ETH_IRQ_TXLO_BIT     3
 119
 120 /* Port config bits */
 121 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 122
 123 /* SDMA command bits */
 124 #define MP_ETH_CMD_TXHI         (1 << 23)
 125 #define MP_ETH_CMD_TXLO         (1 << 22)
 126
 127 typedef struct mv88w8618_tx_desc {
 128     uint32_t cmdstat;
 129     uint16_t res;
 130     uint16_t bytes;
 131     uint32_t buffer;
 132     uint32_t next;
 133 } mv88w8618_tx_desc;
 134
 135 typedef struct mv88w8618_rx_desc {
 136     uint32_t cmdstat;
 137     uint16_t bytes;
 138     uint16_t buffer_size;
 139     uint32_t buffer;
 140     uint32_t next;
 141 } mv88w8618_rx_desc;
 142
 143 typedef struct mv88w8618_eth_state {
 144     SysBusDevice busdev;
 145     qemu_irq irq;
 146     uint32_t smir;
 147     uint32_t icr;
 148     uint32_t imr;
 149     int mmio_index;
 150     uint32_t vlan_header;
 151     uint32_t tx_queue[2];
 152     uint32_t rx_queue[4];
 153     uint32_t frx_queue[4];
 154     uint32_t cur_rx[4];
 155     NICState *nic;
 156     NICConf conf;
 157 } mv88w8618_eth_state;
 158
 159 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 160 {
 161     cpu_to_le32s(&desc->cmdstat);
 162     cpu_to_le16s(&desc->bytes);
 163     cpu_to_le16s(&desc->buffer_size);
 164     cpu_to_le32s(&desc->buffer);
 165     cpu_to_le32s(&desc->next);
 166     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 167 }
 168
 169 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 170 {
 171     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 172     le32_to_cpus(&desc->cmdstat);
 173     le16_to_cpus(&desc->bytes);
 174     le16_to_cpus(&desc->buffer_size);
 175     le32_to_cpus(&desc->buffer);
 176     le32_to_cpus(&desc->next);
 177 }
 178
 179 static int eth_can_receive(VLANClientState *nc)
 180 {
 181     return 1;
 182 }
 183
 184 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 185 {
 186     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 187     uint32_t desc_addr;
 188     mv88w8618_rx_desc desc;
 189     int i;
 190
 191     for (i = 0; i < 4; i++) {
 192         desc_addr = s->cur_rx[i];
 193         if (!desc_addr) {
 194             continue;
 195         }
 196         do {
 197             eth_rx_desc_get(desc_addr, &desc);
 198             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 199                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 200                                           buf, size);
 201                 desc.bytes = size + s->vlan_header;
 202                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 203                 s->cur_rx[i] = desc.next;
 204
 205                 s->icr |= MP_ETH_IRQ_RX;
 206                 if (s->icr & s->imr) {
 207                     qemu_irq_raise(s->irq);
 208                 }
 209                 eth_rx_desc_put(desc_addr, &desc);
 210                 return size;
 211             }
 212             desc_addr = desc.next;
 213         } while (desc_addr != s->rx_queue[i]);
 214     }
 215     return size;
 216 }
 217
 218 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 219 {
 220     cpu_to_le32s(&desc->cmdstat);
 221     cpu_to_le16s(&desc->res);
 222     cpu_to_le16s(&desc->bytes);
 223     cpu_to_le32s(&desc->buffer);
 224     cpu_to_le32s(&desc->next);
 225     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 226 }
 227
 228 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 229 {
 230     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 231     le32_to_cpus(&desc->cmdstat);
 232     le16_to_cpus(&desc->res);
 233     le16_to_cpus(&desc->bytes);
 234     le32_to_cpus(&desc->buffer);
 235     le32_to_cpus(&desc->next);
 236 }
 237
 238 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 239 {
 240     uint32_t desc_addr = s->tx_queue[queue_index];
 241     mv88w8618_tx_desc desc;
 242     uint32_t next_desc;
 243     uint8_t buf[2048];
 244     int len;
 245
 246     do {
 247         eth_tx_desc_get(desc_addr, &desc);
 248         next_desc = desc.next;
 249         if (desc.cmdstat & MP_ETH_TX_OWN) {
 250             len = desc.bytes;
 251             if (len < 2048) {
 252                 cpu_physical_memory_read(desc.buffer, buf, len);
 253                 qemu_send_packet(&s->nic->nc, buf, len);
 254             }
 255             desc.cmdstat &= ~MP_ETH_TX_OWN;
 256             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 257             eth_tx_desc_put(desc_addr, &desc);
 258         }
 259         desc_addr = next_desc;
 260     } while (desc_addr != s->tx_queue[queue_index]);
 261 }
 262
 263 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 264 {
 265     mv88w8618_eth_state *s = opaque;
 266
 267     switch (offset) {
 268     case MP_ETH_SMIR:
 269         if (s->smir & MP_ETH_SMIR_OPCODE) {
 270             switch (s->smir & MP_ETH_SMIR_ADDR) {
 271             case MP_ETH_PHY1_BMSR:
 272                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 273                        MP_ETH_SMIR_RDVALID;
 274             case MP_ETH_PHY1_PHYSID1:
 275                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 276             case MP_ETH_PHY1_PHYSID2:
 277                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 278             default:
 279                 return MP_ETH_SMIR_RDVALID;
 280             }
 281         }
 282         return 0;
 283
 284     case MP_ETH_ICR:
 285         return s->icr;
 286
 287     case MP_ETH_IMR:
 288         return s->imr;
 289
 290     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 291         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 292
 293     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 294         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 295
 296     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 297         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 298
 299     default:
 300         return 0;
 301     }
 302 }
 303
 304 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 305                                 uint32_t value)
 306 {
 307     mv88w8618_eth_state *s = opaque;
 308
 309     switch (offset) {
 310     case MP_ETH_SMIR:
 311         s->smir = value;
 312         break;
 313
 314     case MP_ETH_PCXR:
 315         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 316         break;
 317
 318     case MP_ETH_SDCMR:
 319         if (value & MP_ETH_CMD_TXHI) {
 320             eth_send(s, 1);
 321         }
 322         if (value & MP_ETH_CMD_TXLO) {
 323             eth_send(s, 0);
 324         }
 325         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 326             qemu_irq_raise(s->irq);
 327         }
 328         break;
 329
 330     case MP_ETH_ICR:
 331         s->icr &= value;
 332         break;
 333
 334     case MP_ETH_IMR:
 335         s->imr = value;
 336         if (s->icr & s->imr) {
 337             qemu_irq_raise(s->irq);
 338         }
 339         break;
 340
 341     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 342         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 343         break;
 344
 345     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 346         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 347             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 348         break;
 349
 350     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 351         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 352         break;
 353     }
 354 }
 355
 356 static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
 357     mv88w8618_eth_read,
 358     mv88w8618_eth_read,
 359     mv88w8618_eth_read
 360 };
 361
 362 static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
 363     mv88w8618_eth_write,
 364     mv88w8618_eth_write,
 365     mv88w8618_eth_write
 366 };
 367
 368 static void eth_cleanup(VLANClientState *nc)
 369 {
 370     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 371
 372     s->nic = NULL;
 373 }
 374
 375 static NetClientInfo net_mv88w8618_info = {
 376     .type = NET_CLIENT_TYPE_NIC,
 377     .size = sizeof(NICState),
 378     .can_receive = eth_can_receive,
 379     .receive = eth_receive,
 380     .cleanup = eth_cleanup,
 381 };
 382
 383 static int mv88w8618_eth_init(SysBusDevice *dev)
 384 {
 385     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 386
 387     sysbus_init_irq(dev, &s->irq);
 388     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 389                           dev->qdev.info->name, dev->qdev.id, s);
 390     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 391                                            mv88w8618_eth_writefn, s,
 392                                            DEVICE_NATIVE_ENDIAN);
 393     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 394     return 0;
 395 }
 396
 397 static const VMStateDescription mv88w8618_eth_vmsd = {
 398     .name = "mv88w8618_eth",
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .minimum_version_id_old = 1,
 402     .fields = (VMStateField[]) {
 403         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 404         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 405         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 406         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 407         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 408         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 409         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 410         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 411         VMSTATE_END_OF_LIST()
 412     }
 413 };
 414
 415 static SysBusDeviceInfo mv88w8618_eth_info = {
 416     .init = mv88w8618_eth_init,
 417     .qdev.name = "mv88w8618_eth",
 418     .qdev.size = sizeof(mv88w8618_eth_state),
 419     .qdev.vmsd = &mv88w8618_eth_vmsd,
 420     .qdev.props = (Property[]) {
 421         DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 422         DEFINE_PROP_END_OF_LIST(),
 423     },
 424 };
 425
 426 /* LCD register offsets */
 427 #define MP_LCD_IRQCTRL          0x180
 428 #define MP_LCD_IRQSTAT          0x184
 429 #define MP_LCD_SPICTRL          0x1ac
 430 #define MP_LCD_INST             0x1bc
 431 #define MP_LCD_DATA             0x1c0
 432
 433 /* Mode magics */
 434 #define MP_LCD_SPI_DATA         0x00100011
 435 #define MP_LCD_SPI_CMD          0x00104011
 436 #define MP_LCD_SPI_INVALID      0x00000000
 437
 438 /* Commmands */
 439 #define MP_LCD_INST_SETPAGE0    0xB0
 440 /* ... */
 441 #define MP_LCD_INST_SETPAGE7    0xB7
 442
 443 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 444
 445 typedef struct musicpal_lcd_state {
 446     SysBusDevice busdev;
 447     uint32_t brightness;
 448     uint32_t mode;
 449     uint32_t irqctrl;
 450     uint32_t page;
 451     uint32_t page_off;
 452     DisplayState *ds;
 453     uint8_t video_ram[128*64/8];
 454 } musicpal_lcd_state;
 455
 456 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 457 {
 458     switch (s->brightness) {
 459     case 7:
 460         return col;
 461     case 0:
 462         return 0;
 463     default:
 464         return (col * s->brightness) / 7;
 465     }
 466 }
 467
 468 #define SET_LCD_PIXEL(depth, type) \
 469 static inline void glue(set_lcd_pixel, depth) \
 470         (musicpal_lcd_state *s, int x, int y, type col) \
 471 { \
 472     int dx, dy; \
 473     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 474 \
 475     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 476         for (dx = 0; dx < 3; dx++, pixel++) \
 477             *pixel = col; \
 478 }
 479 SET_LCD_PIXEL(8, uint8_t)
 480 SET_LCD_PIXEL(16, uint16_t)
 481 SET_LCD_PIXEL(32, uint32_t)
 482
 483 #include "pixel_ops.h"
 484
 485 static void lcd_refresh(void *opaque)
 486 {
 487     musicpal_lcd_state *s = opaque;
 488     int x, y, col;
 489
 490     switch (ds_get_bits_per_pixel(s->ds)) {
 491     case 0:
 492         return;
 493 #define LCD_REFRESH(depth, func) \
 494     case depth: \
 495         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 496                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 497                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 498         for (x = 0; x < 128; x++) { \
 499             for (y = 0; y < 64; y++) { \
 500                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 501                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 502                 } else { \
 503                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 504                 } \
 505             } \
 506         } \
 507         break;
 508     LCD_REFRESH(8, rgb_to_pixel8)
 509     LCD_REFRESH(16, rgb_to_pixel16)
 510     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 511                      rgb_to_pixel32bgr : rgb_to_pixel32))
 512     default:
 513         hw_error("unsupported colour depth %i\n",
 514                   ds_get_bits_per_pixel(s->ds));
 515     }
 516
 517     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 518 }
 519
 520 static void lcd_invalidate(void *opaque)
 521 {
 522 }
 523
 524 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 525 {
 526     musicpal_lcd_state *s = opaque;
 527     s->brightness &= ~(1 << irq);
 528     s->brightness |= level << irq;
 529 }
 530
 531 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 532 {
 533     musicpal_lcd_state *s = opaque;
 534
 535     switch (offset) {
 536     case MP_LCD_IRQCTRL:
 537         return s->irqctrl;
 538
 539     default:
 540         return 0;
 541     }
 542 }
 543
 544 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 545                                uint32_t value)
 546 {
 547     musicpal_lcd_state *s = opaque;
 548
 549     switch (offset) {
 550     case MP_LCD_IRQCTRL:
 551         s->irqctrl = value;
 552         break;
 553
 554     case MP_LCD_SPICTRL:
 555         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 556             s->mode = value;
 557         } else {
 558             s->mode = MP_LCD_SPI_INVALID;
 559         }
 560         break;
 561
 562     case MP_LCD_INST:
 563         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 564             s->page = value - MP_LCD_INST_SETPAGE0;
 565             s->page_off = 0;
 566         }
 567         break;
 568
 569     case MP_LCD_DATA:
 570         if (s->mode == MP_LCD_SPI_CMD) {
 571             if (value >= MP_LCD_INST_SETPAGE0 &&
 572                 value <= MP_LCD_INST_SETPAGE7) {
 573                 s->page = value - MP_LCD_INST_SETPAGE0;
 574                 s->page_off = 0;
 575             }
 576         } else if (s->mode == MP_LCD_SPI_DATA) {
 577             s->video_ram[s->page*128 + s->page_off] = value;
 578             s->page_off = (s->page_off + 1) & 127;
 579         }
 580         break;
 581     }
 582 }
 583
 584 static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
 585     musicpal_lcd_read,
 586     musicpal_lcd_read,
 587     musicpal_lcd_read
 588 };
 589
 590 static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
 591     musicpal_lcd_write,
 592     musicpal_lcd_write,
 593     musicpal_lcd_write
 594 };
 595
 596 static int musicpal_lcd_init(SysBusDevice *dev)
 597 {
 598     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 599     int iomemtype;
 600
 601     s->brightness = 7;
 602
 603     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 604                                        musicpal_lcd_writefn, s,
 605                                        DEVICE_NATIVE_ENDIAN);
 606     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 607
 608     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 609                                  NULL, NULL, s);
 610     qemu_console_resize(s->ds, 128*3, 64*3);
 611
 612     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 613
 614     return 0;
 615 }
 616
 617 static const VMStateDescription musicpal_lcd_vmsd = {
 618     .name = "musicpal_lcd",
 619     .version_id = 1,
 620     .minimum_version_id = 1,
 621     .minimum_version_id_old = 1,
 622     .fields = (VMStateField[]) {
 623         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 624         VMSTATE_UINT32(mode, musicpal_lcd_state),
 625         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 626         VMSTATE_UINT32(page, musicpal_lcd_state),
 627         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 628         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 629         VMSTATE_END_OF_LIST()
 630     }
 631 };
 632
 633 static SysBusDeviceInfo musicpal_lcd_info = {
 634     .init = musicpal_lcd_init,
 635     .qdev.name = "musicpal_lcd",
 636     .qdev.size = sizeof(musicpal_lcd_state),
 637     .qdev.vmsd = &musicpal_lcd_vmsd,
 638 };
 639
 640 /* PIC register offsets */
 641 #define MP_PIC_STATUS           0x00
 642 #define MP_PIC_ENABLE_SET       0x08
 643 #define MP_PIC_ENABLE_CLR       0x0C
 644
 645 typedef struct mv88w8618_pic_state
 646 {
 647     SysBusDevice busdev;
 648     uint32_t level;
 649     uint32_t enabled;
 650     qemu_irq parent_irq;
 651 } mv88w8618_pic_state;
 652
 653 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 654 {
 655     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 656 }
 657
 658 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 659 {
 660     mv88w8618_pic_state *s = opaque;
 661
 662     if (level) {
 663         s->level |= 1 << irq;
 664     } else {
 665         s->level &= ~(1 << irq);
 666     }
 667     mv88w8618_pic_update(s);
 668 }
 669
 670 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 671 {
 672     mv88w8618_pic_state *s = opaque;
 673
 674     switch (offset) {
 675     case MP_PIC_STATUS:
 676         return s->level & s->enabled;
 677
 678     default:
 679         return 0;
 680     }
 681 }
 682
 683 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 684                                 uint32_t value)
 685 {
 686     mv88w8618_pic_state *s = opaque;
 687
 688     switch (offset) {
 689     case MP_PIC_ENABLE_SET:
 690         s->enabled |= value;
 691         break;
 692
 693     case MP_PIC_ENABLE_CLR:
 694         s->enabled &= ~value;
 695         s->level &= ~value;
 696         break;
 697     }
 698     mv88w8618_pic_update(s);
 699 }
 700
 701 static void mv88w8618_pic_reset(DeviceState *d)
 702 {
 703     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 704                                          sysbus_from_qdev(d));
 705
 706     s->level = 0;
 707     s->enabled = 0;
 708 }
 709
 710 static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
 711     mv88w8618_pic_read,
 712     mv88w8618_pic_read,
 713     mv88w8618_pic_read
 714 };
 715
 716 static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
 717     mv88w8618_pic_write,
 718     mv88w8618_pic_write,
 719     mv88w8618_pic_write
 720 };
 721
 722 static int mv88w8618_pic_init(SysBusDevice *dev)
 723 {
 724     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 725     int iomemtype;
 726
 727     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 728     sysbus_init_irq(dev, &s->parent_irq);
 729     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
 730                                        mv88w8618_pic_writefn, s,
 731                                        DEVICE_NATIVE_ENDIAN);
 732     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
 733     return 0;
 734 }
 735
 736 static const VMStateDescription mv88w8618_pic_vmsd = {
 737     .name = "mv88w8618_pic",
 738     .version_id = 1,
 739     .minimum_version_id = 1,
 740     .minimum_version_id_old = 1,
 741     .fields = (VMStateField[]) {
 742         VMSTATE_UINT32(level, mv88w8618_pic_state),
 743         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 744         VMSTATE_END_OF_LIST()
 745     }
 746 };
 747
 748 static SysBusDeviceInfo mv88w8618_pic_info = {
 749     .init = mv88w8618_pic_init,
 750     .qdev.name = "mv88w8618_pic",
 751     .qdev.size = sizeof(mv88w8618_pic_state),
 752     .qdev.reset = mv88w8618_pic_reset,
 753     .qdev.vmsd = &mv88w8618_pic_vmsd,
 754 };
 755
 756 /* PIT register offsets */
 757 #define MP_PIT_TIMER1_LENGTH    0x00
 758 /* ... */
 759 #define MP_PIT_TIMER4_LENGTH    0x0C
 760 #define MP_PIT_CONTROL          0x10
 761 #define MP_PIT_TIMER1_VALUE     0x14
 762 /* ... */
 763 #define MP_PIT_TIMER4_VALUE     0x20
 764 #define MP_BOARD_RESET          0x34
 765
 766 /* Magic board reset value (probably some watchdog behind it) */
 767 #define MP_BOARD_RESET_MAGIC    0x10000
 768
 769 typedef struct mv88w8618_timer_state {
 770     ptimer_state *ptimer;
 771     uint32_t limit;
 772     int freq;
 773     qemu_irq irq;
 774 } mv88w8618_timer_state;
 775
 776 typedef struct mv88w8618_pit_state {
 777     SysBusDevice busdev;
 778     mv88w8618_timer_state timer[4];
 779 } mv88w8618_pit_state;
 780
 781 static void mv88w8618_timer_tick(void *opaque)
 782 {
 783     mv88w8618_timer_state *s = opaque;
 784
 785     qemu_irq_raise(s->irq);
 786 }
 787
 788 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 789                                  uint32_t freq)
 790 {
 791     QEMUBH *bh;
 792
 793     sysbus_init_irq(dev, &s->irq);
 794     s->freq = freq;
 795
 796     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 797     s->ptimer = ptimer_init(bh);
 798 }
 799
 800 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
 801 {
 802     mv88w8618_pit_state *s = opaque;
 803     mv88w8618_timer_state *t;
 804
 805     switch (offset) {
 806     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 807         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 808         return ptimer_get_count(t->ptimer);
 809
 810     default:
 811         return 0;
 812     }
 813 }
 814
 815 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 816                                 uint32_t value)
 817 {
 818     mv88w8618_pit_state *s = opaque;
 819     mv88w8618_timer_state *t;
 820     int i;
 821
 822     switch (offset) {
 823     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 824         t = &s->timer[offset >> 2];
 825         t->limit = value;
 826         if (t->limit > 0) {
 827             ptimer_set_limit(t->ptimer, t->limit, 1);
 828         } else {
 829             ptimer_stop(t->ptimer);
 830         }
 831         break;
 832
 833     case MP_PIT_CONTROL:
 834         for (i = 0; i < 4; i++) {
 835             t = &s->timer[i];
 836             if (value & 0xf && t->limit > 0) {
 837                 ptimer_set_limit(t->ptimer, t->limit, 0);
 838                 ptimer_set_freq(t->ptimer, t->freq);
 839                 ptimer_run(t->ptimer, 0);
 840             } else {
 841                 ptimer_stop(t->ptimer);
 842             }
 843             value >>= 4;
 844         }
 845         break;
 846
 847     case MP_BOARD_RESET:
 848         if (value == MP_BOARD_RESET_MAGIC) {
 849             qemu_system_reset_request();
 850         }
 851         break;
 852     }
 853 }
 854
 855 static void mv88w8618_pit_reset(DeviceState *d)
 856 {
 857     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 858                                          sysbus_from_qdev(d));
 859     int i;
 860
 861     for (i = 0; i < 4; i++) {
 862         ptimer_stop(s->timer[i].ptimer);
 863         s->timer[i].limit = 0;
 864     }
 865 }
 866
 867 static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
 868     mv88w8618_pit_read,
 869     mv88w8618_pit_read,
 870     mv88w8618_pit_read
 871 };
 872
 873 static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
 874     mv88w8618_pit_write,
 875     mv88w8618_pit_write,
 876     mv88w8618_pit_write
 877 };
 878
 879 static int mv88w8618_pit_init(SysBusDevice *dev)
 880 {
 881     int iomemtype;
 882     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 883     int i;
 884
 885     /* Letting them all run at 1 MHz is likely just a pragmatic
 886      * simplification. */
 887     for (i = 0; i < 4; i++) {
 888         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 889     }
 890
 891     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
 892                                        mv88w8618_pit_writefn, s,
 893                                        DEVICE_NATIVE_ENDIAN);
 894     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
 895     return 0;
 896 }
 897
 898 static const VMStateDescription mv88w8618_timer_vmsd = {
 899     .name = "timer",
 900     .version_id = 1,
 901     .minimum_version_id = 1,
 902     .minimum_version_id_old = 1,
 903     .fields = (VMStateField[]) {
 904         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 905         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 906         VMSTATE_END_OF_LIST()
 907     }
 908 };
 909
 910 static const VMStateDescription mv88w8618_pit_vmsd = {
 911     .name = "mv88w8618_pit",
 912     .version_id = 1,
 913     .minimum_version_id = 1,
 914     .minimum_version_id_old = 1,
 915     .fields = (VMStateField[]) {
 916         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 917                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 918         VMSTATE_END_OF_LIST()
 919     }
 920 };
 921
 922 static SysBusDeviceInfo mv88w8618_pit_info = {
 923     .init = mv88w8618_pit_init,
 924     .qdev.name  = "mv88w8618_pit",
 925     .qdev.size  = sizeof(mv88w8618_pit_state),
 926     .qdev.reset = mv88w8618_pit_reset,
 927     .qdev.vmsd  = &mv88w8618_pit_vmsd,
 928 };
 929
 930 /* Flash config register offsets */
 931 #define MP_FLASHCFG_CFGR0    0x04
 932
 933 typedef struct mv88w8618_flashcfg_state {
 934     SysBusDevice busdev;
 935     uint32_t cfgr0;
 936 } mv88w8618_flashcfg_state;
 937
 938 static uint32_t mv88w8618_flashcfg_read(void *opaque,
 939                                         target_phys_addr_t offset)
 940 {
 941     mv88w8618_flashcfg_state *s = opaque;
 942
 943     switch (offset) {
 944     case MP_FLASHCFG_CFGR0:
 945         return s->cfgr0;
 946
 947     default:
 948         return 0;
 949     }
 950 }
 951
 952 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 953                                      uint32_t value)
 954 {
 955     mv88w8618_flashcfg_state *s = opaque;
 956
 957     switch (offset) {
 958     case MP_FLASHCFG_CFGR0:
 959         s->cfgr0 = value;
 960         break;
 961     }
 962 }
 963
 964 static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
 965     mv88w8618_flashcfg_read,
 966     mv88w8618_flashcfg_read,
 967     mv88w8618_flashcfg_read
 968 };
 969
 970 static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
 971     mv88w8618_flashcfg_write,
 972     mv88w8618_flashcfg_write,
 973     mv88w8618_flashcfg_write
 974 };
 975
 976 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 977 {
 978     int iomemtype;
 979     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 980
 981     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 982     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
 983                                        mv88w8618_flashcfg_writefn, s,
 984                                        DEVICE_NATIVE_ENDIAN);
 985     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
 986     return 0;
 987 }
 988
 989 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
 990     .name = "mv88w8618_flashcfg",
 991     .version_id = 1,
 992     .minimum_version_id = 1,
 993     .minimum_version_id_old = 1,
 994     .fields = (VMStateField[]) {
 995         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
 996         VMSTATE_END_OF_LIST()
 997     }
 998 };
 999
1000 static SysBusDeviceInfo mv88w8618_flashcfg_info = {
1001     .init = mv88w8618_flashcfg_init,
1002     .qdev.name  = "mv88w8618_flashcfg",
1003     .qdev.size  = sizeof(mv88w8618_flashcfg_state),
1004     .qdev.vmsd  = &mv88w8618_flashcfg_vmsd,
1005 };
1006
1007 /* Misc register offsets */
1008 #define MP_MISC_BOARD_REVISION  0x18
1009
1010 #define MP_BOARD_REVISION       0x31
1011
1012 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1013 {
1014     switch (offset) {
1015     case MP_MISC_BOARD_REVISION:
1016         return MP_BOARD_REVISION;
1017
1018     default:
1019         return 0;
1020     }
1021 }
1022
1023 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1024                                 uint32_t value)
1025 {
1026 }
1027
1028 static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
1029     musicpal_misc_read,
1030     musicpal_misc_read,
1031     musicpal_misc_read,
1032 };
1033
1034 static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
1035     musicpal_misc_write,
1036     musicpal_misc_write,
1037     musicpal_misc_write,
1038 };
1039
1040 static void musicpal_misc_init(void)
1041 {
1042     int iomemtype;
1043
1044     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
1045                                        musicpal_misc_writefn, NULL,
1046                                        DEVICE_NATIVE_ENDIAN);
1047     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1048 }
1049
1050 /* WLAN register offsets */
1051 #define MP_WLAN_MAGIC1          0x11c
1052 #define MP_WLAN_MAGIC2          0x124
1053
1054 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1055 {
1056     switch (offset) {
1057     /* Workaround to allow loading the binary-only wlandrv.ko crap
1058      * from the original Freecom firmware. */
1059     case MP_WLAN_MAGIC1:
1060         return ~3;
1061     case MP_WLAN_MAGIC2:
1062         return -1;
1063
1064     default:
1065         return 0;
1066     }
1067 }
1068
1069 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1070                                  uint32_t value)
1071 {
1072 }
1073
1074 static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
1075     mv88w8618_wlan_read,
1076     mv88w8618_wlan_read,
1077     mv88w8618_wlan_read,
1078 };
1079
1080 static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
1081     mv88w8618_wlan_write,
1082     mv88w8618_wlan_write,
1083     mv88w8618_wlan_write,
1084 };
1085
1086 static int mv88w8618_wlan_init(SysBusDevice *dev)
1087 {
1088     int iomemtype;
1089
1090     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
1091                                        mv88w8618_wlan_writefn, NULL,
1092                                        DEVICE_NATIVE_ENDIAN);
1093     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
1094     return 0;
1095 }
1096
1097 /* GPIO register offsets */
1098 #define MP_GPIO_OE_LO           0x008
1099 #define MP_GPIO_OUT_LO          0x00c
1100 #define MP_GPIO_IN_LO           0x010
1101 #define MP_GPIO_IER_LO          0x014
1102 #define MP_GPIO_IMR_LO          0x018
1103 #define MP_GPIO_ISR_LO          0x020
1104 #define MP_GPIO_OE_HI           0x508
1105 #define MP_GPIO_OUT_HI          0x50c
1106 #define MP_GPIO_IN_HI           0x510
1107 #define MP_GPIO_IER_HI          0x514
1108 #define MP_GPIO_IMR_HI          0x518
1109 #define MP_GPIO_ISR_HI          0x520
1110
1111 /* GPIO bits & masks */
1112 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1113 #define MP_GPIO_I2C_DATA_BIT    29
1114 #define MP_GPIO_I2C_CLOCK_BIT   30
1115
1116 /* LCD brightness bits in GPIO_OE_HI */
1117 #define MP_OE_LCD_BRIGHTNESS    0x0007
1118
1119 typedef struct musicpal_gpio_state {
1120     SysBusDevice busdev;
1121     uint32_t lcd_brightness;
1122     uint32_t out_state;
1123     uint32_t in_state;
1124     uint32_t ier;
1125     uint32_t imr;
1126     uint32_t isr;
1127     qemu_irq irq;
1128     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1129 } musicpal_gpio_state;
1130
1131 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1132     int i;
1133     uint32_t brightness;
1134
1135     /* compute brightness ratio */
1136     switch (s->lcd_brightness) {
1137     case 0x00000007:
1138         brightness = 0;
1139         break;
1140
1141     case 0x00020000:
1142         brightness = 1;
1143         break;
1144
1145     case 0x00020001:
1146         brightness = 2;
1147         break;
1148
1149     case 0x00040000:
1150         brightness = 3;
1151         break;
1152
1153     case 0x00010006:
1154         brightness = 4;
1155         break;
1156
1157     case 0x00020005:
1158         brightness = 5;
1159         break;
1160
1161     case 0x00040003:
1162         brightness = 6;
1163         break;
1164
1165     case 0x00030004:
1166     default:
1167         brightness = 7;
1168     }
1169
1170     /* set lcd brightness GPIOs  */
1171     for (i = 0; i <= 2; i++) {
1172         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1173     }
1174 }
1175
1176 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1177 {
1178     musicpal_gpio_state *s = opaque;
1179     uint32_t mask = 1 << pin;
1180     uint32_t delta = level << pin;
1181     uint32_t old = s->in_state & mask;
1182
1183     s->in_state &= ~mask;
1184     s->in_state |= delta;
1185
1186     if ((old ^ delta) &&
1187         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1188         s->isr = mask;
1189         qemu_irq_raise(s->irq);
1190     }
1191 }
1192
1193 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1194 {
1195     musicpal_gpio_state *s = opaque;
1196
1197     switch (offset) {
1198     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1199         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1200
1201     case MP_GPIO_OUT_LO:
1202         return s->out_state & 0xFFFF;
1203     case MP_GPIO_OUT_HI:
1204         return s->out_state >> 16;
1205
1206     case MP_GPIO_IN_LO:
1207         return s->in_state & 0xFFFF;
1208     case MP_GPIO_IN_HI:
1209         return s->in_state >> 16;
1210
1211     case MP_GPIO_IER_LO:
1212         return s->ier & 0xFFFF;
1213     case MP_GPIO_IER_HI:
1214         return s->ier >> 16;
1215
1216     case MP_GPIO_IMR_LO:
1217         return s->imr & 0xFFFF;
1218     case MP_GPIO_IMR_HI:
1219         return s->imr >> 16;
1220
1221     case MP_GPIO_ISR_LO:
1222         return s->isr & 0xFFFF;
1223     case MP_GPIO_ISR_HI:
1224         return s->isr >> 16;
1225
1226     default:
1227         return 0;
1228     }
1229 }
1230
1231 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1232                                 uint32_t value)
1233 {
1234     musicpal_gpio_state *s = opaque;
1235     switch (offset) {
1236     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1237         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1238                          (value & MP_OE_LCD_BRIGHTNESS);
1239         musicpal_gpio_brightness_update(s);
1240         break;
1241
1242     case MP_GPIO_OUT_LO:
1243         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1244         break;
1245     case MP_GPIO_OUT_HI:
1246         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1247         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1248                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1249         musicpal_gpio_brightness_update(s);
1250         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1251         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1252         break;
1253
1254     case MP_GPIO_IER_LO:
1255         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1256         break;
1257     case MP_GPIO_IER_HI:
1258         s->ier = (s->ier & 0xFFFF) | (value << 16);
1259         break;
1260
1261     case MP_GPIO_IMR_LO:
1262         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1263         break;
1264     case MP_GPIO_IMR_HI:
1265         s->imr = (s->imr & 0xFFFF) | (value << 16);
1266         break;
1267     }
1268 }
1269
1270 static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
1271     musicpal_gpio_read,
1272     musicpal_gpio_read,
1273     musicpal_gpio_read,
1274 };
1275
1276 static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
1277     musicpal_gpio_write,
1278     musicpal_gpio_write,
1279     musicpal_gpio_write,
1280 };
1281
1282 static void musicpal_gpio_reset(DeviceState *d)
1283 {
1284     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1285                                          sysbus_from_qdev(d));
1286
1287     s->lcd_brightness = 0;
1288     s->out_state = 0;
1289     s->in_state = 0xffffffff;
1290     s->ier = 0;
1291     s->imr = 0;
1292     s->isr = 0;
1293 }
1294
1295 static int musicpal_gpio_init(SysBusDevice *dev)
1296 {
1297     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1298     int iomemtype;
1299
1300     sysbus_init_irq(dev, &s->irq);
1301
1302     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1303                                        musicpal_gpio_writefn, s,
1304                                        DEVICE_NATIVE_ENDIAN);
1305     sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1306
1307     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1308
1309     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1310
1311     return 0;
1312 }
1313
1314 static const VMStateDescription musicpal_gpio_vmsd = {
1315     .name = "musicpal_gpio",
1316     .version_id = 1,
1317     .minimum_version_id = 1,
1318     .minimum_version_id_old = 1,
1319     .fields = (VMStateField[]) {
1320         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1321         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1322         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1323         VMSTATE_UINT32(ier, musicpal_gpio_state),
1324         VMSTATE_UINT32(imr, musicpal_gpio_state),
1325         VMSTATE_UINT32(isr, musicpal_gpio_state),
1326         VMSTATE_END_OF_LIST()
1327     }
1328 };
1329
1330 static SysBusDeviceInfo musicpal_gpio_info = {
1331     .init = musicpal_gpio_init,
1332     .qdev.name  = "musicpal_gpio",
1333     .qdev.size  = sizeof(musicpal_gpio_state),
1334     .qdev.reset = musicpal_gpio_reset,
1335     .qdev.vmsd  = &musicpal_gpio_vmsd,
1336 };
1337
1338 /* Keyboard codes & masks */
1339 #define KEY_RELEASED            0x80
1340 #define KEY_CODE                0x7f
1341
1342 #define KEYCODE_TAB             0x0f
1343 #define KEYCODE_ENTER           0x1c
1344 #define KEYCODE_F               0x21
1345 #define KEYCODE_M               0x32
1346
1347 #define KEYCODE_EXTENDED        0xe0
1348 #define KEYCODE_UP              0x48
1349 #define KEYCODE_DOWN            0x50
1350 #define KEYCODE_LEFT            0x4b
1351 #define KEYCODE_RIGHT           0x4d
1352
1353 #define MP_KEY_WHEEL_VOL       (1 << 0)
1354 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1355 #define MP_KEY_WHEEL_NAV       (1 << 2)
1356 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1357 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1358 #define MP_KEY_BTN_MENU        (1 << 5)
1359 #define MP_KEY_BTN_VOLUME      (1 << 6)
1360 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1361
1362 typedef struct musicpal_key_state {
1363     SysBusDevice busdev;
1364     uint32_t kbd_extended;
1365     uint32_t pressed_keys;
1366     qemu_irq out[8];
1367 } musicpal_key_state;
1368
1369 static void musicpal_key_event(void *opaque, int keycode)
1370 {
1371     musicpal_key_state *s = opaque;
1372     uint32_t event = 0;
1373     int i;
1374
1375     if (keycode == KEYCODE_EXTENDED) {
1376         s->kbd_extended = 1;
1377         return;
1378     }
1379
1380     if (s->kbd_extended) {
1381         switch (keycode & KEY_CODE) {
1382         case KEYCODE_UP:
1383             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1384             break;
1385
1386         case KEYCODE_DOWN:
1387             event = MP_KEY_WHEEL_NAV;
1388             break;
1389
1390         case KEYCODE_LEFT:
1391             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1392             break;
1393
1394         case KEYCODE_RIGHT:
1395             event = MP_KEY_WHEEL_VOL;
1396             break;
1397         }
1398     } else {
1399         switch (keycode & KEY_CODE) {
1400         case KEYCODE_F:
1401             event = MP_KEY_BTN_FAVORITS;
1402             break;
1403
1404         case KEYCODE_TAB:
1405             event = MP_KEY_BTN_VOLUME;
1406             break;
1407
1408         case KEYCODE_ENTER:
1409             event = MP_KEY_BTN_NAVIGATION;
1410             break;
1411
1412         case KEYCODE_M:
1413             event = MP_KEY_BTN_MENU;
1414             break;
1415         }
1416         /* Do not repeat already pressed buttons */
1417         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1418             event = 0;
1419         }
1420     }
1421
1422     if (event) {
1423         /* Raise GPIO pin first if repeating a key */
1424         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1425             for (i = 0; i <= 7; i++) {
1426                 if (event & (1 << i)) {
1427                     qemu_set_irq(s->out[i], 1);
1428                 }
1429             }
1430         }
1431         for (i = 0; i <= 7; i++) {
1432             if (event & (1 << i)) {
1433                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1434             }
1435         }
1436         if (keycode & KEY_RELEASED) {
1437             s->pressed_keys &= ~event;
1438         } else {
1439             s->pressed_keys |= event;
1440         }
1441     }
1442
1443     s->kbd_extended = 0;
1444 }
1445
1446 static int musicpal_key_init(SysBusDevice *dev)
1447 {
1448     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1449
1450     sysbus_init_mmio(dev, 0x0, 0);
1451
1452     s->kbd_extended = 0;
1453     s->pressed_keys = 0;
1454
1455     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1456
1457     qemu_add_kbd_event_handler(musicpal_key_event, s);
1458
1459     return 0;
1460 }
1461
1462 static const VMStateDescription musicpal_key_vmsd = {
1463     .name = "musicpal_key",
1464     .version_id = 1,
1465     .minimum_version_id = 1,
1466     .minimum_version_id_old = 1,
1467     .fields = (VMStateField[]) {
1468         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1469         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1470         VMSTATE_END_OF_LIST()
1471     }
1472 };
1473
1474 static SysBusDeviceInfo musicpal_key_info = {
1475     .init = musicpal_key_init,
1476     .qdev.name  = "musicpal_key",
1477     .qdev.size  = sizeof(musicpal_key_state),
1478     .qdev.vmsd  = &musicpal_key_vmsd,
1479 };
1480
1481 static struct arm_boot_info musicpal_binfo = {
1482     .loader_start = 0x0,
1483     .board_id = 0x20e,
1484 };
1485
1486 static void musicpal_init(ram_addr_t ram_size,
1487                const char *boot_device,
1488                const char *kernel_filename, const char *kernel_cmdline,
1489                const char *initrd_filename, const char *cpu_model)
1490 {
1491     CPUState *env;
1492     qemu_irq *cpu_pic;
1493     qemu_irq pic[32];
1494     DeviceState *dev;
1495     DeviceState *i2c_dev;
1496     DeviceState *lcd_dev;
1497     DeviceState *key_dev;
1498     DeviceState *wm8750_dev;
1499     SysBusDevice *s;
1500     i2c_bus *i2c;
1501     int i;
1502     unsigned long flash_size;
1503     DriveInfo *dinfo;
1504     ram_addr_t sram_off;
1505
1506     if (!cpu_model) {
1507         cpu_model = "arm926";
1508     }
1509     env = cpu_init(cpu_model);
1510     if (!env) {
1511         fprintf(stderr, "Unable to find CPU definition\n");
1512         exit(1);
1513     }
1514     cpu_pic = arm_pic_init_cpu(env);
1515
1516     /* For now we use a fixed - the original - RAM size */
1517     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1518                                  qemu_ram_alloc(NULL, "musicpal.ram",
1519                                                 MP_RAM_DEFAULT_SIZE));
1520
1521     sram_off = qemu_ram_alloc(NULL, "musicpal.sram", MP_SRAM_SIZE);
1522     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1523
1524     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1525                                cpu_pic[ARM_PIC_CPU_IRQ]);
1526     for (i = 0; i < 32; i++) {
1527         pic[i] = qdev_get_gpio_in(dev, i);
1528     }
1529     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1530                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1531                           pic[MP_TIMER4_IRQ], NULL);
1532
1533     if (serial_hds[0]) {
1534 #ifdef TARGET_WORDS_BIGENDIAN
1535         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1536                        serial_hds[0], 1, 1);
1537 #else
1538         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1539                        serial_hds[0], 1, 0);
1540 #endif
1541     }
1542     if (serial_hds[1]) {
1543 #ifdef TARGET_WORDS_BIGENDIAN
1544         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1545                        serial_hds[1], 1, 1);
1546 #else
1547         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1548                        serial_hds[1], 1, 0);
1549 #endif
1550     }
1551
1552     /* Register flash */
1553     dinfo = drive_get(IF_PFLASH, 0, 0);
1554     if (dinfo) {
1555         flash_size = bdrv_getlength(dinfo->bdrv);
1556         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1557             flash_size != 32*1024*1024) {
1558             fprintf(stderr, "Invalid flash image size\n");
1559             exit(1);
1560         }
1561
1562         /*
1563          * The original U-Boot accesses the flash at 0xFE000000 instead of
1564          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1565          * image is smaller than 32 MB.
1566          */
1567 #ifdef TARGET_WORDS_BIGENDIAN
1568         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
1569                               "musicpal.flash", flash_size),
1570                               dinfo->bdrv, 0x10000,
1571                               (flash_size + 0xffff) >> 16,
1572                               MP_FLASH_SIZE_MAX / flash_size,
1573                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1574                               0x5555, 0x2AAA, 1);
1575 #else
1576         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
1577                               "musicpal.flash", flash_size),
1578                               dinfo->bdrv, 0x10000,
1579                               (flash_size + 0xffff) >> 16,
1580                               MP_FLASH_SIZE_MAX / flash_size,
1581                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1582                               0x5555, 0x2AAA, 0);
1583 #endif
1584
1585     }
1586     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1587
1588     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1589     dev = qdev_create(NULL, "mv88w8618_eth");
1590     qdev_set_nic_properties(dev, &nd_table[0]);
1591     qdev_init_nofail(dev);
1592     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1593     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1594
1595     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1596
1597     musicpal_misc_init();
1598
1599     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1600     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1601     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1602
1603     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1604     key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1605
1606     /* I2C read data */
1607     qdev_connect_gpio_out(i2c_dev, 0,
1608                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1609     /* I2C data */
1610     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1611     /* I2C clock */
1612     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1613
1614     for (i = 0; i < 3; i++) {
1615         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1616     }
1617     for (i = 0; i < 4; i++) {
1618         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1619     }
1620     for (i = 4; i < 8; i++) {
1621         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1622     }
1623
1624     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1625     dev = qdev_create(NULL, "mv88w8618_audio");
1626     s = sysbus_from_qdev(dev);
1627     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1628     qdev_init_nofail(dev);
1629     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1630     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1631
1632     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1633     musicpal_binfo.kernel_filename = kernel_filename;
1634     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1635     musicpal_binfo.initrd_filename = initrd_filename;
1636     arm_load_kernel(env, &musicpal_binfo);
1637 }
1638
1639 static QEMUMachine musicpal_machine = {
1640     .name = "musicpal",
1641     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1642     .init = musicpal_init,
1643 };
1644
1645 static void musicpal_machine_init(void)
1646 {
1647     qemu_register_machine(&musicpal_machine);
1648 }
1649
1650 machine_init(musicpal_machine_init);
1651
1652 static void musicpal_register_devices(void)
1653 {
1654     sysbus_register_withprop(&mv88w8618_pic_info);
1655     sysbus_register_withprop(&mv88w8618_pit_info);
1656     sysbus_register_withprop(&mv88w8618_flashcfg_info);
1657     sysbus_register_withprop(&mv88w8618_eth_info);
1658     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1659                         mv88w8618_wlan_init);
1660     sysbus_register_withprop(&musicpal_lcd_info);
1661     sysbus_register_withprop(&musicpal_gpio_info);
1662     sysbus_register_withprop(&musicpal_key_info);
1663 }
1664
1665 device_init(musicpal_register_devices)