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libqos/ahci: Add ahci_port_check_interrupts helper
[qemu/ar7.git] / target-i386 / kvm.c
blob40d6a14c854d6966269d3636a95f8f4e154fd278
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "qapi/qmp/qerror.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_bndcfgs;
77 static bool has_msr_kvm_steal_time;
78 static int lm_capable_kernel;
79 static bool has_msr_hv_hypercall;
80 static bool has_msr_hv_vapic;
81 static bool has_msr_hv_tsc;
82 static bool has_msr_mtrr;
83 static bool has_msr_xss;
84
85 static bool has_msr_architectural_pmu;
86 static uint32_t num_architectural_pmu_counters;
87
88 bool kvm_allows_irq0_override(void)
89 {
90 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
91 }
92
93 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
94 {
95 struct kvm_cpuid2 *cpuid;
96 int r, size;
97
98 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
99 cpuid = g_malloc0(size);
100 cpuid->nent = max;
101 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
102 if (r == 0 && cpuid->nent >= max) {
103 r = -E2BIG;
104 }
105 if (r < 0) {
106 if (r == -E2BIG) {
107 g_free(cpuid);
108 return NULL;
109 } else {
110 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
111 strerror(-r));
112 exit(1);
113 }
114 }
115 return cpuid;
116 }
117
118 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
119 * for all entries.
120 */
121 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
122 {
123 struct kvm_cpuid2 *cpuid;
124 int max = 1;
125 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
126 max *= 2;
127 }
128 return cpuid;
129 }
130
131 static const struct kvm_para_features {
132 int cap;
133 int feature;
134 } para_features[] = {
135 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
136 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
137 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
138 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
139 };
140
141 static int get_para_features(KVMState *s)
142 {
143 int i, features = 0;
144
145 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
146 if (kvm_check_extension(s, para_features[i].cap)) {
147 features |= (1 << para_features[i].feature);
148 }
149 }
150
151 return features;
152 }
153
154
155 /* Returns the value for a specific register on the cpuid entry
156 */
157 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
158 {
159 uint32_t ret = 0;
160 switch (reg) {
161 case R_EAX:
162 ret = entry->eax;
163 break;
164 case R_EBX:
165 ret = entry->ebx;
166 break;
167 case R_ECX:
168 ret = entry->ecx;
169 break;
170 case R_EDX:
171 ret = entry->edx;
172 break;
173 }
174 return ret;
175 }
176
177 /* Find matching entry for function/index on kvm_cpuid2 struct
178 */
179 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
180 uint32_t function,
181 uint32_t index)
182 {
183 int i;
184 for (i = 0; i < cpuid->nent; ++i) {
185 if (cpuid->entries[i].function == function &&
186 cpuid->entries[i].index == index) {
187 return &cpuid->entries[i];
188 }
189 }
190 /* not found: */
191 return NULL;
192 }
193
194 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
195 uint32_t index, int reg)
196 {
197 struct kvm_cpuid2 *cpuid;
198 uint32_t ret = 0;
199 uint32_t cpuid_1_edx;
200 bool found = false;
201
202 cpuid = get_supported_cpuid(s);
203
204 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
205 if (entry) {
206 found = true;
207 ret = cpuid_entry_get_reg(entry, reg);
208 }
209
210 /* Fixups for the data returned by KVM, below */
211
212 if (function == 1 && reg == R_EDX) {
213 /* KVM before 2.6.30 misreports the following features */
214 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
215 } else if (function == 1 && reg == R_ECX) {
216 /* We can set the hypervisor flag, even if KVM does not return it on
217 * GET_SUPPORTED_CPUID
218 */
219 ret |= CPUID_EXT_HYPERVISOR;
220 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
221 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
222 * and the irqchip is in the kernel.
223 */
224 if (kvm_irqchip_in_kernel() &&
225 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
226 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
227 }
228
229 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
230 * without the in-kernel irqchip
231 */
232 if (!kvm_irqchip_in_kernel()) {
233 ret &= ~CPUID_EXT_X2APIC;
234 }
235 } else if (function == 0x80000001 && reg == R_EDX) {
236 /* On Intel, kvm returns cpuid according to the Intel spec,
237 * so add missing bits according to the AMD spec:
238 */
239 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
240 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
241 }
242
243 g_free(cpuid);
244
245 /* fallback for older kernels */
246 if ((function == KVM_CPUID_FEATURES) && !found) {
247 ret = get_para_features(s);
248 }
249
250 return ret;
251 }
252
253 typedef struct HWPoisonPage {
254 ram_addr_t ram_addr;
255 QLIST_ENTRY(HWPoisonPage) list;
256 } HWPoisonPage;
257
258 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
259 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
260
261 static void kvm_unpoison_all(void *param)
262 {
263 HWPoisonPage *page, *next_page;
264
265 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
266 QLIST_REMOVE(page, list);
267 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
268 g_free(page);
269 }
270 }
271
272 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
273 {
274 HWPoisonPage *page;
275
276 QLIST_FOREACH(page, &hwpoison_page_list, list) {
277 if (page->ram_addr == ram_addr) {
278 return;
279 }
280 }
281 page = g_new(HWPoisonPage, 1);
282 page->ram_addr = ram_addr;
283 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
284 }
285
286 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
287 int *max_banks)
288 {
289 int r;
290
291 r = kvm_check_extension(s, KVM_CAP_MCE);
292 if (r > 0) {
293 *max_banks = r;
294 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
295 }
296 return -ENOSYS;
297 }
298
299 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
300 {
301 CPUX86State *env = &cpu->env;
302 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
303 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
304 uint64_t mcg_status = MCG_STATUS_MCIP;
305
306 if (code == BUS_MCEERR_AR) {
307 status |= MCI_STATUS_AR | 0x134;
308 mcg_status |= MCG_STATUS_EIPV;
309 } else {
310 status |= 0xc0;
311 mcg_status |= MCG_STATUS_RIPV;
312 }
313 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
314 (MCM_ADDR_PHYS << 6) | 0xc,
315 cpu_x86_support_mca_broadcast(env) ?
316 MCE_INJECT_BROADCAST : 0);
317 }
318
319 static void hardware_memory_error(void)
320 {
321 fprintf(stderr, "Hardware memory error!\n");
322 exit(1);
323 }
324
325 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
326 {
327 X86CPU *cpu = X86_CPU(c);
328 CPUX86State *env = &cpu->env;
329 ram_addr_t ram_addr;
330 hwaddr paddr;
331
332 if ((env->mcg_cap & MCG_SER_P) && addr
333 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
334 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
335 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
336 fprintf(stderr, "Hardware memory error for memory used by "
337 "QEMU itself instead of guest system!\n");
338 /* Hope we are lucky for AO MCE */
339 if (code == BUS_MCEERR_AO) {
340 return 0;
341 } else {
342 hardware_memory_error();
343 }
344 }
345 kvm_hwpoison_page_add(ram_addr);
346 kvm_mce_inject(cpu, paddr, code);
347 } else {
348 if (code == BUS_MCEERR_AO) {
349 return 0;
350 } else if (code == BUS_MCEERR_AR) {
351 hardware_memory_error();
352 } else {
353 return 1;
354 }
355 }
356 return 0;
357 }
358
359 int kvm_arch_on_sigbus(int code, void *addr)
360 {
361 X86CPU *cpu = X86_CPU(first_cpu);
362
363 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
364 ram_addr_t ram_addr;
365 hwaddr paddr;
366
367 /* Hope we are lucky for AO MCE */
368 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
369 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
370 addr, &paddr)) {
371 fprintf(stderr, "Hardware memory error for memory used by "
372 "QEMU itself instead of guest system!: %p\n", addr);
373 return 0;
374 }
375 kvm_hwpoison_page_add(ram_addr);
376 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
377 } else {
378 if (code == BUS_MCEERR_AO) {
379 return 0;
380 } else if (code == BUS_MCEERR_AR) {
381 hardware_memory_error();
382 } else {
383 return 1;
384 }
385 }
386 return 0;
387 }
388
389 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
390 {
391 CPUX86State *env = &cpu->env;
392
393 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
394 unsigned int bank, bank_num = env->mcg_cap & 0xff;
395 struct kvm_x86_mce mce;
396
397 env->exception_injected = -1;
398
399 /*
400 * There must be at least one bank in use if an MCE is pending.
401 * Find it and use its values for the event injection.
402 */
403 for (bank = 0; bank < bank_num; bank++) {
404 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
405 break;
406 }
407 }
408 assert(bank < bank_num);
409
410 mce.bank = bank;
411 mce.status = env->mce_banks[bank * 4 + 1];
412 mce.mcg_status = env->mcg_status;
413 mce.addr = env->mce_banks[bank * 4 + 2];
414 mce.misc = env->mce_banks[bank * 4 + 3];
415
416 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
417 }
418 return 0;
419 }
420
421 static void cpu_update_state(void *opaque, int running, RunState state)
422 {
423 CPUX86State *env = opaque;
424
425 if (running) {
426 env->tsc_valid = false;
427 }
428 }
429
430 unsigned long kvm_arch_vcpu_id(CPUState *cs)
431 {
432 X86CPU *cpu = X86_CPU(cs);
433 return cpu->env.cpuid_apic_id;
434 }
435
436 #ifndef KVM_CPUID_SIGNATURE_NEXT
437 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
438 #endif
439
440 static bool hyperv_hypercall_available(X86CPU *cpu)
441 {
442 return cpu->hyperv_vapic ||
443 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
444 }
445
446 static bool hyperv_enabled(X86CPU *cpu)
447 {
448 CPUState *cs = CPU(cpu);
449 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
450 (hyperv_hypercall_available(cpu) ||
451 cpu->hyperv_time ||
452 cpu->hyperv_relaxed_timing);
453 }
454
455 static Error *invtsc_mig_blocker;
456
457 #define KVM_MAX_CPUID_ENTRIES 100
458
459 int kvm_arch_init_vcpu(CPUState *cs)
460 {
461 struct {
462 struct kvm_cpuid2 cpuid;
463 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
464 } QEMU_PACKED cpuid_data;
465 X86CPU *cpu = X86_CPU(cs);
466 CPUX86State *env = &cpu->env;
467 uint32_t limit, i, j, cpuid_i;
468 uint32_t unused;
469 struct kvm_cpuid_entry2 *c;
470 uint32_t signature[3];
471 int kvm_base = KVM_CPUID_SIGNATURE;
472 int r;
473
474 memset(&cpuid_data, 0, sizeof(cpuid_data));
475
476 cpuid_i = 0;
477
478 /* Paravirtualization CPUIDs */
479 if (hyperv_enabled(cpu)) {
480 c = &cpuid_data.entries[cpuid_i++];
481 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
482 memcpy(signature, "Microsoft Hv", 12);
483 c->eax = HYPERV_CPUID_MIN;
484 c->ebx = signature[0];
485 c->ecx = signature[1];
486 c->edx = signature[2];
487
488 c = &cpuid_data.entries[cpuid_i++];
489 c->function = HYPERV_CPUID_INTERFACE;
490 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
491 c->eax = signature[0];
492 c->ebx = 0;
493 c->ecx = 0;
494 c->edx = 0;
495
496 c = &cpuid_data.entries[cpuid_i++];
497 c->function = HYPERV_CPUID_VERSION;
498 c->eax = 0x00001bbc;
499 c->ebx = 0x00060001;
500
501 c = &cpuid_data.entries[cpuid_i++];
502 c->function = HYPERV_CPUID_FEATURES;
503 if (cpu->hyperv_relaxed_timing) {
504 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
505 }
506 if (cpu->hyperv_vapic) {
507 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
508 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
509 has_msr_hv_vapic = true;
510 }
511 if (cpu->hyperv_time &&
512 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
513 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
514 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
515 c->eax |= 0x200;
516 has_msr_hv_tsc = true;
517 }
518 c = &cpuid_data.entries[cpuid_i++];
519 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
520 if (cpu->hyperv_relaxed_timing) {
521 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
522 }
523 if (has_msr_hv_vapic) {
524 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
525 }
526 c->ebx = cpu->hyperv_spinlock_attempts;
527
528 c = &cpuid_data.entries[cpuid_i++];
529 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
530 c->eax = 0x40;
531 c->ebx = 0x40;
532
533 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
534 has_msr_hv_hypercall = true;
535 }
536
537 if (cpu->expose_kvm) {
538 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
539 c = &cpuid_data.entries[cpuid_i++];
540 c->function = KVM_CPUID_SIGNATURE | kvm_base;
541 c->eax = KVM_CPUID_FEATURES | kvm_base;
542 c->ebx = signature[0];
543 c->ecx = signature[1];
544 c->edx = signature[2];
545
546 c = &cpuid_data.entries[cpuid_i++];
547 c->function = KVM_CPUID_FEATURES | kvm_base;
548 c->eax = env->features[FEAT_KVM];
549
550 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
551
552 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
553
554 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
555 }
556
557 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
558
559 for (i = 0; i <= limit; i++) {
560 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
561 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
562 abort();
563 }
564 c = &cpuid_data.entries[cpuid_i++];
565
566 switch (i) {
567 case 2: {
568 /* Keep reading function 2 till all the input is received */
569 int times;
570
571 c->function = i;
572 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
573 KVM_CPUID_FLAG_STATE_READ_NEXT;
574 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
575 times = c->eax & 0xff;
576
577 for (j = 1; j < times; ++j) {
578 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
579 fprintf(stderr, "cpuid_data is full, no space for "
580 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
581 abort();
582 }
583 c = &cpuid_data.entries[cpuid_i++];
584 c->function = i;
585 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
586 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
587 }
588 break;
589 }
590 case 4:
591 case 0xb:
592 case 0xd:
593 for (j = 0; ; j++) {
594 if (i == 0xd && j == 64) {
595 break;
596 }
597 c->function = i;
598 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
599 c->index = j;
600 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
601
602 if (i == 4 && c->eax == 0) {
603 break;
604 }
605 if (i == 0xb && !(c->ecx & 0xff00)) {
606 break;
607 }
608 if (i == 0xd && c->eax == 0) {
609 continue;
610 }
611 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
612 fprintf(stderr, "cpuid_data is full, no space for "
613 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
614 abort();
615 }
616 c = &cpuid_data.entries[cpuid_i++];
617 }
618 break;
619 default:
620 c->function = i;
621 c->flags = 0;
622 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
623 break;
624 }
625 }
626
627 if (limit >= 0x0a) {
628 uint32_t ver;
629
630 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
631 if ((ver & 0xff) > 0) {
632 has_msr_architectural_pmu = true;
633 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
634
635 /* Shouldn't be more than 32, since that's the number of bits
636 * available in EBX to tell us _which_ counters are available.
637 * Play it safe.
638 */
639 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
640 num_architectural_pmu_counters = MAX_GP_COUNTERS;
641 }
642 }
643 }
644
645 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
646
647 for (i = 0x80000000; i <= limit; i++) {
648 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
649 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
650 abort();
651 }
652 c = &cpuid_data.entries[cpuid_i++];
653
654 c->function = i;
655 c->flags = 0;
656 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
657 }
658
659 /* Call Centaur's CPUID instructions they are supported. */
660 if (env->cpuid_xlevel2 > 0) {
661 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
662
663 for (i = 0xC0000000; i <= limit; i++) {
664 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
665 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
666 abort();
667 }
668 c = &cpuid_data.entries[cpuid_i++];
669
670 c->function = i;
671 c->flags = 0;
672 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
673 }
674 }
675
676 cpuid_data.cpuid.nent = cpuid_i;
677
678 if (((env->cpuid_version >> 8)&0xF) >= 6
679 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
680 (CPUID_MCE | CPUID_MCA)
681 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
682 uint64_t mcg_cap;
683 int banks;
684 int ret;
685
686 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
687 if (ret < 0) {
688 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
689 return ret;
690 }
691
692 if (banks > MCE_BANKS_DEF) {
693 banks = MCE_BANKS_DEF;
694 }
695 mcg_cap &= MCE_CAP_DEF;
696 mcg_cap |= banks;
697 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
698 if (ret < 0) {
699 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
700 return ret;
701 }
702
703 env->mcg_cap = mcg_cap;
704 }
705
706 qemu_add_vm_change_state_handler(cpu_update_state, env);
707
708 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
709 if (c) {
710 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
711 !!(c->ecx & CPUID_EXT_SMX);
712 }
713
714 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
715 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
716 /* for migration */
717 error_setg(&invtsc_mig_blocker,
718 "State blocked by non-migratable CPU device"
719 " (invtsc flag)");
720 migrate_add_blocker(invtsc_mig_blocker);
721 /* for savevm */
722 vmstate_x86_cpu.unmigratable = 1;
723 }
724
725 cpuid_data.cpuid.padding = 0;
726 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
727 if (r) {
728 return r;
729 }
730
731 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
732 if (r && env->tsc_khz) {
733 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
734 if (r < 0) {
735 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
736 return r;
737 }
738 }
739
740 if (kvm_has_xsave()) {
741 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
742 }
743
744 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
745 has_msr_mtrr = true;
746 }
747
748 return 0;
749 }
750
751 void kvm_arch_reset_vcpu(X86CPU *cpu)
752 {
753 CPUX86State *env = &cpu->env;
754
755 env->exception_injected = -1;
756 env->interrupt_injected = -1;
757 env->xcr0 = 1;
758 if (kvm_irqchip_in_kernel()) {
759 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
760 KVM_MP_STATE_UNINITIALIZED;
761 } else {
762 env->mp_state = KVM_MP_STATE_RUNNABLE;
763 }
764 }
765
766 void kvm_arch_do_init_vcpu(X86CPU *cpu)
767 {
768 CPUX86State *env = &cpu->env;
769
770 /* APs get directly into wait-for-SIPI state. */
771 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
772 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
773 }
774 }
775
776 static int kvm_get_supported_msrs(KVMState *s)
777 {
778 static int kvm_supported_msrs;
779 int ret = 0;
780
781 /* first time */
782 if (kvm_supported_msrs == 0) {
783 struct kvm_msr_list msr_list, *kvm_msr_list;
784
785 kvm_supported_msrs = -1;
786
787 /* Obtain MSR list from KVM. These are the MSRs that we must
788 * save/restore */
789 msr_list.nmsrs = 0;
790 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
791 if (ret < 0 && ret != -E2BIG) {
792 return ret;
793 }
794 /* Old kernel modules had a bug and could write beyond the provided
795 memory. Allocate at least a safe amount of 1K. */
796 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
797 msr_list.nmsrs *
798 sizeof(msr_list.indices[0])));
799
800 kvm_msr_list->nmsrs = msr_list.nmsrs;
801 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
802 if (ret >= 0) {
803 int i;
804
805 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
806 if (kvm_msr_list->indices[i] == MSR_STAR) {
807 has_msr_star = true;
808 continue;
809 }
810 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
811 has_msr_hsave_pa = true;
812 continue;
813 }
814 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
815 has_msr_tsc_adjust = true;
816 continue;
817 }
818 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
819 has_msr_tsc_deadline = true;
820 continue;
821 }
822 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
823 has_msr_misc_enable = true;
824 continue;
825 }
826 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
827 has_msr_bndcfgs = true;
828 continue;
829 }
830 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
831 has_msr_xss = true;
832 continue;
833 }
834 }
835 }
836
837 g_free(kvm_msr_list);
838 }
839
840 return ret;
841 }
842
843 int kvm_arch_init(KVMState *s)
844 {
845 uint64_t identity_base = 0xfffbc000;
846 uint64_t shadow_mem;
847 int ret;
848 struct utsname utsname;
849
850 ret = kvm_get_supported_msrs(s);
851 if (ret < 0) {
852 return ret;
853 }
854
855 uname(&utsname);
856 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
857
858 /*
859 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
860 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
861 * Since these must be part of guest physical memory, we need to allocate
862 * them, both by setting their start addresses in the kernel and by
863 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
864 *
865 * Older KVM versions may not support setting the identity map base. In
866 * that case we need to stick with the default, i.e. a 256K maximum BIOS
867 * size.
868 */
869 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
870 /* Allows up to 16M BIOSes. */
871 identity_base = 0xfeffc000;
872
873 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
874 if (ret < 0) {
875 return ret;
876 }
877 }
878
879 /* Set TSS base one page after EPT identity map. */
880 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
881 if (ret < 0) {
882 return ret;
883 }
884
885 /* Tell fw_cfg to notify the BIOS to reserve the range. */
886 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
887 if (ret < 0) {
888 fprintf(stderr, "e820_add_entry() table is full\n");
889 return ret;
890 }
891 qemu_register_reset(kvm_unpoison_all, NULL);
892
893 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
894 "kvm_shadow_mem", -1);
895 if (shadow_mem != -1) {
896 shadow_mem /= 4096;
897 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
898 if (ret < 0) {
899 return ret;
900 }
901 }
902 return 0;
903 }
904
905 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
906 {
907 lhs->selector = rhs->selector;
908 lhs->base = rhs->base;
909 lhs->limit = rhs->limit;
910 lhs->type = 3;
911 lhs->present = 1;
912 lhs->dpl = 3;
913 lhs->db = 0;
914 lhs->s = 1;
915 lhs->l = 0;
916 lhs->g = 0;
917 lhs->avl = 0;
918 lhs->unusable = 0;
919 }
920
921 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
922 {
923 unsigned flags = rhs->flags;
924 lhs->selector = rhs->selector;
925 lhs->base = rhs->base;
926 lhs->limit = rhs->limit;
927 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
928 lhs->present = (flags & DESC_P_MASK) != 0;
929 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
930 lhs->db = (flags >> DESC_B_SHIFT) & 1;
931 lhs->s = (flags & DESC_S_MASK) != 0;
932 lhs->l = (flags >> DESC_L_SHIFT) & 1;
933 lhs->g = (flags & DESC_G_MASK) != 0;
934 lhs->avl = (flags & DESC_AVL_MASK) != 0;
935 lhs->unusable = 0;
936 lhs->padding = 0;
937 }
938
939 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
940 {
941 lhs->selector = rhs->selector;
942 lhs->base = rhs->base;
943 lhs->limit = rhs->limit;
944 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
945 (rhs->present * DESC_P_MASK) |
946 (rhs->dpl << DESC_DPL_SHIFT) |
947 (rhs->db << DESC_B_SHIFT) |
948 (rhs->s * DESC_S_MASK) |
949 (rhs->l << DESC_L_SHIFT) |
950 (rhs->g * DESC_G_MASK) |
951 (rhs->avl * DESC_AVL_MASK);
952 }
953
954 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
955 {
956 if (set) {
957 *kvm_reg = *qemu_reg;
958 } else {
959 *qemu_reg = *kvm_reg;
960 }
961 }
962
963 static int kvm_getput_regs(X86CPU *cpu, int set)
964 {
965 CPUX86State *env = &cpu->env;
966 struct kvm_regs regs;
967 int ret = 0;
968
969 if (!set) {
970 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
971 if (ret < 0) {
972 return ret;
973 }
974 }
975
976 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
977 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
978 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
979 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
980 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
981 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
982 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
983 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
984 #ifdef TARGET_X86_64
985 kvm_getput_reg(&regs.r8, &env->regs[8], set);
986 kvm_getput_reg(&regs.r9, &env->regs[9], set);
987 kvm_getput_reg(&regs.r10, &env->regs[10], set);
988 kvm_getput_reg(&regs.r11, &env->regs[11], set);
989 kvm_getput_reg(&regs.r12, &env->regs[12], set);
990 kvm_getput_reg(&regs.r13, &env->regs[13], set);
991 kvm_getput_reg(&regs.r14, &env->regs[14], set);
992 kvm_getput_reg(&regs.r15, &env->regs[15], set);
993 #endif
994
995 kvm_getput_reg(&regs.rflags, &env->eflags, set);
996 kvm_getput_reg(&regs.rip, &env->eip, set);
997
998 if (set) {
999 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1000 }
1001
1002 return ret;
1003 }
1004
1005 static int kvm_put_fpu(X86CPU *cpu)
1006 {
1007 CPUX86State *env = &cpu->env;
1008 struct kvm_fpu fpu;
1009 int i;
1010
1011 memset(&fpu, 0, sizeof fpu);
1012 fpu.fsw = env->fpus & ~(7 << 11);
1013 fpu.fsw |= (env->fpstt & 7) << 11;
1014 fpu.fcw = env->fpuc;
1015 fpu.last_opcode = env->fpop;
1016 fpu.last_ip = env->fpip;
1017 fpu.last_dp = env->fpdp;
1018 for (i = 0; i < 8; ++i) {
1019 fpu.ftwx |= (!env->fptags[i]) << i;
1020 }
1021 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1022 for (i = 0; i < CPU_NB_REGS; i++) {
1023 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1024 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1025 }
1026 fpu.mxcsr = env->mxcsr;
1027
1028 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1029 }
1030
1031 #define XSAVE_FCW_FSW 0
1032 #define XSAVE_FTW_FOP 1
1033 #define XSAVE_CWD_RIP 2
1034 #define XSAVE_CWD_RDP 4
1035 #define XSAVE_MXCSR 6
1036 #define XSAVE_ST_SPACE 8
1037 #define XSAVE_XMM_SPACE 40
1038 #define XSAVE_XSTATE_BV 128
1039 #define XSAVE_YMMH_SPACE 144
1040 #define XSAVE_BNDREGS 240
1041 #define XSAVE_BNDCSR 256
1042 #define XSAVE_OPMASK 272
1043 #define XSAVE_ZMM_Hi256 288
1044 #define XSAVE_Hi16_ZMM 416
1045
1046 static int kvm_put_xsave(X86CPU *cpu)
1047 {
1048 CPUX86State *env = &cpu->env;
1049 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1050 uint16_t cwd, swd, twd;
1051 uint8_t *xmm, *ymmh, *zmmh;
1052 int i, r;
1053
1054 if (!kvm_has_xsave()) {
1055 return kvm_put_fpu(cpu);
1056 }
1057
1058 memset(xsave, 0, sizeof(struct kvm_xsave));
1059 twd = 0;
1060 swd = env->fpus & ~(7 << 11);
1061 swd |= (env->fpstt & 7) << 11;
1062 cwd = env->fpuc;
1063 for (i = 0; i < 8; ++i) {
1064 twd |= (!env->fptags[i]) << i;
1065 }
1066 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1067 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1068 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1069 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1070 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1071 sizeof env->fpregs);
1072 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1073 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1074 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1075 sizeof env->bnd_regs);
1076 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1077 sizeof(env->bndcs_regs));
1078 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1079 sizeof env->opmask_regs);
1080
1081 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1082 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1083 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1084 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1085 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1086 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1087 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1088 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1089 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1090 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1091 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1092 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1093 }
1094
1095 #ifdef TARGET_X86_64
1096 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1097 16 * sizeof env->xmm_regs[16]);
1098 #endif
1099 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1100 return r;
1101 }
1102
1103 static int kvm_put_xcrs(X86CPU *cpu)
1104 {
1105 CPUX86State *env = &cpu->env;
1106 struct kvm_xcrs xcrs = {};
1107
1108 if (!kvm_has_xcrs()) {
1109 return 0;
1110 }
1111
1112 xcrs.nr_xcrs = 1;
1113 xcrs.flags = 0;
1114 xcrs.xcrs[0].xcr = 0;
1115 xcrs.xcrs[0].value = env->xcr0;
1116 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1117 }
1118
1119 static int kvm_put_sregs(X86CPU *cpu)
1120 {
1121 CPUX86State *env = &cpu->env;
1122 struct kvm_sregs sregs;
1123
1124 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1125 if (env->interrupt_injected >= 0) {
1126 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1127 (uint64_t)1 << (env->interrupt_injected % 64);
1128 }
1129
1130 if ((env->eflags & VM_MASK)) {
1131 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1132 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1133 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1134 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1135 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1136 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1137 } else {
1138 set_seg(&sregs.cs, &env->segs[R_CS]);
1139 set_seg(&sregs.ds, &env->segs[R_DS]);
1140 set_seg(&sregs.es, &env->segs[R_ES]);
1141 set_seg(&sregs.fs, &env->segs[R_FS]);
1142 set_seg(&sregs.gs, &env->segs[R_GS]);
1143 set_seg(&sregs.ss, &env->segs[R_SS]);
1144 }
1145
1146 set_seg(&sregs.tr, &env->tr);
1147 set_seg(&sregs.ldt, &env->ldt);
1148
1149 sregs.idt.limit = env->idt.limit;
1150 sregs.idt.base = env->idt.base;
1151 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1152 sregs.gdt.limit = env->gdt.limit;
1153 sregs.gdt.base = env->gdt.base;
1154 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1155
1156 sregs.cr0 = env->cr[0];
1157 sregs.cr2 = env->cr[2];
1158 sregs.cr3 = env->cr[3];
1159 sregs.cr4 = env->cr[4];
1160
1161 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1162 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1163
1164 sregs.efer = env->efer;
1165
1166 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1167 }
1168
1169 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1170 uint32_t index, uint64_t value)
1171 {
1172 entry->index = index;
1173 entry->reserved = 0;
1174 entry->data = value;
1175 }
1176
1177 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1178 {
1179 CPUX86State *env = &cpu->env;
1180 struct {
1181 struct kvm_msrs info;
1182 struct kvm_msr_entry entries[1];
1183 } msr_data;
1184 struct kvm_msr_entry *msrs = msr_data.entries;
1185
1186 if (!has_msr_tsc_deadline) {
1187 return 0;
1188 }
1189
1190 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1191
1192 msr_data.info = (struct kvm_msrs) {
1193 .nmsrs = 1,
1194 };
1195
1196 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1197 }
1198
1199 /*
1200 * Provide a separate write service for the feature control MSR in order to
1201 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1202 * before writing any other state because forcibly leaving nested mode
1203 * invalidates the VCPU state.
1204 */
1205 static int kvm_put_msr_feature_control(X86CPU *cpu)
1206 {
1207 struct {
1208 struct kvm_msrs info;
1209 struct kvm_msr_entry entry;
1210 } msr_data;
1211
1212 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1213 cpu->env.msr_ia32_feature_control);
1214
1215 msr_data.info = (struct kvm_msrs) {
1216 .nmsrs = 1,
1217 };
1218
1219 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1220 }
1221
1222 static int kvm_put_msrs(X86CPU *cpu, int level)
1223 {
1224 CPUX86State *env = &cpu->env;
1225 struct {
1226 struct kvm_msrs info;
1227 struct kvm_msr_entry entries[150];
1228 } msr_data;
1229 struct kvm_msr_entry *msrs = msr_data.entries;
1230 int n = 0, i;
1231
1232 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1233 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1234 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1235 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1236 if (has_msr_star) {
1237 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1238 }
1239 if (has_msr_hsave_pa) {
1240 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1241 }
1242 if (has_msr_tsc_adjust) {
1243 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1244 }
1245 if (has_msr_misc_enable) {
1246 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1247 env->msr_ia32_misc_enable);
1248 }
1249 if (has_msr_bndcfgs) {
1250 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1251 }
1252 if (has_msr_xss) {
1253 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1254 }
1255 #ifdef TARGET_X86_64
1256 if (lm_capable_kernel) {
1257 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1258 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1259 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1260 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1261 }
1262 #endif
1263 /*
1264 * The following MSRs have side effects on the guest or are too heavy
1265 * for normal writeback. Limit them to reset or full state updates.
1266 */
1267 if (level >= KVM_PUT_RESET_STATE) {
1268 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1269 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1270 env->system_time_msr);
1271 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1272 if (has_msr_async_pf_en) {
1273 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1274 env->async_pf_en_msr);
1275 }
1276 if (has_msr_pv_eoi_en) {
1277 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1278 env->pv_eoi_en_msr);
1279 }
1280 if (has_msr_kvm_steal_time) {
1281 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1282 env->steal_time_msr);
1283 }
1284 if (has_msr_architectural_pmu) {
1285 /* Stop the counter. */
1286 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1287 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1288
1289 /* Set the counter values. */
1290 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1291 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1292 env->msr_fixed_counters[i]);
1293 }
1294 for (i = 0; i < num_architectural_pmu_counters; i++) {
1295 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1296 env->msr_gp_counters[i]);
1297 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1298 env->msr_gp_evtsel[i]);
1299 }
1300 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1301 env->msr_global_status);
1302 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1303 env->msr_global_ovf_ctrl);
1304
1305 /* Now start the PMU. */
1306 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1307 env->msr_fixed_ctr_ctrl);
1308 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1309 env->msr_global_ctrl);
1310 }
1311 if (has_msr_hv_hypercall) {
1312 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1313 env->msr_hv_guest_os_id);
1314 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1315 env->msr_hv_hypercall);
1316 }
1317 if (has_msr_hv_vapic) {
1318 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1319 env->msr_hv_vapic);
1320 }
1321 if (has_msr_hv_tsc) {
1322 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1323 env->msr_hv_tsc);
1324 }
1325 if (has_msr_mtrr) {
1326 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1327 kvm_msr_entry_set(&msrs[n++],
1328 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1329 kvm_msr_entry_set(&msrs[n++],
1330 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1331 kvm_msr_entry_set(&msrs[n++],
1332 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1333 kvm_msr_entry_set(&msrs[n++],
1334 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1335 kvm_msr_entry_set(&msrs[n++],
1336 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1337 kvm_msr_entry_set(&msrs[n++],
1338 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1339 kvm_msr_entry_set(&msrs[n++],
1340 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1341 kvm_msr_entry_set(&msrs[n++],
1342 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1343 kvm_msr_entry_set(&msrs[n++],
1344 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1345 kvm_msr_entry_set(&msrs[n++],
1346 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1347 kvm_msr_entry_set(&msrs[n++],
1348 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1349 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1350 kvm_msr_entry_set(&msrs[n++],
1351 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1352 kvm_msr_entry_set(&msrs[n++],
1353 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1354 }
1355 }
1356
1357 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1358 * kvm_put_msr_feature_control. */
1359 }
1360 if (env->mcg_cap) {
1361 int i;
1362
1363 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1364 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1365 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1366 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1367 }
1368 }
1369
1370 msr_data.info = (struct kvm_msrs) {
1371 .nmsrs = n,
1372 };
1373
1374 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1375
1376 }
1377
1378
1379 static int kvm_get_fpu(X86CPU *cpu)
1380 {
1381 CPUX86State *env = &cpu->env;
1382 struct kvm_fpu fpu;
1383 int i, ret;
1384
1385 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1386 if (ret < 0) {
1387 return ret;
1388 }
1389
1390 env->fpstt = (fpu.fsw >> 11) & 7;
1391 env->fpus = fpu.fsw;
1392 env->fpuc = fpu.fcw;
1393 env->fpop = fpu.last_opcode;
1394 env->fpip = fpu.last_ip;
1395 env->fpdp = fpu.last_dp;
1396 for (i = 0; i < 8; ++i) {
1397 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1398 }
1399 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1400 for (i = 0; i < CPU_NB_REGS; i++) {
1401 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1402 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1403 }
1404 env->mxcsr = fpu.mxcsr;
1405
1406 return 0;
1407 }
1408
1409 static int kvm_get_xsave(X86CPU *cpu)
1410 {
1411 CPUX86State *env = &cpu->env;
1412 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1413 int ret, i;
1414 const uint8_t *xmm, *ymmh, *zmmh;
1415 uint16_t cwd, swd, twd;
1416
1417 if (!kvm_has_xsave()) {
1418 return kvm_get_fpu(cpu);
1419 }
1420
1421 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1422 if (ret < 0) {
1423 return ret;
1424 }
1425
1426 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1427 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1428 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1429 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1430 env->fpstt = (swd >> 11) & 7;
1431 env->fpus = swd;
1432 env->fpuc = cwd;
1433 for (i = 0; i < 8; ++i) {
1434 env->fptags[i] = !((twd >> i) & 1);
1435 }
1436 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1437 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1438 env->mxcsr = xsave->region[XSAVE_MXCSR];
1439 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1440 sizeof env->fpregs);
1441 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1442 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1443 sizeof env->bnd_regs);
1444 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1445 sizeof(env->bndcs_regs));
1446 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1447 sizeof env->opmask_regs);
1448
1449 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1450 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1451 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1452 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1453 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1454 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1455 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1456 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1457 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1458 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1459 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1460 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1461 }
1462
1463 #ifdef TARGET_X86_64
1464 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1465 16 * sizeof env->xmm_regs[16]);
1466 #endif
1467 return 0;
1468 }
1469
1470 static int kvm_get_xcrs(X86CPU *cpu)
1471 {
1472 CPUX86State *env = &cpu->env;
1473 int i, ret;
1474 struct kvm_xcrs xcrs;
1475
1476 if (!kvm_has_xcrs()) {
1477 return 0;
1478 }
1479
1480 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1481 if (ret < 0) {
1482 return ret;
1483 }
1484
1485 for (i = 0; i < xcrs.nr_xcrs; i++) {
1486 /* Only support xcr0 now */
1487 if (xcrs.xcrs[i].xcr == 0) {
1488 env->xcr0 = xcrs.xcrs[i].value;
1489 break;
1490 }
1491 }
1492 return 0;
1493 }
1494
1495 static int kvm_get_sregs(X86CPU *cpu)
1496 {
1497 CPUX86State *env = &cpu->env;
1498 struct kvm_sregs sregs;
1499 uint32_t hflags;
1500 int bit, i, ret;
1501
1502 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1503 if (ret < 0) {
1504 return ret;
1505 }
1506
1507 /* There can only be one pending IRQ set in the bitmap at a time, so try
1508 to find it and save its number instead (-1 for none). */
1509 env->interrupt_injected = -1;
1510 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1511 if (sregs.interrupt_bitmap[i]) {
1512 bit = ctz64(sregs.interrupt_bitmap[i]);
1513 env->interrupt_injected = i * 64 + bit;
1514 break;
1515 }
1516 }
1517
1518 get_seg(&env->segs[R_CS], &sregs.cs);
1519 get_seg(&env->segs[R_DS], &sregs.ds);
1520 get_seg(&env->segs[R_ES], &sregs.es);
1521 get_seg(&env->segs[R_FS], &sregs.fs);
1522 get_seg(&env->segs[R_GS], &sregs.gs);
1523 get_seg(&env->segs[R_SS], &sregs.ss);
1524
1525 get_seg(&env->tr, &sregs.tr);
1526 get_seg(&env->ldt, &sregs.ldt);
1527
1528 env->idt.limit = sregs.idt.limit;
1529 env->idt.base = sregs.idt.base;
1530 env->gdt.limit = sregs.gdt.limit;
1531 env->gdt.base = sregs.gdt.base;
1532
1533 env->cr[0] = sregs.cr0;
1534 env->cr[2] = sregs.cr2;
1535 env->cr[3] = sregs.cr3;
1536 env->cr[4] = sregs.cr4;
1537
1538 env->efer = sregs.efer;
1539
1540 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1541
1542 #define HFLAG_COPY_MASK \
1543 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1544 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1545 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1546 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1547
1548 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1549 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1550 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1551 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1552 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1553 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1554 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1555
1556 if (env->efer & MSR_EFER_LMA) {
1557 hflags |= HF_LMA_MASK;
1558 }
1559
1560 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1561 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1562 } else {
1563 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1564 (DESC_B_SHIFT - HF_CS32_SHIFT);
1565 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1566 (DESC_B_SHIFT - HF_SS32_SHIFT);
1567 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1568 !(hflags & HF_CS32_MASK)) {
1569 hflags |= HF_ADDSEG_MASK;
1570 } else {
1571 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1572 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1573 }
1574 }
1575 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1576
1577 return 0;
1578 }
1579
1580 static int kvm_get_msrs(X86CPU *cpu)
1581 {
1582 CPUX86State *env = &cpu->env;
1583 struct {
1584 struct kvm_msrs info;
1585 struct kvm_msr_entry entries[150];
1586 } msr_data;
1587 struct kvm_msr_entry *msrs = msr_data.entries;
1588 int ret, i, n;
1589
1590 n = 0;
1591 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1592 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1593 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1594 msrs[n++].index = MSR_PAT;
1595 if (has_msr_star) {
1596 msrs[n++].index = MSR_STAR;
1597 }
1598 if (has_msr_hsave_pa) {
1599 msrs[n++].index = MSR_VM_HSAVE_PA;
1600 }
1601 if (has_msr_tsc_adjust) {
1602 msrs[n++].index = MSR_TSC_ADJUST;
1603 }
1604 if (has_msr_tsc_deadline) {
1605 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1606 }
1607 if (has_msr_misc_enable) {
1608 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1609 }
1610 if (has_msr_feature_control) {
1611 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1612 }
1613 if (has_msr_bndcfgs) {
1614 msrs[n++].index = MSR_IA32_BNDCFGS;
1615 }
1616 if (has_msr_xss) {
1617 msrs[n++].index = MSR_IA32_XSS;
1618 }
1619
1620
1621 if (!env->tsc_valid) {
1622 msrs[n++].index = MSR_IA32_TSC;
1623 env->tsc_valid = !runstate_is_running();
1624 }
1625
1626 #ifdef TARGET_X86_64
1627 if (lm_capable_kernel) {
1628 msrs[n++].index = MSR_CSTAR;
1629 msrs[n++].index = MSR_KERNELGSBASE;
1630 msrs[n++].index = MSR_FMASK;
1631 msrs[n++].index = MSR_LSTAR;
1632 }
1633 #endif
1634 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1635 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1636 if (has_msr_async_pf_en) {
1637 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1638 }
1639 if (has_msr_pv_eoi_en) {
1640 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1641 }
1642 if (has_msr_kvm_steal_time) {
1643 msrs[n++].index = MSR_KVM_STEAL_TIME;
1644 }
1645 if (has_msr_architectural_pmu) {
1646 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1647 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1648 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1649 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1650 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1651 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1652 }
1653 for (i = 0; i < num_architectural_pmu_counters; i++) {
1654 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1655 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1656 }
1657 }
1658
1659 if (env->mcg_cap) {
1660 msrs[n++].index = MSR_MCG_STATUS;
1661 msrs[n++].index = MSR_MCG_CTL;
1662 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1663 msrs[n++].index = MSR_MC0_CTL + i;
1664 }
1665 }
1666
1667 if (has_msr_hv_hypercall) {
1668 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1669 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1670 }
1671 if (has_msr_hv_vapic) {
1672 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1673 }
1674 if (has_msr_hv_tsc) {
1675 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1676 }
1677 if (has_msr_mtrr) {
1678 msrs[n++].index = MSR_MTRRdefType;
1679 msrs[n++].index = MSR_MTRRfix64K_00000;
1680 msrs[n++].index = MSR_MTRRfix16K_80000;
1681 msrs[n++].index = MSR_MTRRfix16K_A0000;
1682 msrs[n++].index = MSR_MTRRfix4K_C0000;
1683 msrs[n++].index = MSR_MTRRfix4K_C8000;
1684 msrs[n++].index = MSR_MTRRfix4K_D0000;
1685 msrs[n++].index = MSR_MTRRfix4K_D8000;
1686 msrs[n++].index = MSR_MTRRfix4K_E0000;
1687 msrs[n++].index = MSR_MTRRfix4K_E8000;
1688 msrs[n++].index = MSR_MTRRfix4K_F0000;
1689 msrs[n++].index = MSR_MTRRfix4K_F8000;
1690 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1691 msrs[n++].index = MSR_MTRRphysBase(i);
1692 msrs[n++].index = MSR_MTRRphysMask(i);
1693 }
1694 }
1695
1696 msr_data.info = (struct kvm_msrs) {
1697 .nmsrs = n,
1698 };
1699
1700 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1701 if (ret < 0) {
1702 return ret;
1703 }
1704
1705 for (i = 0; i < ret; i++) {
1706 uint32_t index = msrs[i].index;
1707 switch (index) {
1708 case MSR_IA32_SYSENTER_CS:
1709 env->sysenter_cs = msrs[i].data;
1710 break;
1711 case MSR_IA32_SYSENTER_ESP:
1712 env->sysenter_esp = msrs[i].data;
1713 break;
1714 case MSR_IA32_SYSENTER_EIP:
1715 env->sysenter_eip = msrs[i].data;
1716 break;
1717 case MSR_PAT:
1718 env->pat = msrs[i].data;
1719 break;
1720 case MSR_STAR:
1721 env->star = msrs[i].data;
1722 break;
1723 #ifdef TARGET_X86_64
1724 case MSR_CSTAR:
1725 env->cstar = msrs[i].data;
1726 break;
1727 case MSR_KERNELGSBASE:
1728 env->kernelgsbase = msrs[i].data;
1729 break;
1730 case MSR_FMASK:
1731 env->fmask = msrs[i].data;
1732 break;
1733 case MSR_LSTAR:
1734 env->lstar = msrs[i].data;
1735 break;
1736 #endif
1737 case MSR_IA32_TSC:
1738 env->tsc = msrs[i].data;
1739 break;
1740 case MSR_TSC_ADJUST:
1741 env->tsc_adjust = msrs[i].data;
1742 break;
1743 case MSR_IA32_TSCDEADLINE:
1744 env->tsc_deadline = msrs[i].data;
1745 break;
1746 case MSR_VM_HSAVE_PA:
1747 env->vm_hsave = msrs[i].data;
1748 break;
1749 case MSR_KVM_SYSTEM_TIME:
1750 env->system_time_msr = msrs[i].data;
1751 break;
1752 case MSR_KVM_WALL_CLOCK:
1753 env->wall_clock_msr = msrs[i].data;
1754 break;
1755 case MSR_MCG_STATUS:
1756 env->mcg_status = msrs[i].data;
1757 break;
1758 case MSR_MCG_CTL:
1759 env->mcg_ctl = msrs[i].data;
1760 break;
1761 case MSR_IA32_MISC_ENABLE:
1762 env->msr_ia32_misc_enable = msrs[i].data;
1763 break;
1764 case MSR_IA32_FEATURE_CONTROL:
1765 env->msr_ia32_feature_control = msrs[i].data;
1766 break;
1767 case MSR_IA32_BNDCFGS:
1768 env->msr_bndcfgs = msrs[i].data;
1769 break;
1770 case MSR_IA32_XSS:
1771 env->xss = msrs[i].data;
1772 break;
1773 default:
1774 if (msrs[i].index >= MSR_MC0_CTL &&
1775 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1776 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1777 }
1778 break;
1779 case MSR_KVM_ASYNC_PF_EN:
1780 env->async_pf_en_msr = msrs[i].data;
1781 break;
1782 case MSR_KVM_PV_EOI_EN:
1783 env->pv_eoi_en_msr = msrs[i].data;
1784 break;
1785 case MSR_KVM_STEAL_TIME:
1786 env->steal_time_msr = msrs[i].data;
1787 break;
1788 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1789 env->msr_fixed_ctr_ctrl = msrs[i].data;
1790 break;
1791 case MSR_CORE_PERF_GLOBAL_CTRL:
1792 env->msr_global_ctrl = msrs[i].data;
1793 break;
1794 case MSR_CORE_PERF_GLOBAL_STATUS:
1795 env->msr_global_status = msrs[i].data;
1796 break;
1797 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1798 env->msr_global_ovf_ctrl = msrs[i].data;
1799 break;
1800 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1801 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1802 break;
1803 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1804 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1805 break;
1806 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1807 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1808 break;
1809 case HV_X64_MSR_HYPERCALL:
1810 env->msr_hv_hypercall = msrs[i].data;
1811 break;
1812 case HV_X64_MSR_GUEST_OS_ID:
1813 env->msr_hv_guest_os_id = msrs[i].data;
1814 break;
1815 case HV_X64_MSR_APIC_ASSIST_PAGE:
1816 env->msr_hv_vapic = msrs[i].data;
1817 break;
1818 case HV_X64_MSR_REFERENCE_TSC:
1819 env->msr_hv_tsc = msrs[i].data;
1820 break;
1821 case MSR_MTRRdefType:
1822 env->mtrr_deftype = msrs[i].data;
1823 break;
1824 case MSR_MTRRfix64K_00000:
1825 env->mtrr_fixed[0] = msrs[i].data;
1826 break;
1827 case MSR_MTRRfix16K_80000:
1828 env->mtrr_fixed[1] = msrs[i].data;
1829 break;
1830 case MSR_MTRRfix16K_A0000:
1831 env->mtrr_fixed[2] = msrs[i].data;
1832 break;
1833 case MSR_MTRRfix4K_C0000:
1834 env->mtrr_fixed[3] = msrs[i].data;
1835 break;
1836 case MSR_MTRRfix4K_C8000:
1837 env->mtrr_fixed[4] = msrs[i].data;
1838 break;
1839 case MSR_MTRRfix4K_D0000:
1840 env->mtrr_fixed[5] = msrs[i].data;
1841 break;
1842 case MSR_MTRRfix4K_D8000:
1843 env->mtrr_fixed[6] = msrs[i].data;
1844 break;
1845 case MSR_MTRRfix4K_E0000:
1846 env->mtrr_fixed[7] = msrs[i].data;
1847 break;
1848 case MSR_MTRRfix4K_E8000:
1849 env->mtrr_fixed[8] = msrs[i].data;
1850 break;
1851 case MSR_MTRRfix4K_F0000:
1852 env->mtrr_fixed[9] = msrs[i].data;
1853 break;
1854 case MSR_MTRRfix4K_F8000:
1855 env->mtrr_fixed[10] = msrs[i].data;
1856 break;
1857 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1858 if (index & 1) {
1859 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1860 } else {
1861 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1862 }
1863 break;
1864 }
1865 }
1866
1867 return 0;
1868 }
1869
1870 static int kvm_put_mp_state(X86CPU *cpu)
1871 {
1872 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1873
1874 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1875 }
1876
1877 static int kvm_get_mp_state(X86CPU *cpu)
1878 {
1879 CPUState *cs = CPU(cpu);
1880 CPUX86State *env = &cpu->env;
1881 struct kvm_mp_state mp_state;
1882 int ret;
1883
1884 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1885 if (ret < 0) {
1886 return ret;
1887 }
1888 env->mp_state = mp_state.mp_state;
1889 if (kvm_irqchip_in_kernel()) {
1890 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1891 }
1892 return 0;
1893 }
1894
1895 static int kvm_get_apic(X86CPU *cpu)
1896 {
1897 DeviceState *apic = cpu->apic_state;
1898 struct kvm_lapic_state kapic;
1899 int ret;
1900
1901 if (apic && kvm_irqchip_in_kernel()) {
1902 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1903 if (ret < 0) {
1904 return ret;
1905 }
1906
1907 kvm_get_apic_state(apic, &kapic);
1908 }
1909 return 0;
1910 }
1911
1912 static int kvm_put_apic(X86CPU *cpu)
1913 {
1914 DeviceState *apic = cpu->apic_state;
1915 struct kvm_lapic_state kapic;
1916
1917 if (apic && kvm_irqchip_in_kernel()) {
1918 kvm_put_apic_state(apic, &kapic);
1919
1920 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1921 }
1922 return 0;
1923 }
1924
1925 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1926 {
1927 CPUX86State *env = &cpu->env;
1928 struct kvm_vcpu_events events = {};
1929
1930 if (!kvm_has_vcpu_events()) {
1931 return 0;
1932 }
1933
1934 events.exception.injected = (env->exception_injected >= 0);
1935 events.exception.nr = env->exception_injected;
1936 events.exception.has_error_code = env->has_error_code;
1937 events.exception.error_code = env->error_code;
1938 events.exception.pad = 0;
1939
1940 events.interrupt.injected = (env->interrupt_injected >= 0);
1941 events.interrupt.nr = env->interrupt_injected;
1942 events.interrupt.soft = env->soft_interrupt;
1943
1944 events.nmi.injected = env->nmi_injected;
1945 events.nmi.pending = env->nmi_pending;
1946 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1947 events.nmi.pad = 0;
1948
1949 events.sipi_vector = env->sipi_vector;
1950
1951 events.flags = 0;
1952 if (level >= KVM_PUT_RESET_STATE) {
1953 events.flags |=
1954 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1955 }
1956
1957 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1958 }
1959
1960 static int kvm_get_vcpu_events(X86CPU *cpu)
1961 {
1962 CPUX86State *env = &cpu->env;
1963 struct kvm_vcpu_events events;
1964 int ret;
1965
1966 if (!kvm_has_vcpu_events()) {
1967 return 0;
1968 }
1969
1970 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1971 if (ret < 0) {
1972 return ret;
1973 }
1974 env->exception_injected =
1975 events.exception.injected ? events.exception.nr : -1;
1976 env->has_error_code = events.exception.has_error_code;
1977 env->error_code = events.exception.error_code;
1978
1979 env->interrupt_injected =
1980 events.interrupt.injected ? events.interrupt.nr : -1;
1981 env->soft_interrupt = events.interrupt.soft;
1982
1983 env->nmi_injected = events.nmi.injected;
1984 env->nmi_pending = events.nmi.pending;
1985 if (events.nmi.masked) {
1986 env->hflags2 |= HF2_NMI_MASK;
1987 } else {
1988 env->hflags2 &= ~HF2_NMI_MASK;
1989 }
1990
1991 env->sipi_vector = events.sipi_vector;
1992
1993 return 0;
1994 }
1995
1996 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1997 {
1998 CPUState *cs = CPU(cpu);
1999 CPUX86State *env = &cpu->env;
2000 int ret = 0;
2001 unsigned long reinject_trap = 0;
2002
2003 if (!kvm_has_vcpu_events()) {
2004 if (env->exception_injected == 1) {
2005 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2006 } else if (env->exception_injected == 3) {
2007 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2008 }
2009 env->exception_injected = -1;
2010 }
2011
2012 /*
2013 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2014 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2015 * by updating the debug state once again if single-stepping is on.
2016 * Another reason to call kvm_update_guest_debug here is a pending debug
2017 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2018 * reinject them via SET_GUEST_DEBUG.
2019 */
2020 if (reinject_trap ||
2021 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2022 ret = kvm_update_guest_debug(cs, reinject_trap);
2023 }
2024 return ret;
2025 }
2026
2027 static int kvm_put_debugregs(X86CPU *cpu)
2028 {
2029 CPUX86State *env = &cpu->env;
2030 struct kvm_debugregs dbgregs;
2031 int i;
2032
2033 if (!kvm_has_debugregs()) {
2034 return 0;
2035 }
2036
2037 for (i = 0; i < 4; i++) {
2038 dbgregs.db[i] = env->dr[i];
2039 }
2040 dbgregs.dr6 = env->dr[6];
2041 dbgregs.dr7 = env->dr[7];
2042 dbgregs.flags = 0;
2043
2044 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2045 }
2046
2047 static int kvm_get_debugregs(X86CPU *cpu)
2048 {
2049 CPUX86State *env = &cpu->env;
2050 struct kvm_debugregs dbgregs;
2051 int i, ret;
2052
2053 if (!kvm_has_debugregs()) {
2054 return 0;
2055 }
2056
2057 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2058 if (ret < 0) {
2059 return ret;
2060 }
2061 for (i = 0; i < 4; i++) {
2062 env->dr[i] = dbgregs.db[i];
2063 }
2064 env->dr[4] = env->dr[6] = dbgregs.dr6;
2065 env->dr[5] = env->dr[7] = dbgregs.dr7;
2066
2067 return 0;
2068 }
2069
2070 int kvm_arch_put_registers(CPUState *cpu, int level)
2071 {
2072 X86CPU *x86_cpu = X86_CPU(cpu);
2073 int ret;
2074
2075 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2076
2077 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2078 ret = kvm_put_msr_feature_control(x86_cpu);
2079 if (ret < 0) {
2080 return ret;
2081 }
2082 }
2083
2084 ret = kvm_getput_regs(x86_cpu, 1);
2085 if (ret < 0) {
2086 return ret;
2087 }
2088 ret = kvm_put_xsave(x86_cpu);
2089 if (ret < 0) {
2090 return ret;
2091 }
2092 ret = kvm_put_xcrs(x86_cpu);
2093 if (ret < 0) {
2094 return ret;
2095 }
2096 ret = kvm_put_sregs(x86_cpu);
2097 if (ret < 0) {
2098 return ret;
2099 }
2100 /* must be before kvm_put_msrs */
2101 ret = kvm_inject_mce_oldstyle(x86_cpu);
2102 if (ret < 0) {
2103 return ret;
2104 }
2105 ret = kvm_put_msrs(x86_cpu, level);
2106 if (ret < 0) {
2107 return ret;
2108 }
2109 if (level >= KVM_PUT_RESET_STATE) {
2110 ret = kvm_put_mp_state(x86_cpu);
2111 if (ret < 0) {
2112 return ret;
2113 }
2114 ret = kvm_put_apic(x86_cpu);
2115 if (ret < 0) {
2116 return ret;
2117 }
2118 }
2119
2120 ret = kvm_put_tscdeadline_msr(x86_cpu);
2121 if (ret < 0) {
2122 return ret;
2123 }
2124
2125 ret = kvm_put_vcpu_events(x86_cpu, level);
2126 if (ret < 0) {
2127 return ret;
2128 }
2129 ret = kvm_put_debugregs(x86_cpu);
2130 if (ret < 0) {
2131 return ret;
2132 }
2133 /* must be last */
2134 ret = kvm_guest_debug_workarounds(x86_cpu);
2135 if (ret < 0) {
2136 return ret;
2137 }
2138 return 0;
2139 }
2140
2141 int kvm_arch_get_registers(CPUState *cs)
2142 {
2143 X86CPU *cpu = X86_CPU(cs);
2144 int ret;
2145
2146 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2147
2148 ret = kvm_getput_regs(cpu, 0);
2149 if (ret < 0) {
2150 return ret;
2151 }
2152 ret = kvm_get_xsave(cpu);
2153 if (ret < 0) {
2154 return ret;
2155 }
2156 ret = kvm_get_xcrs(cpu);
2157 if (ret < 0) {
2158 return ret;
2159 }
2160 ret = kvm_get_sregs(cpu);
2161 if (ret < 0) {
2162 return ret;
2163 }
2164 ret = kvm_get_msrs(cpu);
2165 if (ret < 0) {
2166 return ret;
2167 }
2168 ret = kvm_get_mp_state(cpu);
2169 if (ret < 0) {
2170 return ret;
2171 }
2172 ret = kvm_get_apic(cpu);
2173 if (ret < 0) {
2174 return ret;
2175 }
2176 ret = kvm_get_vcpu_events(cpu);
2177 if (ret < 0) {
2178 return ret;
2179 }
2180 ret = kvm_get_debugregs(cpu);
2181 if (ret < 0) {
2182 return ret;
2183 }
2184 return 0;
2185 }
2186
2187 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2188 {
2189 X86CPU *x86_cpu = X86_CPU(cpu);
2190 CPUX86State *env = &x86_cpu->env;
2191 int ret;
2192
2193 /* Inject NMI */
2194 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2195 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2196 DPRINTF("injected NMI\n");
2197 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2198 if (ret < 0) {
2199 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2200 strerror(-ret));
2201 }
2202 }
2203
2204 /* Force the VCPU out of its inner loop to process any INIT requests
2205 * or (for userspace APIC, but it is cheap to combine the checks here)
2206 * pending TPR access reports.
2207 */
2208 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2209 cpu->exit_request = 1;
2210 }
2211
2212 if (!kvm_irqchip_in_kernel()) {
2213 /* Try to inject an interrupt if the guest can accept it */
2214 if (run->ready_for_interrupt_injection &&
2215 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2216 (env->eflags & IF_MASK)) {
2217 int irq;
2218
2219 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2220 irq = cpu_get_pic_interrupt(env);
2221 if (irq >= 0) {
2222 struct kvm_interrupt intr;
2223
2224 intr.irq = irq;
2225 DPRINTF("injected interrupt %d\n", irq);
2226 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2227 if (ret < 0) {
2228 fprintf(stderr,
2229 "KVM: injection failed, interrupt lost (%s)\n",
2230 strerror(-ret));
2231 }
2232 }
2233 }
2234
2235 /* If we have an interrupt but the guest is not ready to receive an
2236 * interrupt, request an interrupt window exit. This will
2237 * cause a return to userspace as soon as the guest is ready to
2238 * receive interrupts. */
2239 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2240 run->request_interrupt_window = 1;
2241 } else {
2242 run->request_interrupt_window = 0;
2243 }
2244
2245 DPRINTF("setting tpr\n");
2246 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2247 }
2248 }
2249
2250 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2251 {
2252 X86CPU *x86_cpu = X86_CPU(cpu);
2253 CPUX86State *env = &x86_cpu->env;
2254
2255 if (run->if_flag) {
2256 env->eflags |= IF_MASK;
2257 } else {
2258 env->eflags &= ~IF_MASK;
2259 }
2260 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2261 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2262 }
2263
2264 int kvm_arch_process_async_events(CPUState *cs)
2265 {
2266 X86CPU *cpu = X86_CPU(cs);
2267 CPUX86State *env = &cpu->env;
2268
2269 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2270 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2271 assert(env->mcg_cap);
2272
2273 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2274
2275 kvm_cpu_synchronize_state(cs);
2276
2277 if (env->exception_injected == EXCP08_DBLE) {
2278 /* this means triple fault */
2279 qemu_system_reset_request();
2280 cs->exit_request = 1;
2281 return 0;
2282 }
2283 env->exception_injected = EXCP12_MCHK;
2284 env->has_error_code = 0;
2285
2286 cs->halted = 0;
2287 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2288 env->mp_state = KVM_MP_STATE_RUNNABLE;
2289 }
2290 }
2291
2292 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2293 kvm_cpu_synchronize_state(cs);
2294 do_cpu_init(cpu);
2295 }
2296
2297 if (kvm_irqchip_in_kernel()) {
2298 return 0;
2299 }
2300
2301 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2302 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2303 apic_poll_irq(cpu->apic_state);
2304 }
2305 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2306 (env->eflags & IF_MASK)) ||
2307 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2308 cs->halted = 0;
2309 }
2310 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2311 kvm_cpu_synchronize_state(cs);
2312 do_cpu_sipi(cpu);
2313 }
2314 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2315 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2316 kvm_cpu_synchronize_state(cs);
2317 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2318 env->tpr_access_type);
2319 }
2320
2321 return cs->halted;
2322 }
2323
2324 static int kvm_handle_halt(X86CPU *cpu)
2325 {
2326 CPUState *cs = CPU(cpu);
2327 CPUX86State *env = &cpu->env;
2328
2329 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2330 (env->eflags & IF_MASK)) &&
2331 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2332 cs->halted = 1;
2333 return EXCP_HLT;
2334 }
2335
2336 return 0;
2337 }
2338
2339 static int kvm_handle_tpr_access(X86CPU *cpu)
2340 {
2341 CPUState *cs = CPU(cpu);
2342 struct kvm_run *run = cs->kvm_run;
2343
2344 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2345 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2346 : TPR_ACCESS_READ);
2347 return 1;
2348 }
2349
2350 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2351 {
2352 static const uint8_t int3 = 0xcc;
2353
2354 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2355 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2356 return -EINVAL;
2357 }
2358 return 0;
2359 }
2360
2361 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2362 {
2363 uint8_t int3;
2364
2365 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2366 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2367 return -EINVAL;
2368 }
2369 return 0;
2370 }
2371
2372 static struct {
2373 target_ulong addr;
2374 int len;
2375 int type;
2376 } hw_breakpoint[4];
2377
2378 static int nb_hw_breakpoint;
2379
2380 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2381 {
2382 int n;
2383
2384 for (n = 0; n < nb_hw_breakpoint; n++) {
2385 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2386 (hw_breakpoint[n].len == len || len == -1)) {
2387 return n;
2388 }
2389 }
2390 return -1;
2391 }
2392
2393 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2394 target_ulong len, int type)
2395 {
2396 switch (type) {
2397 case GDB_BREAKPOINT_HW:
2398 len = 1;
2399 break;
2400 case GDB_WATCHPOINT_WRITE:
2401 case GDB_WATCHPOINT_ACCESS:
2402 switch (len) {
2403 case 1:
2404 break;
2405 case 2:
2406 case 4:
2407 case 8:
2408 if (addr & (len - 1)) {
2409 return -EINVAL;
2410 }
2411 break;
2412 default:
2413 return -EINVAL;
2414 }
2415 break;
2416 default:
2417 return -ENOSYS;
2418 }
2419
2420 if (nb_hw_breakpoint == 4) {
2421 return -ENOBUFS;
2422 }
2423 if (find_hw_breakpoint(addr, len, type) >= 0) {
2424 return -EEXIST;
2425 }
2426 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2427 hw_breakpoint[nb_hw_breakpoint].len = len;
2428 hw_breakpoint[nb_hw_breakpoint].type = type;
2429 nb_hw_breakpoint++;
2430
2431 return 0;
2432 }
2433
2434 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2435 target_ulong len, int type)
2436 {
2437 int n;
2438
2439 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2440 if (n < 0) {
2441 return -ENOENT;
2442 }
2443 nb_hw_breakpoint--;
2444 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2445
2446 return 0;
2447 }
2448
2449 void kvm_arch_remove_all_hw_breakpoints(void)
2450 {
2451 nb_hw_breakpoint = 0;
2452 }
2453
2454 static CPUWatchpoint hw_watchpoint;
2455
2456 static int kvm_handle_debug(X86CPU *cpu,
2457 struct kvm_debug_exit_arch *arch_info)
2458 {
2459 CPUState *cs = CPU(cpu);
2460 CPUX86State *env = &cpu->env;
2461 int ret = 0;
2462 int n;
2463
2464 if (arch_info->exception == 1) {
2465 if (arch_info->dr6 & (1 << 14)) {
2466 if (cs->singlestep_enabled) {
2467 ret = EXCP_DEBUG;
2468 }
2469 } else {
2470 for (n = 0; n < 4; n++) {
2471 if (arch_info->dr6 & (1 << n)) {
2472 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2473 case 0x0:
2474 ret = EXCP_DEBUG;
2475 break;
2476 case 0x1:
2477 ret = EXCP_DEBUG;
2478 cs->watchpoint_hit = &hw_watchpoint;
2479 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2480 hw_watchpoint.flags = BP_MEM_WRITE;
2481 break;
2482 case 0x3:
2483 ret = EXCP_DEBUG;
2484 cs->watchpoint_hit = &hw_watchpoint;
2485 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2486 hw_watchpoint.flags = BP_MEM_ACCESS;
2487 break;
2488 }
2489 }
2490 }
2491 }
2492 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2493 ret = EXCP_DEBUG;
2494 }
2495 if (ret == 0) {
2496 cpu_synchronize_state(cs);
2497 assert(env->exception_injected == -1);
2498
2499 /* pass to guest */
2500 env->exception_injected = arch_info->exception;
2501 env->has_error_code = 0;
2502 }
2503
2504 return ret;
2505 }
2506
2507 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2508 {
2509 const uint8_t type_code[] = {
2510 [GDB_BREAKPOINT_HW] = 0x0,
2511 [GDB_WATCHPOINT_WRITE] = 0x1,
2512 [GDB_WATCHPOINT_ACCESS] = 0x3
2513 };
2514 const uint8_t len_code[] = {
2515 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2516 };
2517 int n;
2518
2519 if (kvm_sw_breakpoints_active(cpu)) {
2520 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2521 }
2522 if (nb_hw_breakpoint > 0) {
2523 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2524 dbg->arch.debugreg[7] = 0x0600;
2525 for (n = 0; n < nb_hw_breakpoint; n++) {
2526 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2527 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2528 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2529 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2530 }
2531 }
2532 }
2533
2534 static bool host_supports_vmx(void)
2535 {
2536 uint32_t ecx, unused;
2537
2538 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2539 return ecx & CPUID_EXT_VMX;
2540 }
2541
2542 #define VMX_INVALID_GUEST_STATE 0x80000021
2543
2544 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2545 {
2546 X86CPU *cpu = X86_CPU(cs);
2547 uint64_t code;
2548 int ret;
2549
2550 switch (run->exit_reason) {
2551 case KVM_EXIT_HLT:
2552 DPRINTF("handle_hlt\n");
2553 ret = kvm_handle_halt(cpu);
2554 break;
2555 case KVM_EXIT_SET_TPR:
2556 ret = 0;
2557 break;
2558 case KVM_EXIT_TPR_ACCESS:
2559 ret = kvm_handle_tpr_access(cpu);
2560 break;
2561 case KVM_EXIT_FAIL_ENTRY:
2562 code = run->fail_entry.hardware_entry_failure_reason;
2563 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2564 code);
2565 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2566 fprintf(stderr,
2567 "\nIf you're running a guest on an Intel machine without "
2568 "unrestricted mode\n"
2569 "support, the failure can be most likely due to the guest "
2570 "entering an invalid\n"
2571 "state for Intel VT. For example, the guest maybe running "
2572 "in big real mode\n"
2573 "which is not supported on less recent Intel processors."
2574 "\n\n");
2575 }
2576 ret = -1;
2577 break;
2578 case KVM_EXIT_EXCEPTION:
2579 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2580 run->ex.exception, run->ex.error_code);
2581 ret = -1;
2582 break;
2583 case KVM_EXIT_DEBUG:
2584 DPRINTF("kvm_exit_debug\n");
2585 ret = kvm_handle_debug(cpu, &run->debug.arch);
2586 break;
2587 default:
2588 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2589 ret = -1;
2590 break;
2591 }
2592
2593 return ret;
2594 }
2595
2596 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2597 {
2598 X86CPU *cpu = X86_CPU(cs);
2599 CPUX86State *env = &cpu->env;
2600
2601 kvm_cpu_synchronize_state(cs);
2602 return !(env->cr[0] & CR0_PE_MASK) ||
2603 ((env->segs[R_CS].selector & 3) != 3);
2604 }
2605
2606 void kvm_arch_init_irq_routing(KVMState *s)
2607 {
2608 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2609 /* If kernel can't do irq routing, interrupt source
2610 * override 0->2 cannot be set up as required by HPET.
2611 * So we have to disable it.
2612 */
2613 no_hpet = 1;
2614 }
2615 /* We know at this point that we're using the in-kernel
2616 * irqchip, so we can use irqfds, and on x86 we know
2617 * we can use msi via irqfd and GSI routing.
2618 */
2619 kvm_msi_via_irqfd_allowed = true;
2620 kvm_gsi_routing_allowed = true;
2621 }
2622
2623 /* Classic KVM device assignment interface. Will remain x86 only. */
2624 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2625 uint32_t flags, uint32_t *dev_id)
2626 {
2627 struct kvm_assigned_pci_dev dev_data = {
2628 .segnr = dev_addr->domain,
2629 .busnr = dev_addr->bus,
2630 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2631 .flags = flags,
2632 };
2633 int ret;
2634
2635 dev_data.assigned_dev_id =
2636 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2637
2638 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2639 if (ret < 0) {
2640 return ret;
2641 }
2642
2643 *dev_id = dev_data.assigned_dev_id;
2644
2645 return 0;
2646 }
2647
2648 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2649 {
2650 struct kvm_assigned_pci_dev dev_data = {
2651 .assigned_dev_id = dev_id,
2652 };
2653
2654 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2655 }
2656
2657 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2658 uint32_t irq_type, uint32_t guest_irq)
2659 {
2660 struct kvm_assigned_irq assigned_irq = {
2661 .assigned_dev_id = dev_id,
2662 .guest_irq = guest_irq,
2663 .flags = irq_type,
2664 };
2665
2666 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2667 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2668 } else {
2669 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2670 }
2671 }
2672
2673 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2674 uint32_t guest_irq)
2675 {
2676 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2677 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2678
2679 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2680 }
2681
2682 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2683 {
2684 struct kvm_assigned_pci_dev dev_data = {
2685 .assigned_dev_id = dev_id,
2686 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2687 };
2688
2689 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2690 }
2691
2692 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2693 uint32_t type)
2694 {
2695 struct kvm_assigned_irq assigned_irq = {
2696 .assigned_dev_id = dev_id,
2697 .flags = type,
2698 };
2699
2700 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2701 }
2702
2703 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2704 {
2705 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2706 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2707 }
2708
2709 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2710 {
2711 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2712 KVM_DEV_IRQ_GUEST_MSI, virq);
2713 }
2714
2715 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2716 {
2717 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2718 KVM_DEV_IRQ_HOST_MSI);
2719 }
2720
2721 bool kvm_device_msix_supported(KVMState *s)
2722 {
2723 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2724 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2725 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2726 }
2727
2728 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2729 uint32_t nr_vectors)
2730 {
2731 struct kvm_assigned_msix_nr msix_nr = {
2732 .assigned_dev_id = dev_id,
2733 .entry_nr = nr_vectors,
2734 };
2735
2736 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2737 }
2738
2739 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2740 int virq)
2741 {
2742 struct kvm_assigned_msix_entry msix_entry = {
2743 .assigned_dev_id = dev_id,
2744 .gsi = virq,
2745 .entry = vector,
2746 };
2747
2748 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2749 }
2750
2751 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2752 {
2753 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2754 KVM_DEV_IRQ_GUEST_MSIX, 0);
2755 }
2756
2757 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2758 {
2759 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2760 KVM_DEV_IRQ_HOST_MSIX);
2761 }
2762
2763 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2764 uint64_t address, uint32_t data)
2765 {
2766 return 0;
2767 }
AR7 emulation for QEMU