hw/char/parallel.c

   1 /*
   2  * QEMU Parallel PORT emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2007 Marko Kohtala
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "hw/hw.h"
  28 #include "chardev/char-parallel.h"
  29 #include "chardev/char-fe.h"
  30 #include "hw/isa/isa.h"
  31 #include "hw/i386/pc.h"
  32 #include "sysemu/sysemu.h"
  33
  34 //#define DEBUG_PARALLEL
  35
  36 #ifdef DEBUG_PARALLEL
  37 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
  38 #else
  39 #define pdebug(fmt, ...) ((void)0)
  40 #endif
  41
  42 #define PARA_REG_DATA 0
  43 #define PARA_REG_STS 1
  44 #define PARA_REG_CTR 2
  45 #define PARA_REG_EPP_ADDR 3
  46 #define PARA_REG_EPP_DATA 4
  47
  48 /*
  49  * These are the definitions for the Printer Status Register
  50  */
  51 #define PARA_STS_BUSY   0x80    /* Busy complement */
  52 #define PARA_STS_ACK    0x40    /* Acknowledge */
  53 #define PARA_STS_PAPER  0x20    /* Out of paper */
  54 #define PARA_STS_ONLINE 0x10    /* Online */
  55 #define PARA_STS_ERROR  0x08    /* Error complement */
  56 #define PARA_STS_TMOUT  0x01    /* EPP timeout */
  57
  58 /*
  59  * These are the definitions for the Printer Control Register
  60  */
  61 #define PARA_CTR_DIR    0x20    /* Direction (1=read, 0=write) */
  62 #define PARA_CTR_INTEN  0x10    /* IRQ Enable */
  63 #define PARA_CTR_SELECT 0x08    /* Select In complement */
  64 #define PARA_CTR_INIT   0x04    /* Initialize Printer complement */
  65 #define PARA_CTR_AUTOLF 0x02    /* Auto linefeed complement */
  66 #define PARA_CTR_STROBE 0x01    /* Strobe complement */
  67
  68 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
  69
  70 typedef struct ParallelState {
  71     MemoryRegion iomem;
  72     uint8_t dataw;
  73     uint8_t datar;
  74     uint8_t status;
  75     uint8_t control;
  76     qemu_irq irq;
  77     int irq_pending;
  78     CharBackend chr;
  79     int hw_driver;
  80     int epp_timeout;
  81     uint32_t last_read_offset; /* For debugging */
  82     /* Memory-mapped interface */
  83     int it_shift;
  84     PortioList portio_list;
  85 } ParallelState;
  86
  87 #define TYPE_ISA_PARALLEL "isa-parallel"
  88 #define ISA_PARALLEL(obj) \
  89     OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)
  90
  91 typedef struct ISAParallelState {
  92     ISADevice parent_obj;
  93
  94     uint32_t index;
  95     uint32_t iobase;
  96     uint32_t isairq;
  97     ParallelState state;
  98 } ISAParallelState;
  99
 100 static void parallel_update_irq(ParallelState *s)
 101 {
 102     if (s->irq_pending)
 103         qemu_irq_raise(s->irq);
 104     else
 105         qemu_irq_lower(s->irq);
 106 }
 107
 108 static void
 109 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
 110 {
 111     ParallelState *s = opaque;
 112
 113     pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
 114
 115     addr &= 7;
 116     switch(addr) {
 117     case PARA_REG_DATA:
 118         s->dataw = val;
 119         parallel_update_irq(s);
 120         break;
 121     case PARA_REG_CTR:
 122         val |= 0xc0;
 123         if ((val & PARA_CTR_INIT) == 0 ) {
 124             s->status = PARA_STS_BUSY;
 125             s->status |= PARA_STS_ACK;
 126             s->status |= PARA_STS_ONLINE;
 127             s->status |= PARA_STS_ERROR;
 128         }
 129         else if (val & PARA_CTR_SELECT) {
 130             if (val & PARA_CTR_STROBE) {
 131                 s->status &= ~PARA_STS_BUSY;
 132                 if ((s->control & PARA_CTR_STROBE) == 0)
 133                     /* XXX this blocks entire thread. Rewrite to use
 134                      * qemu_chr_fe_write and background I/O callbacks */
 135                     qemu_chr_fe_write_all(&s->chr, &s->dataw, 1);
 136             } else {
 137                 if (s->control & PARA_CTR_INTEN) {
 138                     s->irq_pending = 1;
 139                 }
 140             }
 141         }
 142         parallel_update_irq(s);
 143         s->control = val;
 144         break;
 145     }
 146 }
 147
 148 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
 149 {
 150     ParallelState *s = opaque;
 151     uint8_t parm = val;
 152     int dir;
 153
 154     /* Sometimes programs do several writes for timing purposes on old
 155        HW. Take care not to waste time on writes that do nothing. */
 156
 157     s->last_read_offset = ~0U;
 158
 159     addr &= 7;
 160     switch(addr) {
 161     case PARA_REG_DATA:
 162         if (s->dataw == val)
 163             return;
 164         pdebug("wd%02x\n", val);
 165         qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
 166         s->dataw = val;
 167         break;
 168     case PARA_REG_STS:
 169         pdebug("ws%02x\n", val);
 170         if (val & PARA_STS_TMOUT)
 171             s->epp_timeout = 0;
 172         break;
 173     case PARA_REG_CTR:
 174         val |= 0xc0;
 175         if (s->control == val)
 176             return;
 177         pdebug("wc%02x\n", val);
 178
 179         if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
 180             if (val & PARA_CTR_DIR) {
 181                 dir = 1;
 182             } else {
 183                 dir = 0;
 184             }
 185             qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
 186             parm &= ~PARA_CTR_DIR;
 187         }
 188
 189         qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
 190         s->control = val;
 191         break;
 192     case PARA_REG_EPP_ADDR:
 193         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 194             /* Controls not correct for EPP address cycle, so do nothing */
 195             pdebug("wa%02x s\n", val);
 196         else {
 197             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 198             if (qemu_chr_fe_ioctl(&s->chr,
 199                                   CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
 200                 s->epp_timeout = 1;
 201                 pdebug("wa%02x t\n", val);
 202             }
 203             else
 204                 pdebug("wa%02x\n", val);
 205         }
 206         break;
 207     case PARA_REG_EPP_DATA:
 208         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 209             /* Controls not correct for EPP data cycle, so do nothing */
 210             pdebug("we%02x s\n", val);
 211         else {
 212             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 213             if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
 214                 s->epp_timeout = 1;
 215                 pdebug("we%02x t\n", val);
 216             }
 217             else
 218                 pdebug("we%02x\n", val);
 219         }
 220         break;
 221     }
 222 }
 223
 224 static void
 225 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
 226 {
 227     ParallelState *s = opaque;
 228     uint16_t eppdata = cpu_to_le16(val);
 229     int err;
 230     struct ParallelIOArg ioarg = {
 231         .buffer = &eppdata, .count = sizeof(eppdata)
 232     };
 233     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 234         /* Controls not correct for EPP data cycle, so do nothing */
 235         pdebug("we%04x s\n", val);
 236         return;
 237     }
 238     err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 239     if (err) {
 240         s->epp_timeout = 1;
 241         pdebug("we%04x t\n", val);
 242     }
 243     else
 244         pdebug("we%04x\n", val);
 245 }
 246
 247 static void
 248 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
 249 {
 250     ParallelState *s = opaque;
 251     uint32_t eppdata = cpu_to_le32(val);
 252     int err;
 253     struct ParallelIOArg ioarg = {
 254         .buffer = &eppdata, .count = sizeof(eppdata)
 255     };
 256     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 257         /* Controls not correct for EPP data cycle, so do nothing */
 258         pdebug("we%08x s\n", val);
 259         return;
 260     }
 261     err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 262     if (err) {
 263         s->epp_timeout = 1;
 264         pdebug("we%08x t\n", val);
 265     }
 266     else
 267         pdebug("we%08x\n", val);
 268 }
 269
 270 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
 271 {
 272     ParallelState *s = opaque;
 273     uint32_t ret = 0xff;
 274
 275     addr &= 7;
 276     switch(addr) {
 277     case PARA_REG_DATA:
 278         if (s->control & PARA_CTR_DIR)
 279             ret = s->datar;
 280         else
 281             ret = s->dataw;
 282         break;
 283     case PARA_REG_STS:
 284         ret = s->status;
 285         s->irq_pending = 0;
 286         if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
 287             /* XXX Fixme: wait 5 microseconds */
 288             if (s->status & PARA_STS_ACK)
 289                 s->status &= ~PARA_STS_ACK;
 290             else {
 291                 /* XXX Fixme: wait 5 microseconds */
 292                 s->status |= PARA_STS_ACK;
 293                 s->status |= PARA_STS_BUSY;
 294             }
 295         }
 296         parallel_update_irq(s);
 297         break;
 298     case PARA_REG_CTR:
 299         ret = s->control;
 300         break;
 301     }
 302     pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
 303     return ret;
 304 }
 305
 306 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
 307 {
 308     ParallelState *s = opaque;
 309     uint8_t ret = 0xff;
 310     addr &= 7;
 311     switch(addr) {
 312     case PARA_REG_DATA:
 313         qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
 314         if (s->last_read_offset != addr || s->datar != ret)
 315             pdebug("rd%02x\n", ret);
 316         s->datar = ret;
 317         break;
 318     case PARA_REG_STS:
 319         qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
 320         ret &= ~PARA_STS_TMOUT;
 321         if (s->epp_timeout)
 322             ret |= PARA_STS_TMOUT;
 323         if (s->last_read_offset != addr || s->status != ret)
 324             pdebug("rs%02x\n", ret);
 325         s->status = ret;
 326         break;
 327     case PARA_REG_CTR:
 328         /* s->control has some bits fixed to 1. It is zero only when
 329            it has not been yet written to.  */
 330         if (s->control == 0) {
 331             qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
 332             if (s->last_read_offset != addr)
 333                 pdebug("rc%02x\n", ret);
 334             s->control = ret;
 335         }
 336         else {
 337             ret = s->control;
 338             if (s->last_read_offset != addr)
 339                 pdebug("rc%02x\n", ret);
 340         }
 341         break;
 342     case PARA_REG_EPP_ADDR:
 343         if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
 344             (PARA_CTR_DIR | PARA_CTR_INIT))
 345             /* Controls not correct for EPP addr cycle, so do nothing */
 346             pdebug("ra%02x s\n", ret);
 347         else {
 348             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 349             if (qemu_chr_fe_ioctl(&s->chr,
 350                                   CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
 351                 s->epp_timeout = 1;
 352                 pdebug("ra%02x t\n", ret);
 353             }
 354             else
 355                 pdebug("ra%02x\n", ret);
 356         }
 357         break;
 358     case PARA_REG_EPP_DATA:
 359         if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
 360             (PARA_CTR_DIR | PARA_CTR_INIT))
 361             /* Controls not correct for EPP data cycle, so do nothing */
 362             pdebug("re%02x s\n", ret);
 363         else {
 364             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 365             if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
 366                 s->epp_timeout = 1;
 367                 pdebug("re%02x t\n", ret);
 368             }
 369             else
 370                 pdebug("re%02x\n", ret);
 371         }
 372         break;
 373     }
 374     s->last_read_offset = addr;
 375     return ret;
 376 }
 377
 378 static uint32_t
 379 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
 380 {
 381     ParallelState *s = opaque;
 382     uint32_t ret;
 383     uint16_t eppdata = ~0;
 384     int err;
 385     struct ParallelIOArg ioarg = {
 386         .buffer = &eppdata, .count = sizeof(eppdata)
 387     };
 388     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 389         /* Controls not correct for EPP data cycle, so do nothing */
 390         pdebug("re%04x s\n", eppdata);
 391         return eppdata;
 392     }
 393     err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 394     ret = le16_to_cpu(eppdata);
 395
 396     if (err) {
 397         s->epp_timeout = 1;
 398         pdebug("re%04x t\n", ret);
 399     }
 400     else
 401         pdebug("re%04x\n", ret);
 402     return ret;
 403 }
 404
 405 static uint32_t
 406 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
 407 {
 408     ParallelState *s = opaque;
 409     uint32_t ret;
 410     uint32_t eppdata = ~0U;
 411     int err;
 412     struct ParallelIOArg ioarg = {
 413         .buffer = &eppdata, .count = sizeof(eppdata)
 414     };
 415     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 416         /* Controls not correct for EPP data cycle, so do nothing */
 417         pdebug("re%08x s\n", eppdata);
 418         return eppdata;
 419     }
 420     err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 421     ret = le32_to_cpu(eppdata);
 422
 423     if (err) {
 424         s->epp_timeout = 1;
 425         pdebug("re%08x t\n", ret);
 426     }
 427     else
 428         pdebug("re%08x\n", ret);
 429     return ret;
 430 }
 431
 432 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
 433 {
 434     pdebug("wecp%d=%02x\n", addr & 7, val);
 435 }
 436
 437 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
 438 {
 439     uint8_t ret = 0xff;
 440
 441     pdebug("recp%d:%02x\n", addr & 7, ret);
 442     return ret;
 443 }
 444
 445 static void parallel_reset(void *opaque)
 446 {
 447     ParallelState *s = opaque;
 448
 449     s->datar = ~0;
 450     s->dataw = ~0;
 451     s->status = PARA_STS_BUSY;
 452     s->status |= PARA_STS_ACK;
 453     s->status |= PARA_STS_ONLINE;
 454     s->status |= PARA_STS_ERROR;
 455     s->status |= PARA_STS_TMOUT;
 456     s->control = PARA_CTR_SELECT;
 457     s->control |= PARA_CTR_INIT;
 458     s->control |= 0xc0;
 459     s->irq_pending = 0;
 460     s->hw_driver = 0;
 461     s->epp_timeout = 0;
 462     s->last_read_offset = ~0U;
 463 }
 464
 465 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 466
 467 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
 468     { 0, 8, 1,
 469       .read = parallel_ioport_read_hw,
 470       .write = parallel_ioport_write_hw },
 471     { 4, 1, 2,
 472       .read = parallel_ioport_eppdata_read_hw2,
 473       .write = parallel_ioport_eppdata_write_hw2 },
 474     { 4, 1, 4,
 475       .read = parallel_ioport_eppdata_read_hw4,
 476       .write = parallel_ioport_eppdata_write_hw4 },
 477     { 0x400, 8, 1,
 478       .read = parallel_ioport_ecp_read,
 479       .write = parallel_ioport_ecp_write },
 480     PORTIO_END_OF_LIST(),
 481 };
 482
 483 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
 484     { 0, 8, 1,
 485       .read = parallel_ioport_read_sw,
 486       .write = parallel_ioport_write_sw },
 487     PORTIO_END_OF_LIST(),
 488 };
 489
 490
 491 static const VMStateDescription vmstate_parallel_isa = {
 492     .name = "parallel_isa",
 493     .version_id = 1,
 494     .minimum_version_id = 1,
 495     .fields      = (VMStateField[]) {
 496         VMSTATE_UINT8(state.dataw, ISAParallelState),
 497         VMSTATE_UINT8(state.datar, ISAParallelState),
 498         VMSTATE_UINT8(state.status, ISAParallelState),
 499         VMSTATE_UINT8(state.control, ISAParallelState),
 500         VMSTATE_INT32(state.irq_pending, ISAParallelState),
 501         VMSTATE_INT32(state.epp_timeout, ISAParallelState),
 502         VMSTATE_END_OF_LIST()
 503     }
 504 };
 505
 506 static int parallel_can_receive(void *opaque)
 507 {
 508      return 1;
 509 }
 510
 511 static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
 512 {
 513     static int index;
 514     ISADevice *isadev = ISA_DEVICE(dev);
 515     ISAParallelState *isa = ISA_PARALLEL(dev);
 516     ParallelState *s = &isa->state;
 517     int base;
 518     uint8_t dummy;
 519
 520     if (!qemu_chr_fe_backend_connected(&s->chr)) {
 521         error_setg(errp, "Can't create parallel device, empty char device");
 522         return;
 523     }
 524
 525     if (isa->index == -1) {
 526         isa->index = index;
 527     }
 528     if (isa->index >= MAX_PARALLEL_PORTS) {
 529         error_setg(errp, "Max. supported number of parallel ports is %d.",
 530                    MAX_PARALLEL_PORTS);
 531         return;
 532     }
 533     if (isa->iobase == -1) {
 534         isa->iobase = isa_parallel_io[isa->index];
 535     }
 536     index++;
 537
 538     base = isa->iobase;
 539     isa_init_irq(isadev, &s->irq, isa->isairq);
 540     qemu_register_reset(parallel_reset, s);
 541
 542     qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL,
 543                              NULL, NULL, s, NULL, true);
 544     if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
 545         s->hw_driver = 1;
 546         s->status = dummy;
 547     }
 548
 549     isa_register_portio_list(isadev, &s->portio_list, base,
 550                              (s->hw_driver
 551                               ? &isa_parallel_portio_hw_list[0]
 552                               : &isa_parallel_portio_sw_list[0]),
 553                              s, "parallel");
 554 }
 555
 556 /* Memory mapped interface */
 557 static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
 558 {
 559     ParallelState *s = opaque;
 560
 561     return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
 562 }
 563
 564 static void parallel_mm_writeb (void *opaque,
 565                                 hwaddr addr, uint32_t value)
 566 {
 567     ParallelState *s = opaque;
 568
 569     parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
 570 }
 571
 572 static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
 573 {
 574     ParallelState *s = opaque;
 575
 576     return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
 577 }
 578
 579 static void parallel_mm_writew (void *opaque,
 580                                 hwaddr addr, uint32_t value)
 581 {
 582     ParallelState *s = opaque;
 583
 584     parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
 585 }
 586
 587 static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
 588 {
 589     ParallelState *s = opaque;
 590
 591     return parallel_ioport_read_sw(s, addr >> s->it_shift);
 592 }
 593
 594 static void parallel_mm_writel (void *opaque,
 595                                 hwaddr addr, uint32_t value)
 596 {
 597     ParallelState *s = opaque;
 598
 599     parallel_ioport_write_sw(s, addr >> s->it_shift, value);
 600 }
 601
 602 static const MemoryRegionOps parallel_mm_ops = {
 603     .old_mmio = {
 604         .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
 605         .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
 606     },
 607     .endianness = DEVICE_NATIVE_ENDIAN,
 608 };
 609
 610 /* If fd is zero, it means that the parallel device uses the console */
 611 bool parallel_mm_init(MemoryRegion *address_space,
 612                       hwaddr base, int it_shift, qemu_irq irq,
 613                       Chardev *chr)
 614 {
 615     ParallelState *s;
 616
 617     s = g_malloc0(sizeof(ParallelState));
 618     s->irq = irq;
 619     qemu_chr_fe_init(&s->chr, chr, &error_abort);
 620     s->it_shift = it_shift;
 621     qemu_register_reset(parallel_reset, s);
 622
 623     memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
 624                           "parallel", 8 << it_shift);
 625     memory_region_add_subregion(address_space, base, &s->iomem);
 626     return true;
 627 }
 628
 629 static Property parallel_isa_properties[] = {
 630     DEFINE_PROP_UINT32("index", ISAParallelState, index,   -1),
 631     DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase,  -1),
 632     DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
 633     DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
 634     DEFINE_PROP_END_OF_LIST(),
 635 };
 636
 637 static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
 638 {
 639     DeviceClass *dc = DEVICE_CLASS(klass);
 640
 641     dc->realize = parallel_isa_realizefn;
 642     dc->vmsd = &vmstate_parallel_isa;
 643     dc->props = parallel_isa_properties;
 644     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 645 }
 646
 647 static const TypeInfo parallel_isa_info = {
 648     .name          = TYPE_ISA_PARALLEL,
 649     .parent        = TYPE_ISA_DEVICE,
 650     .instance_size = sizeof(ISAParallelState),
 651     .class_init    = parallel_isa_class_initfn,
 652 };
 653
 654 static void parallel_register_types(void)
 655 {
 656     type_register_static(&parallel_isa_info);
 657 }
 658
 659 type_init(parallel_register_types)