target-microblaze/mmu.c

   1 /*
   2  *  Microblaze MMU emulation for qemu.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21
  22 #define D(x)
  23
  24 static unsigned int tlb_decode_size(unsigned int f)
  25 {
  26     static const unsigned int sizes[] = {
  27         1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
  28         1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
  29     };
  30     assert(f < ARRAY_SIZE(sizes));
  31     return sizes[f];
  32 }
  33
  34 static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
  35 {
  36     struct microblaze_mmu *mmu = &env->mmu;
  37     unsigned int tlb_size;
  38     uint32_t tlb_tag, end, t;
  39
  40     t = mmu->rams[RAM_TAG][idx];
  41     if (!(t & TLB_VALID))
  42         return;
  43
  44     tlb_tag = t & TLB_EPN_MASK;
  45     tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
  46     end = tlb_tag + tlb_size;
  47
  48     while (tlb_tag < end) {
  49         tlb_flush_page(env, tlb_tag);
  50         tlb_tag += TARGET_PAGE_SIZE;
  51     }
  52 }
  53
  54 static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
  55 {
  56     struct microblaze_mmu *mmu = &env->mmu;
  57     unsigned int i;
  58     uint32_t t;
  59
  60     if (newpid & ~0xff)
  61         qemu_log("Illegal rpid=%x\n", newpid);
  62
  63     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
  64         /* Lookup and decode.  */
  65         t = mmu->rams[RAM_TAG][i];
  66         if (t & TLB_VALID) {
  67             if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
  68                 mmu_flush_idx(env, i);
  69         }
  70     }
  71 }
  72
  73 /* rw - 0 = read, 1 = write, 2 = fetch.  */
  74 unsigned int mmu_translate(struct microblaze_mmu *mmu,
  75                            struct microblaze_mmu_lookup *lu,
  76                            target_ulong vaddr, int rw, int mmu_idx)
  77 {
  78     unsigned int i, hit = 0;
  79     unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
  80     unsigned int tlb_size;
  81     uint32_t tlb_tag, tlb_rpn, mask, t0;
  82
  83     lu->err = ERR_MISS;
  84     for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
  85         uint32_t t, d;
  86
  87         /* Lookup and decode.  */
  88         t = mmu->rams[RAM_TAG][i];
  89         D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
  90         if (t & TLB_VALID) {
  91             tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
  92             if (tlb_size < TARGET_PAGE_SIZE) {
  93                 qemu_log("%d pages not supported\n", tlb_size);
  94                 abort();
  95             }
  96
  97             mask = ~(tlb_size - 1);
  98             tlb_tag = t & TLB_EPN_MASK;
  99             if ((vaddr & mask) != (tlb_tag & mask)) {
 100                 D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
 101                            i, vaddr & mask, tlb_tag & mask));
 102                 continue;
 103             }
 104             if (mmu->tids[i]
 105                 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
 106                 D(qemu_log("TLB %d pid=%x != tid=%x\n",
 107                            i, mmu->regs[MMU_R_PID], mmu->tids[i]));
 108                 continue;
 109             }
 110
 111             /* Bring in the data part.  */
 112             d = mmu->rams[RAM_DATA][i];
 113             tlb_ex = d & TLB_EX;
 114             tlb_wr = d & TLB_WR;
 115
 116             /* Now lets see if there is a zone that overrides the protbits.  */
 117             tlb_zsel = (d >> 4) & 0xf;
 118             t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
 119             t0 &= 0x3;
 120
 121             if (tlb_zsel > mmu->c_mmu_zones) {
 122                 qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
 123                 t0 = 1; /* Ignore.  */
 124             }
 125
 126             if (mmu->c_mmu == 1) {
 127                 t0 = 1; /* Zones are disabled.  */
 128             }
 129
 130             switch (t0) {
 131                 case 0:
 132                     if (mmu_idx == MMU_USER_IDX)
 133                         continue;
 134                     break;
 135                 case 2:
 136                     if (mmu_idx != MMU_USER_IDX) {
 137                         tlb_ex = 1;
 138                         tlb_wr = 1;
 139                     }
 140                     break;
 141                 case 3:
 142                     tlb_ex = 1;
 143                     tlb_wr = 1;
 144                     break;
 145                 default: break;
 146             }
 147
 148             lu->err = ERR_PROT;
 149             lu->prot = PAGE_READ;
 150             if (tlb_wr)
 151                 lu->prot |= PAGE_WRITE;
 152             else if (rw == 1)
 153                 goto done;
 154             if (tlb_ex)
 155                 lu->prot |=PAGE_EXEC;
 156             else if (rw == 2) {
 157                 goto done;
 158             }
 159
 160             tlb_rpn = d & TLB_RPN_MASK;
 161
 162             lu->vaddr = tlb_tag;
 163             lu->paddr = tlb_rpn;
 164             lu->size = tlb_size;
 165             lu->err = ERR_HIT;
 166             lu->idx = i;
 167             hit = 1;
 168             goto done;
 169         }
 170     }
 171 done:
 172     D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
 173               vaddr, rw, tlb_wr, tlb_ex, hit));
 174     return hit;
 175 }
 176
 177 /* Writes/reads to the MMU's special regs end up here.  */
 178 uint32_t mmu_read(CPUMBState *env, uint32_t rn)
 179 {
 180     unsigned int i;
 181     uint32_t r;
 182
 183     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
 184         qemu_log("MMU access on MMU-less system\n");
 185         return 0;
 186     }
 187
 188     switch (rn) {
 189         /* Reads to HI/LO trig reads from the mmu rams.  */
 190         case MMU_R_TLBLO:
 191         case MMU_R_TLBHI:
 192             if (!(env->mmu.c_mmu_tlb_access & 1)) {
 193                 qemu_log("Invalid access to MMU reg %d\n", rn);
 194                 return 0;
 195             }
 196
 197             i = env->mmu.regs[MMU_R_TLBX] & 0xff;
 198             r = env->mmu.rams[rn & 1][i];
 199             if (rn == MMU_R_TLBHI)
 200                 env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
 201             break;
 202         case MMU_R_PID:
 203         case MMU_R_ZPR:
 204             if (!(env->mmu.c_mmu_tlb_access & 1)) {
 205                 qemu_log("Invalid access to MMU reg %d\n", rn);
 206                 return 0;
 207             }
 208             r = env->mmu.regs[rn];
 209             break;
 210         default:
 211             r = env->mmu.regs[rn];
 212             break;
 213     }
 214     D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
 215     return r;
 216 }
 217
 218 void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 219 {
 220     unsigned int i;
 221     D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
 222
 223     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
 224         qemu_log("MMU access on MMU-less system\n");
 225         return;
 226     }
 227
 228     switch (rn) {
 229         /* Writes to HI/LO trig writes to the mmu rams.  */
 230         case MMU_R_TLBLO:
 231         case MMU_R_TLBHI:
 232             i = env->mmu.regs[MMU_R_TLBX] & 0xff;
 233             if (rn == MMU_R_TLBHI) {
 234                 if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
 235                     qemu_log("invalidating index %x at pc=%x\n",
 236                              i, env->sregs[SR_PC]);
 237                 env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
 238                 mmu_flush_idx(env, i);
 239             }
 240             env->mmu.rams[rn & 1][i] = v;
 241
 242             D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
 243             break;
 244         case MMU_R_ZPR:
 245             if (env->mmu.c_mmu_tlb_access <= 1) {
 246                 qemu_log("Invalid access to MMU reg %d\n", rn);
 247                 return;
 248             }
 249
 250             /* Changes to the zone protection reg flush the QEMU TLB.
 251                Fortunately, these are very uncommon.  */
 252             if (v != env->mmu.regs[rn]) {
 253                 tlb_flush(env, 1);
 254             }
 255             env->mmu.regs[rn] = v;
 256             break;
 257         case MMU_R_PID:
 258             if (env->mmu.c_mmu_tlb_access <= 1) {
 259                 qemu_log("Invalid access to MMU reg %d\n", rn);
 260                 return;
 261             }
 262
 263             if (v != env->mmu.regs[rn]) {
 264                 mmu_change_pid(env, v);
 265                 env->mmu.regs[rn] = v;
 266             }
 267             break;
 268         case MMU_R_TLBSX:
 269         {
 270             struct microblaze_mmu_lookup lu;
 271             int hit;
 272
 273             if (env->mmu.c_mmu_tlb_access <= 1) {
 274                 qemu_log("Invalid access to MMU reg %d\n", rn);
 275                 return;
 276             }
 277
 278             hit = mmu_translate(&env->mmu, &lu,
 279                                 v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
 280             if (hit) {
 281                 env->mmu.regs[MMU_R_TLBX] = lu.idx;
 282             } else
 283                 env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
 284             break;
 285         }
 286         default:
 287             env->mmu.regs[rn] = v;
 288             break;
 289    }
 290 }
 291
 292 void mmu_init(struct microblaze_mmu *mmu)
 293 {
 294     int i;
 295     for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
 296         mmu->regs[i] = 0;
 297     }
 298 }