2 * QEMU lowRISC Ibex UART device
4 * Copyright (c) 2020 Western Digital
6 * For details check the documentation here:
7 * https://docs.opentitan.org/hw/ip/uart/doc/
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
29 #include "hw/char/ibex_uart.h"
31 #include "hw/qdev-clock.h"
32 #include "hw/qdev-properties.h"
33 #include "migration/vmstate.h"
35 #include "qemu/module.h"
37 static void ibex_uart_update_irqs(IbexUartState
*s
)
39 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_TX_WATERMARK_MASK
) {
40 qemu_set_irq(s
->tx_watermark
, 1);
42 qemu_set_irq(s
->tx_watermark
, 0);
45 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_RX_WATERMARK_MASK
) {
46 qemu_set_irq(s
->rx_watermark
, 1);
48 qemu_set_irq(s
->rx_watermark
, 0);
51 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_TX_EMPTY_MASK
) {
52 qemu_set_irq(s
->tx_empty
, 1);
54 qemu_set_irq(s
->tx_empty
, 0);
57 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_RX_OVERFLOW_MASK
) {
58 qemu_set_irq(s
->rx_overflow
, 1);
60 qemu_set_irq(s
->rx_overflow
, 0);
64 static int ibex_uart_can_receive(void *opaque
)
66 IbexUartState
*s
= opaque
;
68 if (s
->uart_ctrl
& R_CTRL_RX_ENABLE_MASK
) {
75 static void ibex_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
77 IbexUartState
*s
= opaque
;
78 uint8_t rx_fifo_level
= (s
->uart_fifo_ctrl
& R_FIFO_CTRL_RXILVL_MASK
)
79 >> R_FIFO_CTRL_RXILVL_SHIFT
;
83 s
->uart_status
&= ~R_STATUS_RXIDLE_MASK
;
84 s
->uart_status
&= ~R_STATUS_RXEMPTY_MASK
;
86 if (size
> rx_fifo_level
) {
87 s
->uart_intr_state
|= R_INTR_STATE_RX_WATERMARK_MASK
;
90 ibex_uart_update_irqs(s
);
93 static gboolean
ibex_uart_xmit(GIOChannel
*chan
, GIOCondition cond
,
96 IbexUartState
*s
= opaque
;
97 uint8_t tx_fifo_level
= (s
->uart_fifo_ctrl
& R_FIFO_CTRL_TXILVL_MASK
)
98 >> R_FIFO_CTRL_TXILVL_SHIFT
;
101 /* instant drain the fifo when there's no back-end */
102 if (!qemu_chr_fe_backend_connected(&s
->chr
)) {
108 s
->uart_status
&= ~R_STATUS_TXFULL_MASK
;
109 s
->uart_status
|= R_STATUS_TXEMPTY_MASK
;
110 s
->uart_intr_state
|= R_INTR_STATE_TX_EMPTY_MASK
;
111 s
->uart_intr_state
&= ~R_INTR_STATE_TX_WATERMARK_MASK
;
112 ibex_uart_update_irqs(s
);
116 ret
= qemu_chr_fe_write(&s
->chr
, s
->tx_fifo
, s
->tx_level
);
120 memmove(s
->tx_fifo
, s
->tx_fifo
+ ret
, s
->tx_level
);
124 guint r
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
132 /* Clear the TX Full bit */
133 if (s
->tx_level
!= IBEX_UART_TX_FIFO_SIZE
) {
134 s
->uart_status
&= ~R_STATUS_TXFULL_MASK
;
137 /* Disable the TX_WATERMARK IRQ */
138 if (s
->tx_level
< tx_fifo_level
) {
139 s
->uart_intr_state
&= ~R_INTR_STATE_TX_WATERMARK_MASK
;
143 if (s
->tx_level
== 0) {
144 s
->uart_status
|= R_STATUS_TXEMPTY_MASK
;
145 s
->uart_intr_state
|= R_INTR_STATE_TX_EMPTY_MASK
;
148 ibex_uart_update_irqs(s
);
152 static void uart_write_tx_fifo(IbexUartState
*s
, const uint8_t *buf
,
155 uint64_t current_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
156 uint8_t tx_fifo_level
= (s
->uart_fifo_ctrl
& R_FIFO_CTRL_TXILVL_MASK
)
157 >> R_FIFO_CTRL_TXILVL_SHIFT
;
159 if (size
> IBEX_UART_TX_FIFO_SIZE
- s
->tx_level
) {
160 size
= IBEX_UART_TX_FIFO_SIZE
- s
->tx_level
;
161 qemu_log_mask(LOG_GUEST_ERROR
, "ibex_uart: TX FIFO overflow");
164 memcpy(s
->tx_fifo
+ s
->tx_level
, buf
, size
);
167 if (s
->tx_level
> 0) {
168 s
->uart_status
&= ~R_STATUS_TXEMPTY_MASK
;
171 if (s
->tx_level
>= tx_fifo_level
) {
172 s
->uart_intr_state
|= R_INTR_STATE_TX_WATERMARK_MASK
;
173 ibex_uart_update_irqs(s
);
176 if (s
->tx_level
== IBEX_UART_TX_FIFO_SIZE
) {
177 s
->uart_status
|= R_STATUS_TXFULL_MASK
;
180 timer_mod(s
->fifo_trigger_handle
, current_time
+
181 (s
->char_tx_time
* 4));
184 static void ibex_uart_reset(DeviceState
*dev
)
186 IbexUartState
*s
= IBEX_UART(dev
);
188 s
->uart_intr_state
= 0x00000000;
189 s
->uart_intr_state
= 0x00000000;
190 s
->uart_intr_enable
= 0x00000000;
191 s
->uart_ctrl
= 0x00000000;
192 s
->uart_status
= 0x0000003c;
193 s
->uart_rdata
= 0x00000000;
194 s
->uart_fifo_ctrl
= 0x00000000;
195 s
->uart_fifo_status
= 0x00000000;
196 s
->uart_ovrd
= 0x00000000;
197 s
->uart_val
= 0x00000000;
198 s
->uart_timeout_ctrl
= 0x00000000;
202 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ 230400) * 10;
204 ibex_uart_update_irqs(s
);
207 static uint64_t ibex_uart_get_baud(IbexUartState
*s
)
211 baud
= ((s
->uart_ctrl
& R_CTRL_NCO_MASK
) >> 16);
212 baud
*= clock_get_hz(s
->f_clk
);
218 static uint64_t ibex_uart_read(void *opaque
, hwaddr addr
,
221 IbexUartState
*s
= opaque
;
222 uint64_t retvalue
= 0;
226 retvalue
= s
->uart_intr_state
;
229 retvalue
= s
->uart_intr_enable
;
232 qemu_log_mask(LOG_GUEST_ERROR
,
233 "%s: wdata is write only\n", __func__
);
237 retvalue
= s
->uart_ctrl
;
240 retvalue
= s
->uart_status
;
244 retvalue
= s
->uart_rdata
;
245 if (s
->uart_ctrl
& R_CTRL_RX_ENABLE_MASK
) {
246 qemu_chr_fe_accept_input(&s
->chr
);
248 s
->uart_status
|= R_STATUS_RXIDLE_MASK
;
249 s
->uart_status
|= R_STATUS_RXEMPTY_MASK
;
253 qemu_log_mask(LOG_GUEST_ERROR
,
254 "%s: wdata is write only\n", __func__
);
258 retvalue
= s
->uart_fifo_ctrl
;
261 retvalue
= s
->uart_fifo_status
;
263 retvalue
|= s
->tx_level
& 0x1F;
265 qemu_log_mask(LOG_UNIMP
,
266 "%s: RX fifos are not supported\n", __func__
);
270 retvalue
= s
->uart_ovrd
;
271 qemu_log_mask(LOG_UNIMP
,
272 "%s: ovrd is not supported\n", __func__
);
275 retvalue
= s
->uart_val
;
276 qemu_log_mask(LOG_UNIMP
,
277 "%s: val is not supported\n", __func__
);
280 retvalue
= s
->uart_timeout_ctrl
;
281 qemu_log_mask(LOG_UNIMP
,
282 "%s: timeout_ctrl is not supported\n", __func__
);
285 qemu_log_mask(LOG_GUEST_ERROR
,
286 "%s: Bad offset 0x%"HWADDR_PRIx
"\n", __func__
, addr
);
293 static void ibex_uart_write(void *opaque
, hwaddr addr
,
294 uint64_t val64
, unsigned int size
)
296 IbexUartState
*s
= opaque
;
297 uint32_t value
= val64
;
302 s
->uart_intr_state
&= ~value
;
303 ibex_uart_update_irqs(s
);
306 s
->uart_intr_enable
= value
;
307 ibex_uart_update_irqs(s
);
310 s
->uart_intr_state
|= value
;
311 ibex_uart_update_irqs(s
);
315 s
->uart_ctrl
= value
;
317 if (value
& R_CTRL_NF_MASK
) {
318 qemu_log_mask(LOG_UNIMP
,
319 "%s: UART_CTRL_NF is not supported\n", __func__
);
321 if (value
& R_CTRL_SLPBK_MASK
) {
322 qemu_log_mask(LOG_UNIMP
,
323 "%s: UART_CTRL_SLPBK is not supported\n", __func__
);
325 if (value
& R_CTRL_LLPBK_MASK
) {
326 qemu_log_mask(LOG_UNIMP
,
327 "%s: UART_CTRL_LLPBK is not supported\n", __func__
);
329 if (value
& R_CTRL_PARITY_EN_MASK
) {
330 qemu_log_mask(LOG_UNIMP
,
331 "%s: UART_CTRL_PARITY_EN is not supported\n",
334 if (value
& R_CTRL_PARITY_ODD_MASK
) {
335 qemu_log_mask(LOG_UNIMP
,
336 "%s: UART_CTRL_PARITY_ODD is not supported\n",
339 if (value
& R_CTRL_RXBLVL_MASK
) {
340 qemu_log_mask(LOG_UNIMP
,
341 "%s: UART_CTRL_RXBLVL is not supported\n", __func__
);
343 if (value
& R_CTRL_NCO_MASK
) {
344 uint64_t baud
= ibex_uart_get_baud(s
);
346 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ baud
) * 10;
350 qemu_log_mask(LOG_GUEST_ERROR
,
351 "%s: status is read only\n", __func__
);
355 qemu_log_mask(LOG_GUEST_ERROR
,
356 "%s: rdata is read only\n", __func__
);
359 uart_write_tx_fifo(s
, (uint8_t *) &value
, 1);
363 s
->uart_fifo_ctrl
= value
;
365 if (value
& R_FIFO_CTRL_RXRST_MASK
) {
366 qemu_log_mask(LOG_UNIMP
,
367 "%s: RX fifos are not supported\n", __func__
);
369 if (value
& R_FIFO_CTRL_TXRST_MASK
) {
374 qemu_log_mask(LOG_GUEST_ERROR
,
375 "%s: fifo_status is read only\n", __func__
);
379 s
->uart_ovrd
= value
;
380 qemu_log_mask(LOG_UNIMP
,
381 "%s: ovrd is not supported\n", __func__
);
384 qemu_log_mask(LOG_GUEST_ERROR
,
385 "%s: val is read only\n", __func__
);
388 s
->uart_timeout_ctrl
= value
;
389 qemu_log_mask(LOG_UNIMP
,
390 "%s: timeout_ctrl is not supported\n", __func__
);
393 qemu_log_mask(LOG_GUEST_ERROR
,
394 "%s: Bad offset 0x%"HWADDR_PRIx
"\n", __func__
, addr
);
398 static void ibex_uart_clk_update(void *opaque
)
400 IbexUartState
*s
= opaque
;
402 /* recompute uart's speed on clock change */
403 uint64_t baud
= ibex_uart_get_baud(s
);
405 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ baud
) * 10;
408 static void fifo_trigger_update(void *opaque
)
410 IbexUartState
*s
= opaque
;
412 if (s
->uart_ctrl
& R_CTRL_TX_ENABLE_MASK
) {
413 ibex_uart_xmit(NULL
, G_IO_OUT
, s
);
417 static const MemoryRegionOps ibex_uart_ops
= {
418 .read
= ibex_uart_read
,
419 .write
= ibex_uart_write
,
420 .endianness
= DEVICE_NATIVE_ENDIAN
,
421 .impl
.min_access_size
= 4,
422 .impl
.max_access_size
= 4,
425 static int ibex_uart_post_load(void *opaque
, int version_id
)
427 IbexUartState
*s
= opaque
;
429 ibex_uart_update_irqs(s
);
433 static const VMStateDescription vmstate_ibex_uart
= {
434 .name
= TYPE_IBEX_UART
,
436 .minimum_version_id
= 1,
437 .post_load
= ibex_uart_post_load
,
438 .fields
= (VMStateField
[]) {
439 VMSTATE_UINT8_ARRAY(tx_fifo
, IbexUartState
,
440 IBEX_UART_TX_FIFO_SIZE
),
441 VMSTATE_UINT32(tx_level
, IbexUartState
),
442 VMSTATE_UINT64(char_tx_time
, IbexUartState
),
443 VMSTATE_TIMER_PTR(fifo_trigger_handle
, IbexUartState
),
444 VMSTATE_UINT32(uart_intr_state
, IbexUartState
),
445 VMSTATE_UINT32(uart_intr_enable
, IbexUartState
),
446 VMSTATE_UINT32(uart_ctrl
, IbexUartState
),
447 VMSTATE_UINT32(uart_status
, IbexUartState
),
448 VMSTATE_UINT32(uart_rdata
, IbexUartState
),
449 VMSTATE_UINT32(uart_fifo_ctrl
, IbexUartState
),
450 VMSTATE_UINT32(uart_fifo_status
, IbexUartState
),
451 VMSTATE_UINT32(uart_ovrd
, IbexUartState
),
452 VMSTATE_UINT32(uart_val
, IbexUartState
),
453 VMSTATE_UINT32(uart_timeout_ctrl
, IbexUartState
),
454 VMSTATE_END_OF_LIST()
458 static Property ibex_uart_properties
[] = {
459 DEFINE_PROP_CHR("chardev", IbexUartState
, chr
),
460 DEFINE_PROP_END_OF_LIST(),
463 static void ibex_uart_init(Object
*obj
)
465 IbexUartState
*s
= IBEX_UART(obj
);
467 s
->f_clk
= qdev_init_clock_in(DEVICE(obj
), "f_clock",
468 ibex_uart_clk_update
, s
);
469 clock_set_hz(s
->f_clk
, IBEX_UART_CLOCK
);
471 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->tx_watermark
);
472 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->rx_watermark
);
473 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->tx_empty
);
474 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->rx_overflow
);
476 memory_region_init_io(&s
->mmio
, obj
, &ibex_uart_ops
, s
,
477 TYPE_IBEX_UART
, 0x400);
478 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->mmio
);
481 static void ibex_uart_realize(DeviceState
*dev
, Error
**errp
)
483 IbexUartState
*s
= IBEX_UART(dev
);
485 s
->fifo_trigger_handle
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
486 fifo_trigger_update
, s
);
488 qemu_chr_fe_set_handlers(&s
->chr
, ibex_uart_can_receive
,
489 ibex_uart_receive
, NULL
, NULL
,
493 static void ibex_uart_class_init(ObjectClass
*klass
, void *data
)
495 DeviceClass
*dc
= DEVICE_CLASS(klass
);
497 dc
->reset
= ibex_uart_reset
;
498 dc
->realize
= ibex_uart_realize
;
499 dc
->vmsd
= &vmstate_ibex_uart
;
500 device_class_set_props(dc
, ibex_uart_properties
);
503 static const TypeInfo ibex_uart_info
= {
504 .name
= TYPE_IBEX_UART
,
505 .parent
= TYPE_SYS_BUS_DEVICE
,
506 .instance_size
= sizeof(IbexUartState
),
507 .instance_init
= ibex_uart_init
,
508 .class_init
= ibex_uart_class_init
,
511 static void ibex_uart_register_types(void)
513 type_register_static(&ibex_uart_info
);
516 type_init(ibex_uart_register_types
)