2 * USB xHCI controller for system-bus interface
3 * Based on hcd-echi-sysbus.c
5 * SPDX-FileCopyrightText: 2020 Xilinx
6 * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "qemu/osdep.h"
11 #include "hw/qdev-properties.h"
12 #include "migration/vmstate.h"
14 #include "qapi/error.h"
15 #include "hcd-xhci-sysbus.h"
16 #include "hw/acpi/aml-build.h"
19 static void xhci_sysbus_intr_raise(XHCIState
*xhci
, int n
, bool level
)
21 XHCISysbusState
*s
= container_of(xhci
, XHCISysbusState
, xhci
);
23 qemu_set_irq(s
->irq
[n
], level
);
26 void xhci_sysbus_reset(DeviceState
*dev
)
28 XHCISysbusState
*s
= XHCI_SYSBUS(dev
);
30 device_legacy_reset(DEVICE(&s
->xhci
));
33 static void xhci_sysbus_realize(DeviceState
*dev
, Error
**errp
)
35 XHCISysbusState
*s
= XHCI_SYSBUS(dev
);
38 object_property_set_link(OBJECT(&s
->xhci
), "host", OBJECT(s
), NULL
);
39 object_property_set_bool(OBJECT(&s
->xhci
), "realized", true, &err
);
41 error_propagate(errp
, err
);
44 s
->irq
= g_new0(qemu_irq
, s
->xhci
.numintrs
);
45 qdev_init_gpio_out_named(dev
, s
->irq
, SYSBUS_DEVICE_GPIO_IRQ
,
48 s
->xhci
.as
= g_malloc0(sizeof(AddressSpace
));
49 address_space_init(s
->xhci
.as
, s
->xhci
.dma_mr
, NULL
);
51 s
->xhci
.as
= &address_space_memory
;
54 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->xhci
.mem
);
57 static void xhci_sysbus_instance_init(Object
*obj
)
59 XHCISysbusState
*s
= XHCI_SYSBUS(obj
);
61 object_initialize_child(obj
, "xhci-core", &s
->xhci
, TYPE_XHCI
);
62 qdev_alias_all_properties(DEVICE(&s
->xhci
), obj
);
64 object_property_add_link(obj
, "dma", TYPE_MEMORY_REGION
,
65 (Object
**)&s
->xhci
.dma_mr
,
66 qdev_prop_allow_set_link_before_realize
,
67 OBJ_PROP_LINK_STRONG
);
68 s
->xhci
.intr_update
= NULL
;
69 s
->xhci
.intr_raise
= xhci_sysbus_intr_raise
;
72 void xhci_sysbus_build_aml(Aml
*scope
, uint32_t mmio
, unsigned int irq
)
74 Aml
*dev
= aml_device("XHCI");
75 Aml
*crs
= aml_resource_template();
77 aml_append(crs
, aml_memory32_fixed(mmio
, XHCI_LEN_REGS
, AML_READ_WRITE
));
78 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
79 AML_EXCLUSIVE
, &irq
, 1));
81 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0D10")));
82 aml_append(dev
, aml_name_decl("_CRS", crs
));
83 aml_append(scope
, dev
);
86 static Property xhci_sysbus_props
[] = {
87 DEFINE_PROP_UINT32("intrs", XHCISysbusState
, xhci
.numintrs
, XHCI_MAXINTRS
),
88 DEFINE_PROP_UINT32("slots", XHCISysbusState
, xhci
.numslots
, XHCI_MAXSLOTS
),
89 DEFINE_PROP_END_OF_LIST(),
92 static const VMStateDescription vmstate_xhci_sysbus
= {
93 .name
= "xhci-sysbus",
95 .fields
= (VMStateField
[]) {
96 VMSTATE_STRUCT(xhci
, XHCISysbusState
, 1, vmstate_xhci
, XHCIState
),
101 static void xhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
103 DeviceClass
*dc
= DEVICE_CLASS(klass
);
105 dc
->reset
= xhci_sysbus_reset
;
106 dc
->realize
= xhci_sysbus_realize
;
107 dc
->vmsd
= &vmstate_xhci_sysbus
;
108 device_class_set_props(dc
, xhci_sysbus_props
);
111 static const TypeInfo xhci_sysbus_info
= {
112 .name
= TYPE_XHCI_SYSBUS
,
113 .parent
= TYPE_SYS_BUS_DEVICE
,
114 .instance_size
= sizeof(XHCISysbusState
),
115 .class_init
= xhci_sysbus_class_init
,
116 .instance_init
= xhci_sysbus_instance_init
119 static void xhci_sysbus_register_types(void)
121 type_register_static(&xhci_sysbus_info
);
124 type_init(xhci_sysbus_register_types
);